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1. 发明专利

JP2003152702A INFORMATION PROCESSING APPARATUS 审中-公开
公开(公告)号：JP2003152702A
公开(公告)日：2003-05-23
申请号：JP2001350936
申请日：2001-11-16
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： ENDO TAKASHI , KAMINAGA MASAHIRO , WATANABE TAKASHI , NAKADA KUNIHIKO , TSUKAMOTO TAKU
IPC分类号： H04L9/10 , G06F7/48 , G06F7/501 , G06F21/00 , H04L9/08
摘要： PROBLEM TO BE SOLVED: To provide an information processing apparatus that prevents secret information processed the inside thereof from being estimated from leak information such as a consumed current or the like. SOLUTION: This invention provides the image processing apparatus as a means to solve the problem above includes: at least a key generating device for automatically generating key information; an encryption device for using the key information to encrypt data; a register for recording a plurality of encrypted data with the key information used to encrypt the data; and an arithmetic unit that receives the data expressed with the key information for the encryption and new key information, calculates them, and encrypts the arithmetic result by the received new key and outputs the encrypted data. The image processing apparatus can process the data therein under an encrypted data expression.

2. 发明专利

JP2003114618A DATA PROCESSOR 审中-公开
公开(公告)号：JP2003114618A
公开(公告)日：2003-04-18
申请号：JP2001308154
申请日：2001-10-04
申请人： HITACHI LTD
发明人： KAMINAGA MASAHIRO , ENDO TAKASHI , WATANABE TAKASHI , NAKADA KUNIHIKO , TSUKAMOTO TAKU , KOBAYASHI SEIJI
IPC分类号： G06F7/72 , G09C1/00
摘要： PROBLEM TO BE SOLVED: To make fast processing conventionally actualized by operating two computing elements in parallel in a Montgomery residue arithmetic circuit. SOLUTION: The mentioned processing can be mathematically composed and actualized by a single computing element.

3. 发明专利

JPH01266635A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH01266635A
公开(公告)日：1989-10-24
申请号：JP9608388
申请日：1988-04-19
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： MIWA YOSHIYUKI , KINO TAKESHI , KEIDA HARUO , NAKADA KUNIHIKO , YASUDA HAJIME
IPC分类号： G06F11/22
摘要： PURPOSE:To shorten the device test time related to a separate signal and to facilitate the generation of a test pattern by providing a gate which can output selectively the separate signal between modules to a common internal bus. CONSTITUTION:When an output gate 20 is in an ON-state, an interrupting signal INT12 from a DMA control part 12 is supplied to a bus DB, and can be confirmed directly on the outside through a common internal bus 14. Therefore, a single test of the control part 12 is facilitated. Also, a switching control signal CONT12 of a high level is latched by an FF 23 and allows a multiplexer 22 to output and select latch data of an FF 21. In this state, a test signal TEST12 is latched by the FF 21, supplied to a CPU 11, and its operating state is confirmed. Also, a single test from the outside against an interruption sequence of the CPU 11 is facilitated.

4. 发明专利

JPS6352255A BUS ARBITER 失效
公开(公告)号：JPS6352255A
公开(公告)日：1988-03-05
申请号：JP19535086
申请日：1986-08-22
申请人： HITACHI LTD
发明人： NAKADA KUNIHIKO
IPC分类号： G06F13/362 , G06F13/364
摘要： PURPOSE:To shift a bus occupation right at a high speed by performing the shift control of the bus occupation right so as to secure synchronism with the end timing of a bus cycle in accordance with the rule of priority set among bus masters. CONSTITUTION:A bus arbiter ARB samples request signals REQ1 and REQ2 which are used for request of occupation of a local bus synchronously with the timing by which bus cycle final timing signals TL1 and TL2 produced by a bus master CPU and a DMAC are set at low levels, i.e., under active states. Then the occupation right of the local bus is decided according to the rule of priority set among bus masters as well as the result of said sampling. Prescribed acknowledge signals ACK1 and ACK2 are controlled to active states synchronously with the timing by which signals TL1 and TL2 are set at high levels, i.e., under inactive states.

5. 发明专利

JPS60233731A DIGITAL INFORMATION PROCESSOR 失效
公开(公告)号：JPS60233731A
公开(公告)日：1985-11-20
申请号：JP8940984
申请日：1984-05-07
申请人： HITACHI LTD
发明人： NAKADA KUNIHIKO
IPC分类号： G06F9/22 , G06F9/26
摘要： PURPOSE:To stop the execution of a program instruction with an optional timing by providing a gate circuit which is controlled by a prescribed control signal at an output part of an instruction decoder circuit. CONSTITUTION:The output signal of a control matrix ROM is delivered via NOR gate circuits G1-G4 respectively. These gate circuits are controllingly opened and closed by the output signal of an OR gate circuit which receives a delay signal DL which requests a temporary stop of actions, a reflesh signal RF, a bus request signal BR, a sleeve signal SL, etc. An action stop request signal is produced with the timing where a microinstruction action of one or several steps is through to a program instruction which is under execution. Then the request signal is supplied to the circuit G5. Thus the output of the circuit G5 is set at ''1'' and at a high impedance, and the circuits G1-G4 are fixed at ''0''. These gate circuits can be held in a non-operation state as long as the action stop request signals are continuously produced.

6. 发明专利

JP2002334317A INFORMATION PROCESSOR 失效
公开(公告)号：JP2002334317A
公开(公告)日：2002-11-22
申请号：JP2001138073
申请日：2001-05-09
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： WATANABE TAKASHI , ENDO TAKASHI , KAMINAGA MASAHIRO , NAKADA KUNIHIKO , NARIYOSHI YUICHIRO , TANIMOTO CHIAKI
IPC分类号： G06K19/10 , G06F11/00 , G06F21/00 , G06K19/07
摘要： PROBLEM TO BE SOLVED: To provide a malfunction detecting device so that an information processor can properly continue, even if malfunctioning, or stop processing. SOLUTION: The information processor having received branch destination information executes conditional branching depending upon the branch destination information and processes data correspondingly. At this time, the process corresponding to the conditional branch destination is executed at the conditional branch destination for data J other than process data I, so that it can be decided afterward through verification whether or not the conditional branching is correctly completed.

7. 发明专利

JPH04262568A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH04262568A
公开(公告)日：1992-09-17
申请号：JP4447291
申请日：1991-02-15
申请人： HITACHI LTD , HITACHI MICRO SYSTEM KK
发明人： OCHIAI TATSUO , MIYAZAKI KENJI , NAKADA KUNIHIKO , FUKADA KAORU
IPC分类号： G01R31/28 , H01L21/66 , H01L21/822 , H01L21/8238 , H01L27/04 , H01L27/092
摘要： PURPOSE:To provide a technique for accurately diagnosing an operation of a P-channel type MOSFET contained in a bus driver coupled to a bus to be precharged. CONSTITUTION:An N-channel type MOSFET 15 is provided. The MOSFET 15 is turned ON in synchronization with an initial clock CLK of a bus cycle thereby to discharge an inner data bus BUS, and hence the bus BUS is set to a low level. Accordingly, a high level is output from a bus driver 17b in a peripheral functional module 19 in this state. The state of the bus BUS at that time is checked by a CPU 18 thereby to diagnose an operation of a P- channel type MOSFET included in the driver 17b.

8. 发明专利

JPH04148343A MICROCOMPUTER 失效
公开(公告)号：JPH04148343A
公开(公告)日：1992-05-21
申请号：JP27310090
申请日：1990-10-11
申请人： HITACHI LTD
发明人： SASAKI HISAO , AKAO YASUSHI , NAKADA KUNIHIKO , KURIHARA TOSHIHIKO
IPC分类号： G06F11/22 , G06F15/78
摘要： PURPOSE:To shorten a test pattern preparing time for a device test by independently performing access of each built-in circuit module from the outside unconnectedly with a central processing unit according to the setting of a test mode. CONSTITUTION:Interface means 13 and 14 which can be turned into signal inputting/outputting states for performing access of the circuit module from the outside in the test mode, are connected inside common buses 10 - 12 to which a central processing unit 2 and plural circuit modules are connected. Also, a one-chip microcomputer 1 is constituted by providing a controlling means 4 which pauses the operation of the central processing unit 2 according to the setting of the test mode, and separates the central processing unit 2 from the inside command buses 10 - 12. Thus, the device test of a semiconductor integrated circuit can be operated by a module unit, and the test pattern preparing time for the device test can be shortened.

9. 发明专利

JPH01279656A DATA PROCESSING DEVICE 失效
公开(公告)号：JPH01279656A
公开(公告)日：1989-11-09
申请号：JP10996288
申请日：1988-05-06
申请人： HITACHI LTD
发明人： SASAKI HISAO , MIYAZAKI KENJI , BABA SHIRO , NAKADA KUNIHIKO , AKAO YASUSHI
IPC分类号： H04L29/06 , G06F7/00 , H04L13/00
摘要： PURPOSE:To perform multifunctional serial communication by providing two kinds, at least, of controlling means among HDLC procedure, BI-SYNC procedure and start-stop synchronizing procedure, and selecting them alternatively according to the instruction of a processor. CONSTITUTION:Three sets of transmitting procedure mode registers MR1-MR3 for giving the instruction to make a transmission controller 26 and a reception controller 16 select what control logic of the start-stop synchronizing procedure, the HDLC procedure or the BI-SYMC procedure are provided. The transmitting procedure mode registers MR1-MR3 are initialized by data to be supplied from a CPU 1 through an internal bus 8 respectively. The reception controller 16 is provided with control logic for adapting the operation of a receiving unit 10 to the procedure of the start-stop synchronizing procedure, the HDLC procedure and the BI-SYNC procedure, and said control logic is selected alternatively according to the set state of the above-mentioned transmitting procedure mode registers MR1-MR3.

10. 发明专利

JPS63293658A COMMUNICATION PROCESSOR 失效
公开(公告)号：JPS63293658A
公开(公告)日：1988-11-30
申请号：JP12831187
申请日：1987-05-27
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： MIYAZAKI KENJI , MURAKAMI TAKASHI , NAKADA KUNIHIKO , OKOCHI TOSHIO
IPC分类号： H04L29/10 , G06F13/00 , G06F13/28
摘要： PURPOSE:To improve the transmitting throughput of a communication system by transmitting the transfer request signal and the transfer request confirmation signal for both reception data and status between a direct memory access (DMA) control part and a serial communication control part. CONSTITUTION:Both the transfer request signal and the transfer request confirmation signal for reception data and reception status are transmitted between a DMA control part DMAC of a communication processor NPU and a serial communication control part SIO. The communication data and the reception status of plural frames transferred continuously are transferred to a random access memory RAM for temporary storage via the DMAC without requiring the processing carried out by a central processing part for each frame.

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