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1. 发明专利

JPH01295181A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH01295181A
公开(公告)日：1989-11-28
申请号：JP12382588
申请日：1988-05-23
申请人： HITACHI LTD
发明人： MIYAZAKI KENJI , NAKADA KUNIHIKO
IPC分类号： G01R31/317 , G01R31/28 , H01L21/822 , H01L27/04
摘要： PURPOSE:To easily and accurately confirm operation characteristics of a logic module, etc., including a sequence circuit by providing a 1st shift register which outputs test data in order and a 2nd shift register which inputs test output signals in order. CONSTITUTION:Multiplexers MX1-MX3 select external input signals supplies through corresponding input terminals I1-Im when a logic module LM1 is in normal operation mode or shift output signals of corresponding input shift registers SR1-SR3 in test mode and send them to a logic circuit LC1. In the test mode, the test output signals outputted by the logic circuit LC1 are inputted to 2nd corresponding shift registers SR4-SR6 and sent to an external testing device through a module bus MB1. Consequently, the dynamic characteristics of the logic module, etc., including the sequence circuit are easily and accurately confirmed.

2. 发明专利

JPS6451533A SYSTEM FOR INTERRUPTING DATA PROCESSING SYSTEM 失效
公开(公告)号：JPS6451533A
公开(公告)日：1989-02-27
申请号：JP20809387
申请日：1987-08-24
申请人： HITACHI LTD
发明人： MIYAZAKI KENJI
IPC分类号： G06F9/48 , G06F13/24
摘要： PURPOSE:To attain reduction in the size of a chip by setting interruption request signals to one at every module, outputting bits showing the kind of modules on an internal bus as the high-order part of an interruption vector and outputting bits showing the kind of interruption factors in a self inner part as the low-order part of the interruption vector. CONSTITUTION:When there are interruption requests from respective modules in accordance with peripheral modules PHM1 and PHM2-PHMn, all of which are integrated in the chip, an interruption controller IRC generates the high- order part of the vector to be jumped and outputs it on the address bus BUS. On the other hand, the peripheral modules PHM1-PHMn which have been integrated in the chip respectively have the output terminals of the interruption request signals and they have the interruption factors in a register or the like in the modules. When the interruption factors occur, the peripheral modules PHM1-PHMn output the interruption request signals REQ, receive allowance signals ACK from the interruption controller IRC and output the bits showing the kind of the interruption factors which the register or the like have on the address bus BUS.

3. 发明专利

JPS63294146A COMMUNICATION CONTROL EQUIPMENT 失效
公开(公告)号：JPS63294146A
公开(公告)日：1988-11-30
申请号：JP12819687
申请日：1987-05-27
申请人： HITACHI LTD
发明人： MIYAZAKI KENJI
IPC分类号： G06F13/00 , H03M13/00 , H03M13/09 , H04L1/00 , H04L1/06 , H04L7/04 , H04L29/02
摘要： PURPOSE:To improve the communication efficiency of serial communication equipment, by operating a shift register by using clock signals which are used for operating a cyclic redundancy check (CRC) calculator. CONSTITUTION:A CRC calculator 5 is installed to serial communication equipment 11 and, at the same time, the CRC calculator 5 is operated by means of the system clock 9 of a receiving-side microprocessor system 10. Therefore, since it becomes unnecessary to shift received CRC codes to the CRC calculator 5 by means of receiving clocks supplied for a MODEM, interruption of CRC calculation caused by discontinuation of receiving clocks can be prevented. In addition, insertion of dummy data after CRC codes on the transmitting side and CRC calculation with software by the microprocessor 10 on the receiving side become unnecessary. Therefore, the communication efficiency of the serial communication equipment 11 is improved.

4. 发明专利

JPH0357334A DATA COMMUNICATION CONTROL EQUIPMENT 失效
公开(公告)号：JPH0357334A
公开(公告)日：1991-03-12
申请号：JP19148589
申请日：1989-07-26
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： OSHIBA MASAFUMI , MIYAZAKI KENJI
IPC分类号： H04L1/00 , H04L29/02 , H04L29/08
摘要： PURPOSE:To disregard a pseudo data due to a flag bit inversion by providing a frame discrimination means neglecting a frame when a word length between flags to be in vicinity mutually is equal to a unit word length of a communication data. CONSTITUTION:A line control section 6 is provided with a frame discrimination means 6b as a function to discriminate a frame fetched from a reception line RL. The means 6b discriminates that a word length between flags located close to each other is equal to a communication data unit word length (1 byte) and informs it to a CPU 10 that the frame is disregarded. Thus, the CPU 10 recognizes that the reception data is not a normal data, activates a write inhibiting signal 14 to block that the information included in the input frame is written in a FIFO buffer 12. Moreover, when the word length between flags located close to each other is less than the unit word length of the communication data, the means 6b disregards even a short frame. Thus, even when a false data is caused due to bit inversion of a flag, the pseudo data is neglected and also the short frame is disregarded.

5. 发明专利

JPH0290382A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH0290382A
公开(公告)日：1990-03-29
申请号：JP24357888
申请日：1988-09-28
申请人： HITACHI LTD
发明人： MIYAZAKI KENJI
IPC分类号： G06F1/08 , G06F13/42 , G06F15/78
摘要： PURPOSE:To improve an operation efficiency as a whole by operating asynchronously plural function modules whose maximum operation frequencies are different, and also, executing a synchronized control for a data transfer between the function modules. CONSTITUTION:A single chip microcomputer 1 incorporates a CPU module 2, a RAM module 3, a timer counter module 4, a serial input/output circuit module 5, a DMAC module 6 and a DMAC module 7. In this state, to the modules 2, 3, 4, 6 and 7, different operation clock signals phi0, phi3, phii, phi1 and phi2 are supplied through a frequency dividing circuit 11 from the output of a clock pulse generator 10 to which an external clock signal CLK1 and the modules execute an asynchronous operation. To the input/output circuit module 5, an independent clock signal CLK2 is applied and a data transfer which passes through a silicon pack plane bus 8 being an asynchronous bus is brought to synchronized control. In such a manner, the operation efficiency as a whole can be improved.

6. 发明专利

JPH0257036A PARALLEL SYNCHRONIZING CIRCUIT 失效
公开(公告)号：JPH0257036A
公开(公告)日：1990-02-26
申请号：JP20905488
申请日：1988-08-23
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： MIYAZAKI KENJI , ASANO MICHIO , MURAKAMI TAKASHI
IPC分类号： H04L13/08 , H04L7/00 , H04L13/18
摘要： PURPOSE:To cause a transfer clock frequency to be close to an operating clock frequency by successively instructing the operation of plural synchronous circuits for reception synchronously to the effective change of a transfer clock and operating the plural synchronous circuits for reception in parallel. CONSTITUTION:An allotment circuit 40 generates and allots allotting signals RXCa and RXCb, whose high levels are not overlapped, synchronously to the effective edge change of a transfer clock RXC with being alternatively changed at every cycle of a transfer clock TXC. One allotting signal RXCa to be generated in this circuit 40 is supplied to a clock input terminal CK of FFs 23 and 27 and the other allotting signal RXCb is supplied to the clock input terminal of FFs 30 and 34. The allotting signals RXCa and RXCb are alternatively controlled to the high level synchronously to the cycle of the transfer clock RXC. Accordingly, the instruction of synchronizing operation to synchronous circuits 21 and 22 is alternatively given at every cycle of the transfer clock RXC. Thus, the respective synchronizing circuits 21 and 22 can define the almost two cycles of the transfer clock RXC as a maximum synchronization operatable period to 1 bit data.

7. 发明专利

JPH0215356A SIGNAL BUS SEPARATING STRUCTURE 失效
公开(公告)号：JPH0215356A
公开(公告)日：1990-01-19
申请号：JP16629888
申请日：1988-07-04
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： SHIZUNO MITSUYOSHI , MIYAZAKI KENJI
IPC分类号： G06F13/36
摘要： PURPOSE:To reduce the unrequired load of a signal bus by providing the title structure with a multiplexer for selectively connecting a pheripheral signal bus to which a bus slave module is connected to a bus master module. CONSTITUTION:The title structure duplexly includes the 1st peripheral signal bus 4 connecting a parallel I/O circuit 2, a serial I/O circuit 3, etc., and the 2nd peripheral signal bus 7 connecting a timer 5, a memory 6, or the like. The multiplexer 8 for selectively connecting a bus 4 or 7 connected to a bus slave to be accessed by a CPU 1 to the CPU 1 is also included to constitute the structure. Since the peripheral signal buses are duplexed and the CPU 1 is selectively connected by the multiplexer 8, the effective load of the signal bus to be driven at the time of accessing can be reduced almost to a half of the whole load in accordance with the multiplication of the peripheral signal buses.

8. 发明专利

JPS63313940A COMMUNICATION CONTROL DEVICE 失效
公开(公告)号：JPS63313940A
公开(公告)日：1988-12-22
申请号：JP14902787
申请日：1987-06-17
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： OSHIBA MASAFUMI , MIYAZAKI KENJI
IPC分类号： H04L29/06 , G06F13/00 , H04L7/08 , H04L13/00 , H04L13/16
摘要： PURPOSE:To simplify a control sequence at the time of a transmission by setting a synchronizing pattern and an idle pattern respectively in separate registers, at the time of the start up of a system. CONSTITUTION:Before starting the transmission, the synchronizing pattern and the idle pattern are previously set in a flag pattern register 13 and an idle pattern register 15 respectively. Then, when a transmission enable signal to instruct the transmission is inputted from a microprocessor, immediately the leading idle pattern in the idle pattern register 15 is transferred to a shift register 12, and the idle pattern is transmitted. Then, a transmission data is transmitted from a system memory side, and at the point of time when it comes into an FIFO 11, the transmission of the idle pattern is interrupted, and instead of it, the synchronizing pattern of two bytes in the flag pattern register 13 is outputted.

9. 发明专利

JPS63307568A DATA PROCESSOR 失效
公开(公告)号：JPS63307568A
公开(公告)日：1988-12-15
申请号：JP14306987
申请日：1987-06-10
申请人： HITACHI LTD
发明人： SASAKI HISAO , BABA SHIRO , AKAO YASUSHI , MIYAZAKI KENJI , OKOCHI TOSHIO
IPC分类号： G06F13/38 , G06F13/28
摘要： PURPOSE:To shorten a data processing time by securing such constitution a direct memory access controller DMAC carries out frame switch processing for changes of data storing addresses, etc., based on the data supplied from a serial channel. CONSTITUTION:A signal line is provided to inform the recognition of data showing the end of a frame serving as a group of information to be exchanged to a DMAC containing a chain function when said data is recognized by a serial channel SIC. The data are divided for each frame and transferred recognizably to a memory DM from a channel SIC. In this case, the DMAC carries out the frame switch processing for changes of the data storing address based on the data given from the signal line. Thus no intervention of a CPU is needed and the data processing time is extremely shortened.

10. 发明专利

JP2006179028A Integrated multimedia system 有权
标题翻译：综合多媒体系统
公开(公告)号：JP2006179028A
公开(公告)日：2006-07-06
申请号：JP2006068018
申请日：2006-03-13
申请人： Equator Technologies Inc , Hitachi Ltd , イクエイターテクノロジーズ、インコーポレイテッド , 株式会社日立製作所
发明人： BAKER DAVID , BASOGLU CHRISTOPHER , CUTLER BENJAMIN , DEELEY RICHARD , GERVASIO GREGORIO , KAWAGUCHI ATSUO , KOJIMA KEIJI , LEE WOOBIN , MIYAZAKI KENJI , MUNDKUR YATIN , NAIK VINAY , NISHIOKA KIYOKAZU , NOJIRI TORU , O'DONNELL JOHN , PADALKAR SARANG
IPC分类号： G06F13/28 , G06T1/20 , G06F13/10 , G06F13/12 , G06F13/36 , G06F15/78 , G06T15/00
CPC分类号： G06F13/102 , G06F13/124 , G06T15/005
摘要： PROBLEM TO BE SOLVED: To provide a multimedia system realizing highly efficient data transfer. SOLUTION: In this integrated multimedia system having a multimedia processor installed inside an integrated circuit, a data transfer switch is arranged inside the multimedia processor to be connected to a second processor transferring data to various modules of the multimedia processor. A data streamer is connected to the data transfer switch and configured to schedule simultaneous data transfers between a plurality of modules disposed in the multimedia processor in accordance with the corresponding channel allocations. COPYRIGHT: (C)2006,JPO&NCIPI

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