专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2010079678A Device for controlling storage switching 审中-公开
标题翻译：用于控制存储开关的设备
公开(公告)号：JP2010079678A
公开(公告)日：2010-04-08
申请号：JP2008248428
申请日：2008-09-26
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： WAKABAYASHI SHUNICHI , SAKAI KOSUKE , NONAKA YUSUKE
IPC分类号： G06F12/00 , G06F3/06
CPC分类号： G06F11/2069 , G06F3/0617 , G06F3/0635 , G06F3/0647 , G06F3/067 , G06F11/2071 , G06F11/2082
摘要： PROBLEM TO BE SOLVED: To perform storage system switching without troubling a user and without substantially stopping the receipt of I/O from a host. SOLUTION: A storage system includes a CTL 31 which controls switching from a pre-switching system 3A to a post-switching system 3B. The CTL 31 includes a confirmation part which confirms whether connection between the pre-switching system 3A and the post-switching system 3B is possible; a determination part which determines whether switching from the system 3A to the system 3B is possible; a takeover information transfer part which transfers takeover information possessed by the system 3A to the system 3B; a user data transfer part which transfers user data of the system 3A to the system 3B; and a switching execution part which allows the receipt of I/O from the host 1 in the system 3B. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：执行存储系统切换，而不会使用户困扰，并且基本上不停止从主机接收I / O。解决方案：存储系统包括控制从预切换系统3A切换到后切换系统3B的CTL 31。 CTL31包括一个确认部分，该确认部分确认预切换系统3A和切换后系统3B之间的连接是否可能; 确定部件，其确定是否可以从系统3A切换到系统3B; 接收信息传送部件，其将系统3A拥有的接管信息传送到系统3B; 将系统3A的用户数据传送到系统3B的用户数据传送部; 以及允许从系统3B中的主机1接收I / O的切换执行部。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2009032205A Storage system for transferring system information element 有权
标题翻译：用于传输系统信息元素的存储系统
公开(公告)号：JP2009032205A
公开(公告)日：2009-02-12
申请号：JP2007198140
申请日：2007-07-30
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： UENO KOICHI , NAGATA KOJI , NONAKA YUSUKE
IPC分类号： G06F3/06 , G06F13/10
CPC分类号： G06F3/0647 , G06F3/0604 , G06F3/067 , G06F11/2092
摘要： PROBLEM TO BE SOLVED: To enable a user to set system information in a transfer destination storage system with less burdens. SOLUTION: A first storage system provided with a first storage device includes a first interface device to be connected to a second interface device provided in a second storage system. A first controller of the first storage system reads out a system information element in first system information (information about the configuration and control of the first storage system) from a first system area (storage area not provided to hosts, in the first storage device) and transfers the system information element or a system information element resulting from changing it, to the second storage system via the first interface device. The system information element is recorded in a second system area of a second storage device provided in the second storage system. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了使用户能够以较少的负担在传送目的地存储系统中设置系统信息。提供有第一存储装置的第一存储系统包括要连接到设置在第二存储系统中的第二接口装置的第一接口装置。第一存储系统的第一控制器从第一系统区域（未提供给主机的存储区域，在第一存储设备中）读出第一系统信息中的系统信息元素（关于第一存储系统的配置和控制的信息）并且将系统信息元素或将其改变而产生的系统信息元素经由第一接口设备传送到第二存储系统。系统信息元素被记录在设置在第二存储系统中的第二存储装置的第二系统区域中。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2005339191A Remote copy with worm guarantee 有权
标题翻译：远程复制与WORM保证
公开(公告)号：JP2005339191A
公开(公告)日：2005-12-08
申请号：JP2004157034
申请日：2004-05-27
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： NONAKA YUSUKE , MATSUNAMI NAOTO , NISHIMOTO SATORU , MIZUNO YOICHI
IPC分类号： G06F13/10 , G06F3/06 , G06F11/20 , G06F12/00 , G06F12/14 , G06F12/16 , G06F21/24
CPC分类号： G06F11/2069
摘要： PROBLEM TO BE SOLVED: To carry out remote copying of data in a storage system A to a storage system B without having a user be conscious of whether or not the data is WORM (Write Once Read Many) data.
SOLUTION: When carrying out setting such that the data stored in a volume in the storage system A is copied to a volume in the storage system B, a first controller in the storage system A judges whether an attribute attached to the volume in the storage system A is an attribute allowing reference and update, or an attribute allowing reference but no updates. If the volume is attached with the attribute allowing reference but no updates, the first controller instructs a second controller in the storage system B to attach an attribute allowing reference but no updates to the volume in the storage system B.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了使存储系统A中的数据远程复制到存储系统B而不用户意识到数据是否是WORM（一次写入一次读取）数据。解决方案：当进行将存储在存储系统A中的卷中存储的数据复制到存储系统B中的卷的设置时，存储系统A中的第一控制器判断附加到卷的属性存储系统A是允许引用和更新的属性，或允许引用但不更新的属性。如果卷附带有允许引用但不进行更新的属性，则第一控制器指示存储系统B中的第二控制器附加允许引用但不更新存储系统B中的卷的属性。版权：（ C）2006，JPO＆NCIPI

4. 发明专利

JP2004326638A Cache unification mechanism between nas devices 审中-公开
公开(公告)号：JP2004326638A
公开(公告)日：2004-11-18
申请号：JP2003123141
申请日：2003-04-28
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： TSUKIJI KENICHI , MATSUNAMI NAOTO , NONAKA YUSUKE
IPC分类号： G06F3/06 , G06F12/00
摘要： PROBLEM TO BE SOLVED: To eliminate the disadvantage that, conventionally, when a server carries out failover due to a fault before data from a client is reflected on an HDD, rewriting of the data from the client is required, that periodic fault detection is conducted between servers, and that much time is thus required for detection.
SOLUTION: The cache unification mechanism has DAFS in file access and unifies cache on a server to hold data, and comprises a means of executing rewriting the data on the server on the occurrence of a fault. Thus, even if the DAFS device is down by a fault before the data from the client is reflected on a HDD, an application does not detect an abnormality after failover is carried out and can ensure the consistency of the data.
COPYRIGHT: (C)2005,JPO&NCIPI

5. 发明专利

JP2003158263A METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：JP2003158263A
公开(公告)日：2003-05-30
申请号：JP2001358969
申请日：2001-11-26
申请人： HITACHI LTD
发明人： YANAGIDA YOHEI , ICHINOSE KATSUHIKO , NONAKA YUSUKE
IPC分类号： H01L29/43 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/49 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To simplify a process for manufacturing a MISFET formed through a dummy gate process. SOLUTION: A gate groove 5 is provided to an oxide film 4 doped with n-type impurities, n-type semiconductor regions 6 functioning as a source and a drain are formed by solid phase diffusion, and furthermore the gate groove 5 is filled up with a high dielectric material 7 and a low-resistance metal film 8 for the formation of a gate insulating film and a gate electrode.

6. 发明专利

JP2003007978A Semiconductor integrated-circuit device and method of manufacturing the same 有权
标题翻译：半导体集成电路装置及其制造方法
公开(公告)号：JP2003007978A
公开(公告)日：2003-01-10
申请号：JP2001183098
申请日：2001-06-18
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： OTSUKA FUMIO , NONAKA YUSUKE , SHIMAMOTO SATOSHI , OMORI SOHEI , KAZAMA HIDEO
IPC分类号： H01L21/768 , H01L21/822 , H01L21/8244 , H01L27/04 , H01L27/10 , H01L27/11
CPC分类号： H01L27/11 , H01L27/1104
摘要： PROBLEM TO BE SOLVED: To enhance the performance of a semiconductor integrated-circuit device in which a storage internode capacitance for an SRAM and an element comprising an analog capacitance are formed on a single substrate. SOLUTION: A plug P1 is formed on a silicon oxide film 21 on a pair of n-channel MISFETs in the memory formation region (SRAM), a local interconnection LIc (MOc) which connects respective gate electrodes to respective drains of the pair of n-channel MISFETs is formed in the upper part of the film 21 and the plug P1, and a capacitance insulating film 23 and an upper electrode 24 are formed in its upper part. Alternatively, a local interconnection ILc (MOc), a capacitance insulating film 23 and an upper electrode 24 are formed on a silicon oxide film 21 and a plug P1 in the film in an analog capacitance formation region (analog capacitor) in the same process as the local interconnection, the capacitance insulating film and the upper electrode which are formed in the memory cell formation region.
摘要翻译：要解决的问题：为了提高半导体集成电路器件的性能，其中在单个衬底上形成有用于SRAM的存储节间电容和包括模拟电容的元件。解决方案：在存储器形成区域（SRAM）中的一对n沟道MISFET上的氧化硅膜21上形成插塞P1，将各个栅极连接到该对n的各个漏极的局部互连LIc（MOc）沟道MISFET形成在膜21的上部和插头P1中，并且电容绝缘膜23和上电极24形成在其上部。或者，在与模拟电容形成区域（模拟电容器）中的膜中的氧化硅膜21和插塞P1上形成局部互连ILc（MOc），电容绝缘膜23和上电极24，形成在存储单元形成区域中的局部互连，电容绝缘膜和上电极。

7. 发明专利

JP2001077361A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURING METHOD 失效
公开(公告)号：JP2001077361A
公开(公告)日：2001-03-23
申请号：JP25398699
申请日：1999-09-08
申请人： HITACHI LTD
发明人： MIYAMOTO MASABUMI , NONAKA YUSUKE , MITANI SHINICHIRO , YANAGISAWA YASUNOBU , SAITO TOMOHIRO
IPC分类号： H01L29/78 , H01L21/8238 , H01L27/092 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To reduce the junction capacity of source/drain regions and to realize a high speed device operation by introducing the impurity of a conduction type opposite to a semiconductor substrate by oblique ion implantation and forming a counter dope layer by bringing it into contact with the lower par of a low concentration semiconductor region. SOLUTION: In an n-channel-type MISFETQ1, a p-type counter dope layer 8 whose impurity concentration is substantially low is formed below a low concentration semiconductor region 3 by oblique ion implantation. Thus, the junction capacity of the low concentration semiconductor region 3 can be reduced. The lateral invasion distance of a side wall spacer 7 from a spacer end to a channel direction can be adjusted at the angle of oblique ion implantation. Junction capacity between the low concentration semiconductor region 3 and the semiconductor substrate 1 can be reduced in a range that does not affect the short channel characteristics and therefore a high speed device operation can be executed.

8. 发明专利

JP2000196070A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JP2000196070A
公开(公告)日：2000-07-14
申请号：JP36674398
申请日：1998-12-24
申请人： HITACHI LTD
发明人： NONAKA YUSUKE , MITANI SHINICHIRO
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8238 , H01L27/092
摘要： PROBLEM TO BE SOLVED: To make an element minute, without affecting the properties of a MISFET, and suppress increase in parasitic resistance of the element accompanying micronization, and also obtain shallow joining of the semiconductor regions to serve as the source and the drain. SOLUTION: The gate electrode 7 is made via a gate insulating film 6 on the element formation region of the main surface of a p-type semiconductor substrate 1, and then semiconductor regions to serve as the source and the drain are made, self-alignedly to the gate electrode, in the element-forming regions of the substrate. Next, an insulating film is made on the element-forming region at the main face of the substrate and on an element isolating region, and the insulting film 11 is left on the element isolating region through selective anisotropic etching, and also a sidewall spacer A, on the sidewall of the gate electrode 7, and a connection hole 11B, on the semiconductor region, are made. Moreover, a conductive film 16 which is lower in sheet resistance than the semiconductor region is made on the main face of the semiconductor substrate including the connection hole, and then the insulating film in other region excluding the inside of the connection hole is removed.

9. 发明专利

JP2000114210A POLISHING DEVICE, POLISHING METHOD, AND MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2000114210A
公开(公告)日：2000-04-21
申请号：JP28445498
申请日：1998-10-06
申请人： HITACHI LTD
发明人： KONISHI NOBUHIRO , NONAKA YUSUKE
IPC分类号： H01L21/304
摘要： PROBLEM TO BE SOLVED: To improve the flatness of the surface of a semiconductor film which is polished by a chemical-mechanical polishing method. SOLUTION: When a semiconductor film 19 formed on a semiconductor substrate 3S is polished by a chemical-mechanical polishing method, a polishing is performed in a state where the polishing selective ratio of the semiconductor film 19 and an underlying insulating film 17 is made relatively large at the beginning step. Then, the selective ratio is made relatively smaller in the middle step to equally polish the semiconductor 19 and the insulating film 17 independently of the kind of a film to be polished.

10. 发明专利

JPH10173035A SEMICONDUCTOR INTEGRATED CIRCUIT AND DESIGN METHOD THEREOF 失效
公开(公告)号：JPH10173035A
公开(公告)日：1998-06-26
申请号：JP32937996
申请日：1996-12-10
申请人： HITACHI LTD
发明人： NARUI SEIJI , NONAKA YUSUKE
IPC分类号： H01L21/76 , H01L21/304 , H01L21/3205 , H01L21/822 , H01L23/52 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To improve the surface flatness of a semiconductor substrate for a semiconductor integrated circuit device having element isolating shallow regions. SOLUTION: A semiconductor integrated circuit device has a semiconductor substrate 1 having element isolating shallow trench regions 2 formed by the chemical-mechanical polishing. A semiconductor region 3 surrounded with each shallow trench region 2 includes a semiconductor region 3a formed on an element forming region A; the region 3a acting as an active region of an MISFET in the semiconductor integrated circuit device and it also includes a dummy semiconductor region 3b formed on a semiconductor region B of the semiconductor substrate 1, not so as to form an isolated semiconductor region. The spacing of the semiconductor regions 3 is 100μm or less.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式