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1. 发明专利

JPH0498685A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0498685A
公开(公告)日：1992-03-31
申请号：JP21399690
申请日：1990-08-13
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD , AKITA DENSHI KK
发明人： NAKAZATO SHINJI , AISAKA YASUHIRO , ITO SHIN , KAWAKAMI MAKOTO , SAKAMOTO MASATAKA
IPC分类号： G11C11/413 , G11C11/408 , H03K19/0175
摘要： PURPOSE:To enable correction without fail in a short developing period by uniquely correcting transmission delay dispersion in the logic signal of the semiconductor integrated circuit device according to the size of a time constant in a protection circuit. CONSTITUTION:Electrostatic destruction proofing circuits 11-1n are operated also as delay circuits to address signals A1-An inputted from terminals pad P1-Pn to a peripheral memory circuit 2 according to the time constant due to resistors Ri1-Rin and MOS capacitors M1-Mn. In this case, the respective resistors Ri1-Rin of the electrostatic destruction proofing circuits 11-1n are respectively set to have the time constant for correcting the timing dispersion of the address signals A1-An generated by the internal circuit such as the peripheral memory circuit 2 or the like. Thus, speed can effectively be improved by suppressing the dispersion of access time for a BiCMOS high-speed SRAM.

2. 发明专利

JPH0474386A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH0474386A
公开(公告)日：1992-03-09
申请号：JP18712890
申请日：1990-07-17
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD , AKITA DENSHI KK
发明人： NAKAZATO SHINJI , AISAKA YASUHIRO , ITO SHIN , KAWAKAMI MAKOTO , SAKAMOTO MASATAKA
IPC分类号： G11C11/413
摘要： PURPOSE:To prevent the breakdown of storage data generated at the time of write of data by generating an internal write pulse at the timing for avoiding it from an error selection period of a memory cell generated by switching of data output state. CONSTITUTION:In a state that a read/write control circuit 11 is selected by a chip selecting signal CS, after a prescribed time elapses after a prescribed address Ain is given from the outside, write enable WE is allowed to fall from a non-active level of a high level to an active level of a low level. After a prescribed transfer delay time after a fall of this write enable WE, a data output control signal Doc is allowed to fall from the non-active level to the active level. In connection therewith, after a prescribed transfer delay time after a fall of write enable WE, an internal write pulse Dwp is allowed to fall from the non-active level to the active level. In such a way, the breakdown of storage data generated at the time of write of data executed by setting a binary output state to a high impedance state can be prevented.

3. 发明专利

JPH06120807A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH06120807A
公开(公告)日：1994-04-28
申请号：JP32854791
申请日：1991-12-12
申请人： HITACHI LTD , AKITA DENSHI KK
发明人： SAKAMOTO MASATAKA , TOKIDA KENSUKE , KAWAKAMI MAKOTO
IPC分类号： G11C11/417 , G11C11/414 , H01L21/8249 , H01L27/06 , H03K19/08
摘要： PURPOSE:To provide a semiconductor integrated circuit which contains a TTL circuit while attaining the power consumption and also to attain a high speed operation. CONSTITUTION:The driving stage CMOS inverter circuits Q3 and Q4 receive the output signals which are converted into the CMOS levels of a first stage CMOS inverter circuits Q1 and Q2 which receive the input signals of TTL levels. An output transistor TR T1 which produces the output signal of a high level is driven by the output signals of the circuits Q1 and Q2. Meanwhile an output MOSFET Q6 which produces the output signal of a low level is driven by the output signals of the circuits Q3 and Q4. Furthermore a P channel MOSFET Q1 and a MOSFET Q5 which generates the base current of the TR T1 are provided on both circuits Q1 and Q2 by reception of the output signal of the first stage or the driving stage CMOS inverter circuit.

4. 发明专利

JPH07130181A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH07130181A
公开(公告)日：1995-05-19
申请号：JP29607493
申请日：1993-11-01
申请人： HITACHI LTD , AKITA DENSHI KK
发明人： KAWAKAMI MAKOTO , MAKUTA KIICHI
IPC分类号： G11C11/413 , H01L21/3205 , H01L21/8244 , H01L23/52 , H01L27/11
摘要： PURPOSE:To suppress that a power noise is transmitted to a power supplying path of an input buffer by providing all or one part of the power supplying path to a data output buffer independently of path to the other internal circuit. CONSTITUTION:Supplied X address signals AX0-AXi are signals of a TTL level, an initial inverter V1 of unit X address buffer UXB0-UXBi has a deviating logical threshold level suitable for the TTL level by changing conductance of a MOSFET P1 and N1. On the other hand, power voltage for operation of a third and fourth step inverters V3, V4 constituting the buffers UXB0-UXBi are the same power voltage VCC2, ground potential VSS2 as the other internal circuits except a data output buffer, but power voltage of inverters V1, V2 are independent voltage VCC3, VSS3. Therefore, the compression and malfunction of noise margin of the X address buffer caused by a power noise when an unit data output buffer becomes a simultaneous operation state can be prevented.

5. 发明专利

JPH06244707A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH06244707A
公开(公告)日：1994-09-02
申请号：JP6148191
申请日：1991-03-26
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD , AKITA DENSHI KK
发明人： SAKAMOTO MASATAKA , NAKAZATO SHINJI , AISAKA YASUHIRO , ITO SHIN , KAWAKAMI MAKOTO
IPC分类号： H03K3/0233 , H03K3/023 , H03K5/08 , H03K19/003
摘要： PURPOSE:To avoide a trouble generated due to the transmission of an intermediate potential by transmitting the intermediate potential outputted by the logical circuit of a preceding stage side as an 'H' or 'L' binary logical signal by the logical circuit of the succeeding stage side which receives the output of the logical circuit of the preceding stage side. CONSTITUTION:Logical circuits 31 and 32 multiple-connected in order to form a delay circuit 30 are constituted so that potentials Vt1 and Vt2 being the boundary of the 'H' and 'L' binary logical level can be different from each other. Thus, even when the signal of the intermediate potential is included in a signal inputted from an outside, and the intermediate potential is outputted from the logical circuit 31 of the preceding stage side, the intermediate potential from the logical circuit of the preceding stage side is not the intermediate potential of the logical circuit 32 of the succeeding stage side. The intermediate potential from the logical circuit of the preceding stage side is transmitted as a logical signal in an 'H' area, and outputted by the logical circuit 32 of the succeeding stage side. Therefore, even when the intermediate potential which is not the 'H' or 'L' binary logical potential is generated, the trouble generated due to the potential is generated, the trouble generated due to the transmission of the intermediate potential to the other part can be prevented.

6. 发明专利

JP2010203309A Steam turbine moving blade and method for manufacturing the same 审中-公开
标题翻译：蒸汽涡轮叶片及其制造方法
公开(公告)号：JP2010203309A
公开(公告)日：2010-09-16
申请号：JP2009049014
申请日：2009-03-03
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： KAWAKAMI MAKOTO
IPC分类号： F01D5/06 , C23C4/04 , F01D5/28 , F01D5/30 , F01D25/00
摘要： PROBLEM TO BE SOLVED: To provide an axial entry type steam turbine moving blade eliminating turbulence of a main steam flow due to leak steam, and method for manufacturing the same.
SOLUTION: The steam turbine moving blade 5 includes a plurality of axial entry type stages where the turbine moving blade 5 is inserted in the blade groove 10 of a rotor disk 4a of a turbine rotor 4 in an axial direction. The steam turbine moving blade 5 is provided with a wearing coating 20 formed on at least one of an outer surface of a rotor hook 15 which is a convex part of the blade groove 10 and an outer surface of a blade hook 14 which is a convex part of the turbine moving blade 5, the turbine moving blade 5 assembled so as to fill the gap between the rotor hook 15 and the blade hook 14 by being inserted in the blade groove 10 while cutting the excessive thickness of the wearing coating 20, and a balance hole 9 disposed on the rotor disk 4a and having dimensions corresponding to the design values of the gap.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种消除由于蒸汽泄漏引起的主蒸汽流紊乱的轴向入口式蒸汽轮机动叶片及其制造方法。蒸汽轮机动叶片5包括多个轴向入口级，其中涡轮机动叶片5沿轴向插入涡轮转子4的转子盘4a的叶片槽10中。蒸汽轮机动叶片5设置有形成在作为叶片槽10的凸部的转子钩15的外表面和作为凸部的叶片钩14的外表面中的至少一个上的磨损涂层20 涡轮机动叶片5的一部分，涡轮机移动叶片5组装成通过插入刀片槽10中而填充转子钩15和刀片钩14之间的间隙，同时切割磨损涂层20的过度的厚度，平衡孔9，其设置在转子盘4a上并且具有与间隙的设计值对应的尺寸。版权所有（C）2010，JPO＆INPIT

7. 发明专利

JP2001203336A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2001203336A
公开(公告)日：2001-07-27
申请号：JP2000009118
申请日：2000-01-18
申请人： HITACHI LTD , AKITA ELECTRONICS CO LTD
发明人： KAWAKAMI MAKOTO
IPC分类号： G11C11/404 , G11C11/401 , G11C29/00 , G11C29/06 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To detect a defect such as a short circuit between adjacent capacitive elements C for storing information by using a simple selective high-potential circuit. SOLUTION: A semiconductor device comprises a plurality of word lines disposed in parallel along the row direction, a plurality of bit lines disposed perpendicularly to the word lines along the column direction, and a memory cell array including memory cells deposed on the intersections of the word lines and the bit lines, The memory cell is composed of a crown-shaped capacitive element for storing information and an MISFET for selecting a memory cell that is connected in series with the capacity element for storing information. An external application circuit is provided which is connected with the bit line, collectively select the memory cells in every other column and sets the cells at a high potential, and sets the memory cells on the adjacent column to a low potential.

8. 发明专利

JP2001035197A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2001035197A
公开(公告)日：2001-02-09
申请号：JP20115999
申请日：1999-07-15
申请人： HITACHI LTD , AKITA ELECTRONICS CO LTD
发明人： KAWAKAMI MAKOTO
IPC分类号： G01R31/28 , G11C11/401 , G11C29/00 , G11C29/12
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device in which shortening a test time can be realized by reducing cycles of disturbance and refresh and improving the degree of freedom of assembling data. SOLUTION: This device is a DRAM, and has a test performing means by which the device is in a non-activation state at the time of normal operation, activated at the time of a test mode, and voltage of a data line is controlled in a non-selection state of a word line and a non-operation state of a sense amplifier. This test performing means is constituted of a word line selection control circuit 1 controlling selection of a word line WLi, a sense amplifier operation control circuit 2 controlling operation of a sense amplifier SAi, a column selection switch selection control circuit 3 controlling selection of column selection switch YSi, a data line voltage control circuit 4 controlling voltage of Di, and the like. A disturbance test of plural memory cells MCi can be performed by controlling voltage of Di arbitrarily without selecting a word line WLi and without operating a sense amplifier SAi.

9. 发明专利

JPS62284247A SAMPLE TABLE 失效
公开(公告)号：JPS62284247A
公开(公告)日：1987-12-10
申请号：JP12576086
申请日：1986-06-02
申请人： HITACHI LTD
发明人： OSADA TAKEO , SAKURAI YUTAKA , SASE AKIRA , FUKUNAGA MASAO , KAWAKAMI MAKOTO
IPC分类号： G12B5/00 , G01N21/84 , G01N21/88 , H05K3/00
摘要： PURPOSE:To reduce the weight of a sample table and increase the rigidity, and to maintain the plane accuracy excellently by employing a partition wall plate structure formed by fitting longitudinal and lateral partition wall plates in one another. CONSTITUTION:The sample table is equipped with a flat plate 1, longitudinal partition wall plates 2 assembled on the flat plate 1 in a specific shape, and a 1st and a 2nd lateral partition wall plates 3 and 4. The longitudinal partition wall plates 2 and the 1st and the 2nd lateral partition wall plates 3 and 4 are assembled alternately by using their fitting grooves and the fitting parts are coupled by brazing. The fitting grooves are the 1st upper and lower part fitting grooves 2a and 2b formed at the upper and lower parts of the longitudinal partition wall plates 2, the 2nd upper fitting grooves 3a formed at the upper parts of the 1st lateral partition wall plates 2 at specific positions for engagement with the 1st lower fitting grooves 2b, and the 2nd lower fitting grooves 4a formed at the lower parts of the 2nd lateral partition wall plates 4 at specific positions for engagement with the 1st upper fitting grooves 2a of the longitudinal partition wall plates 2.

10. 发明专利

JPS62169040A PRINTED BOARD PATTERN INSPECTOR 失效
公开(公告)号：JPS62169040A
公开(公告)日：1987-07-25
申请号：JP1015086
申请日：1986-01-22
申请人： HITACHI LTD
发明人： SAKURAI YUTAKA , KAWAKAMI MAKOTO
IPC分类号： G01N21/88 , G01B11/24 , G01N21/93 , G01N21/956 , H05K3/00
摘要： PURPOSE:To improve the inspection working efficiency of a printed circuit board, by automatically detecting immediately increase in the erroneous detection of a defect by an accidental cause such as mechanical vibration and electric noise to inform a worker of it. CONSTITUTION:The appearance of printed circuit boards 1 and 2 is picked up by image pickup means 6 and 7 to detect a circuit pattern of a substrate by a image processing. When a defect is detected during the inspection, the decision on the defect is made by reinspection at the same point. In a system of such a type, the results of the inspection are sorted into a true and false defect. The number of the defects determined to be false is counted through a counting means 13 and it is so set that when the frequency of the counts exceeds a set reference value, a warning action signal is outputted to accurate an alarm means 15 by this signal.

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