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1. 发明专利

JPH11204943A ELECTRONIC CIRCUIT BOARD AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH11204943A
公开(公告)日：1999-07-30
申请号：JP239698
申请日：1998-01-08
申请人： HITACHI LTD , HITACHI CABLE
发明人： TENMYO HIROYUKI , ISHINO MASAKAZU , AMAMIYA KYOKO , ONDA MAMORU , SATO TAKASHI , MURAKAMI TOMIO
IPC分类号： H05K3/46
摘要： PROBLEM TO BE SOLVED: To ensure reliable connection of conductors between upper and lower sheets in a multilayer electric circuit board which is produced by stacking insulator sheets on which conductor layers are formed and bonding the upper and lower layers. SOLUTION: An electric circuit board has a plurality of stacked insulator films 11, conductor patterns 15, 13 provided on the insulator films 11, and an adhesive layer 12 for bonding the insulator films 11. An alloy layer 27 is formed at the upper and lower junctions of the conductor pattern 15 in a step of heating and pressing the insulator films.

2. 发明专利

JPH0955569A THIN FILM WIRING SHEET, MULTILAYER WIRING BOARD AND THEIR PRODUCTION 失效
公开(公告)号：JPH0955569A
公开(公告)日：1997-02-25
申请号：JP20599295
申请日：1995-08-11
申请人： HITACHI LTD
发明人： TOGAWA HIDEO , SHOJI FUSAJI , ISHINO MASAKAZU
IPC分类号： C08G69/32 , C08G73/10 , C08L71/00 , C08L71/08 , C08L71/10 , C08L81/00 , C08L81/06 , H05K1/03 , H05K1/11 , H05K3/22 , H05K3/40 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To enhance the connection reliability while eliminating the delamination, short circuit and open circuit. SOLUTION: An insulation film 11, a planar wiring 12, and via wirings 16, 18 having one end exposed to the surface of insulation film 11 and the other end connected with the planar wiring 12 are provided. The planar wiring 12 is buried in the insulation film 11. A recess for restricting the spreading of conductor connection material is provided around the exposed part of via wiring.

3. 发明专利

JPH08181450A ELECTRONIC CIRCUIT BOARD AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH08181450A
公开(公告)日：1996-07-12
申请号：JP32076894
申请日：1994-12-22
申请人： HITACHI LTD
发明人： ISHINO MASAKAZU , KAWAI MICHIFUMI , INOUE TAKASHI , KYOI MASAYUKI
IPC分类号： H05K3/46
摘要： PURPOSE: To realize an electronic circuit board adapted for high density mounting and a method for manufacturing the same by superposing many wiring sheets having stable sizes and effectively adhering the electric connections of vias to the sheets. CONSTITUTION: Wiring sheets 200A, 200B are formed by processing wiring patterns (211 for a power source and 212 for signal) made of a material adhered with copper foils 202, 203 to both surfaces of a thermosetting polyimide resin sheet 201. An adhesive sheet 100 provided with metal vias 104 at predetermined positions of a thermoset polyimide resin sheet 101 in parallel therewith, the vias 104 of the sheet and the connecting pads 214 of the signal wiring side of the wiring sheet are aligned, laminated, the laminate is connected at the electric connector under pressure, then heated by a temperature profile of two stages for connecting between the resin sheets, press-bonded to obtain the circuit board of the multilayer.

4. 发明专利

JPH08107279A MANUFACTURE OF WIRING BOARD 失效
公开(公告)号：JPH08107279A
公开(公告)日：1996-04-23
申请号：JP23873894
申请日：1994-10-03
申请人： HITACHI LTD
发明人： ISHINO MASAKAZU , YAMAZAKI TETSUYA , MATSUZAKI EIJI
IPC分类号： H05K3/06 , H05K3/24 , H05K3/46
摘要： PURPOSE: To make it possible to form reliably a wiring pattern having a highly reliable via stud by a method wherein the wiring pattern is formed in a state that the via stud is completely covered with an etching resist of a shape dimension decided by specified functions. CONSTITUTION: While a via stud 105 is protected with an etching resist 106, a wiring pattern is formed on a conductor layer 102. At that time, the shape dimension of the etching resist 106 covering the stud 105 is decided by functions of the angle α of inclination of the wall surface of the stud 105 at the time of electroplating of a through hole provided in a plated resist 103, an angle βof inclination from a segment dropped vertically from a via stud top end part in the resist 106 covering the stud 105 to the surface of a substrate, the diameter (d) of the bottom of the stud 105, the height (h) of the stud 105 and an alignment error (δ) of a photomask. The wiring pattern is formed in a state that the stud 105 is completely covered with the resist 106.

5. 发明专利

JPH07240582A MULTILAYER INTERCONNECTION BOARD AND METHOD AND DEVICE FOR MANUFACTURING MULTILAYER INTERCONNECTION BOARD 失效
公开(公告)号：JPH07240582A
公开(公告)日：1995-09-12
申请号：JP3025694
申请日：1994-02-28
申请人： HITACHI LTD
发明人： KAWAI MICHIFUMI , SATO RYOHEI , YAMADA OSAMU , MATSUZAKI EIJI , ISHINO MASAKAZU , INOUE TAKASHI , TOGAWA HIDEO , KYOI MASAYUKI
IPC分类号： H05K3/46 , H01L21/48 , H05K3/28 , H05K3/42
摘要： PURPOSE:To reduce cost by collectively laminating multilayer substrates and simultaneously solve fine and high-density wiring by connecting especially a member for joint to the surface wiring of a second insulation film via an alloy layer consisting of a metal which is the material of the member for joint and a conductor. CONSTITUTION:An insulation film 1 to be laminated is provided with a wiring 2 on either front or back surface and a via hole 4 whose one edge part 3 is connected to the wiring 2 and the other edge part 3 is penetrated through the other surface. The insulation film 1 is laminated via an adhesive layer 6 with an adhesive curing object. The edge part 3 which is not connected to the wiring 2 of the via hole 4 of the first insulation film 1 is covered with a member 5 for joint consisting of a metal or an alloy which is different from a conductor for forming the wiring 2. The member 5 for joint is connected to the wiring 2 on the surface of the second insulation film 1 via an alloy layer consisting of a metal or an alloy which is the material of the member 5 for joint via an alloy layer consisting of the conductor, the member of the wiring 2, thus reducing cost and achieving a high-density wiring due to collective lamination.

6. 发明专利

JPH07226589A MANUFACTURE OF THIN FILM MULTILAYER WIRING BOARD 失效
公开(公告)号：JPH07226589A
公开(公告)日：1995-08-22
申请号：JP1509394
申请日：1994-02-09
申请人： HITACHI LTD
发明人： ISHINO MASAKAZU
IPC分类号： H05K3/46
摘要： PURPOSE:To enable formation of a via at a fine interval to a wiring board of a thick insulation film by forming a tapered via which can provide a large opening area and by forming a vertical via at a lower diameter which is smaller than an upper diameter of the tapered via in an upper part of the tapered via. CONSTITUTION:A wiring metal 302 is successively formed to a film in a board 301. Resist is applied to the wiring metallic layer 302 and a wiring pattern is exposed and developed. Thereafter, it is removed by etching and a lower wiring layer 303 is formed. An insulation layer 324 is applied to the lower wiring layer 303 and total exposure and development are performed for it excepting a tapered via hole formation part 325 which can provide a large opening area. A second insulation layer 314 is applied by a spinner and a vertical via hole 315 is formed by dry etching. Thereby, a via which enables connection of up and down wiring layers with good yield can be realized while maintaining fine wiring pitch.

7. 发明专利

JPH0562822B2 失效
公开(公告)号：JPH0562822B2
公开(公告)日：1993-09-09
申请号：JP10055885
申请日：1985-05-14
申请人： HITACHI LTD
发明人： ISHINO MASAKAZU , FUNATSU RYUICHI , TAKAHASHI TSUTOMU , ITO FUMIKAZU , ARAYA TATSUYA
IPC分类号： B65D85/86 , H01L21/00 , H01L21/67 , H01L21/673 , H01L21/68

8. 发明专利

JPH055177A SPUTTERING TARGET 失效
公开(公告)号：JPH055177A
公开(公告)日：1993-01-14
申请号：JP17920791
申请日：1991-07-19
申请人： HITACHI LTD , HITACHI METALS LTD
发明人： NARIZUKA YASUNORI , ISHINO MASAKAZU , KENMOCHI AKIHIRO , CHIBA YOSHITAKA , HIRAKI AKITOSHI
IPC分类号： C22C1/05 , C23C14/34 , H01L21/203 , H01L21/285
摘要： PURPOSE:To provide a sputtering target capable of stably and inexpensively forming thin films each consisting of Cr, Si and O and having high specific resistance over a long period of time. CONSTITUTION:The grain sizes of Cr and SiO3 powders are properly selected and the powders are well dried by heating and mixed in such a ratio as to give a compsn. consisting of 50-80wt.% Cr and the balance SiO2. The resulting mixture is charged into a mold and sintered by hot pressing or other method to obtain a sputtering target having a homogeneous two-phase mixed texture and withstanding electric discharge for a long time. When this target is used, a homogeneous thin Cr-Si-O film is formed over a large area with high reproducibility.

9. 发明专利

JPH04354866A SPUTTERING TARGET AND ELECTRIC CIRCUIT INCLUDING THIS TARGET 失效
公开(公告)号：JPH04354866A
公开(公告)日：1992-12-09
申请号：JP12710091
申请日：1991-05-30
申请人： HITACHI LTD
发明人： KENMOCHI AKIHIRO , YAGI KUNIHIRO , ISHINO MASAKAZU , NARIZUKA YASUNORI
IPC分类号： C22C27/06 , C22C29/06 , C22C29/12 , C23C14/34
摘要： PURPOSE:To obtain thin films having a distribution state of desired characteristics with good reproducibility over a long period of time by using the same material system for the entire part of the sputtering target consisting of plural elements and locally changing the element ratios thereof. CONSTITUTION:A plate 3 consisting of a sintered body of a chromium silicon alloy having, for example, a high chromium ratio and a plate 4 consisting of a sintered body of a chromium silicon alloy having a low chromium ratio are produced to a prescribed shape. These sintered bodies 3, 4 are arrayed and are bonded to a backing plate 5 to form the sintered target. The butt parts of the sintered bodies 3, 4 are so inclined as to prevent the backing plate 5 from being viewed directly from above to avoid the erosion of these parts. The sputtering target locally varying in the compsn. is obtd. in this way. The local compsn. ratios of the thin films can be controlled with the good reproducibility if the thin films are formed by using such target and, therefore, the distribution of the film characteristics of the thin film in the substrate is controlled.

10. 发明专利

JPH03166787A INTERCONNECTION BOARD 失效
公开(公告)号：JPH03166787A
公开(公告)日：1991-07-18
申请号：JP30723289
申请日：1989-11-27
申请人： HITACHI LTD
发明人： NARIZUKA YASUNORI , KENMOCHI AKIHIRO , ISHINO MASAKAZU , MATSUZAKI EIJI
IPC分类号： H05K1/02 , H01L23/367 , H01L23/538 , H01L27/01 , H05K1/16 , H05K3/38 , H05K3/46
摘要： PURPOSE:To make it possible to obtain a high reliability interconnection board which is free of damage and burnout of a conductor, a resistor and the like by installing a layer which diffuses heat generated in said interconnection board. CONSTITUTION:An organic insulation layer 2 is formed on a board 1. There is formed a thermal diffusion layer 3 which is made of Si at the thickness ranging from preferably 0.2mum to 10mum on the organic insulation layer 2. On the thermal diffusion layer 3 is formed a conductor layer 4 which is etched into a required shape. On the conductor layer 4 are further formed an organic insulation layer 2a, a thermal diffusion layer 3a, and a conductor layer 4a one by one. A through hole 10a is formed at the same place with the organic insulation layer 2a and the thermal diffusion layer 3a located on the upper layers, thereby connecting the conductor 4a on the upper layer and the conductor 4 on the lower layer. This construction makes it possible to prevent the burnout of interconnections and resistors produced by thermal stress resultant from a temperature rise due to thermal storage.

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