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1. 发明专利

JPH1050881A PACKAGE SUBSTRATE, LEAD FRAME AND SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH1050881A
公开(公告)日：1998-02-20
申请号：JP20356796
申请日：1996-08-01
申请人： HITACHI LTD
发明人： HANABUSA YOSHIAKI , YOSHIDA IKUO
IPC分类号： H01L23/12 , H01L23/50
摘要： PROBLEM TO BE SOLVED: To enable flexible two-dimensional mounting and three-dimensional mounting by one kind of package configuration. SOLUTION: In three-dimensional mounting of a semiconductor device, a tip part of inner leads 3b1 , 4a1 and an electrode part of a semiconductor chip 6 are electrically connected by a bonding wire 7, outer leads 3a1 , 4a of a lead 4 and a land of a printed wiring board are electrically connected and fixed by solder, etc., and a semiconductor device is mounted vertically to a printed wiring board. In second dimensional mounting of a semiconductor device, a tip part of inner leads 3b1 , 3b2 and an electrode part of the semiconductor chip 6 are electrically connected by the bonding wire 7, outer leads 3a1 , 3a2 of a lead 3 and a land of a printed wiring board are electrically connected and fixed by solder, etc., and a semiconductor device is mounted horizontally to a printed wiring board.

2. 发明专利

JPH07226492A SEMICONDUCTOR DEVICE USING SOI SUBSTRATE 失效
公开(公告)号：JPH07226492A
公开(公告)日：1995-08-22
申请号：JP1795994
申请日：1994-02-15
申请人： HITACHI LTD
发明人： HANABUSA YOSHIAKI , IKEDA TAKAHIDE , NONAMI HIDEAKI , KAWAJI MOTONORI
IPC分类号： H01L27/12 , H01L21/02
摘要： PURPOSE:To prevent characteristic fluctuation of a semiconductor device due to ion contamination from a semiconductor chip end face, deterioration in electric insulation between devices and inferior function due to LSI maloperation and to detect diffusion of anode ions such as sodium in a bonded oxide film. CONSTITUTION:Arrangement position of a semiconductor device 2 is defined to a position capable of preventing malfunction due to ion contamination from an end face 1A of a semiconductor chip 1. Further, a sensor to detect diffusion in a bonded oxide film of anode ions such as sodium between the regions where a semiconductor element arrangement region 2 from the end face 1A of the semiconductor chip 1 is arranged, is disposed.

3. 发明专利

JPH01191451A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01191451A
公开(公告)日：1989-08-01
申请号：JP1443588
申请日：1988-01-27
申请人： HITACHI LTD
发明人： HANABUSA YOSHIAKI , TAKAHASHI TAKAHIKO , UDA TAKAYUKI
IPC分类号： H01L21/60
摘要： PURPOSE:To improve the connecting reliability of a CCB bump, by providing a configuration so that the inner periphery length of a contact hole becomes long when a ground film is deposited and formed in the contact hole that is opened and formed in the surface protecting film of a semiconductor wafer and the CCB bump is bonded to the surface. CONSTITUTION:An Si3N4 film 2 is deposited on the surface of a wafer 1. A hole is provided at a specified place by photoresist/etching, and an Al wiring 3 is exposed. Thereafter, a glass protecting film 4 comprising SiO2 is formed. Then, photoresist having a comb-teeth pattern is deposited on the surface of the glass protecting film 4. Wet etching is performed, and a contact hole 5 is formed. Then, a thin ground film 6 comprising chromium/copper/gold and the like is evaporated on the inner periphery of the hole 5. Thereafter, photoresist is deposited on the surface of the wafer 1. The hole 5 is opened by etching, and the ground film 6 is exposed. A solder film 8 comprising tin and lead is formed. The photoresist 7 and the unnecessary solder film 8 are removed. Thereafter, the wafer 1 is put into a reflow furnace for fusing and heating. Thus, a CCB bump 9 is formed.

4. 发明专利

JPS63120440A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS63120440A
公开(公告)日：1988-05-24
申请号：JP26550586
申请日：1986-11-10
申请人： HITACHI LTD
发明人： HANABUSA YOSHIAKI , TAKAHASHI TAKAHIKO , OWADA NOBUO , KOBAYASHI TORU
IPC分类号： H01L21/3213
摘要： PURPOSE:To prevent element regions from being damaged in case of etching an insulating film to make connecting holes by a method wherein the connecting holes between the first layer wirings and the second layer wirings are arranged only on a field insulating film or an interlayer insulating film. CONSTITUTION:Connecting holes 11a, 11b of a semiconductor integrated circuit device with said connecting holes 11a, 11b made in an insulating film between the first and the second layer wirings 10, 12 formed on a semiconductor substrate are arranged only on a field insulating film 4 or an interlayer insulating film. For example, in case of a bipolar LSI, the first layer wirings 101-104 comprising Al films are covered with the insulating film 11 such as PSG film and then the second layer wirings comprising Al films are provided on the insulating film 11 to be connected respectively to the wirings 103, 104 through the tapered connecting holes 11a, 11b made in the insulating film 11. Furthermore, said connecting holes 11a, 11b and other connecting holes are arranged only on the field insulating film 4.

5. 发明专利

JPS61125057A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS61125057A
公开(公告)日：1986-06-12
申请号：JP24599084
申请日：1984-11-22
申请人： Hitachi Ltd
发明人： HANABUSA YOSHIAKI
IPC分类号： H01L23/44 , H01L23/427
CPC分类号： H01L23/427 , H01L2224/16225 , H01L2924/15312
摘要： PURPOSE:To improve cooling capability and heat radiation effect of a semiconductor chip by a simple structure, by sealing a sealing medium of insulating, low-boiling-point liquid or gas in the inside of a sealed hollow package. CONSTITUTION:A wiring comprising aluminum is provided on a package substrate 1. Outer leads 2 for input and output are electrically connected to the specified wiring on the package substrate 1. A package cap 3 is bonded and sealed to the package substrate 1 by a heavy duty bonding agent or low melting point glass. Protruded electrodes 5 for input and output terminals are provided on a semiconductor chip 4. The protruded electrodes 5 are reflowed. The input and output terminals of the semiconductor chip 4 and the input and output terminals of the package substrate 1 are electrically connected through the wiring. As for a cooling medium 6 of insulating, low-boiling-point liquid or gas, which is sealed in the package, distilled waver, alcohol and the like are used in detail. The outside of the package cap 3 is forcibly cooled by cooling water or cooling gas.
摘要翻译：目的：通过简单的结构提高半导体芯片的冷却能力和散热效果，通过密封密封中空封装内部的绝缘低沸点液体或气体的密封介质。构成：在封装基板1上设置包含铝的布线。用于输入和输出的外引线2与封装基板1上的指定布线电连接。封装盖3通过重的低熔点玻璃。用于输入和输出端子的突出电极5设置在半导体芯片4上。突出的电极5被回流。半导体芯片4的输入输出端子和封装基板1的输入输出端子通过布线电连接。对于密封在包装中的绝缘低沸点液体或气体的冷却介质6，详细地使用蒸馏水，酒精等。包装盖3的外部被冷却水或冷却气体强制冷却。

6. 发明专利

JPH09129638A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH09129638A
公开(公告)日：1997-05-16
申请号：JP28004995
申请日：1995-10-27
申请人： HITACHI LTD
发明人： HANABUSA YOSHIAKI , FUJISAKI YASUNORI
IPC分类号： H01L21/28 , H01L21/3205 , H01L23/52
摘要： PROBLEM TO BE SOLVED: To provide a technique capable of making an electromigration resistance enhance in the case where a laminated wiring comprising a high-melting point metal layer and an aluminium alloy layer is formed in a contact hole formed in an insulating film in a fine width. SOLUTION: Al crystal grains 12 in an Al-Cu-Si alloy layer 8 constituting one part of an upper wiring layer 6 are formed in a size larger than the width L and thickness T of the wiring layer 6 and have the so-called bamboo structure. In such a way, by forming specially the Al crystal grains 12 in a size larger than the width L and thickness T of the wiring layer 6, it becomes possible to stop almost an Al atom transfer along crystal grain boundaries in the layer 6. As a result, it becomes possible to reduce the generation of an electro-migration.

7. 发明专利

JPH0961501A DATA-PROCESSING APPARATUS 失效
公开(公告)号：JPH0961501A
公开(公告)日：1997-03-07
申请号：JP24364895
申请日：1995-08-29
申请人： HITACHI LTD
发明人： HANABUSA YOSHIAKI , NONAMI HIDEAKI , HOSOE HIDEYUKI , HONMA KENJI , FUJISAKI YASUNORI
IPC分类号： G01R31/302
摘要： PROBLEM TO BE SOLVED: To make it easy to visually recognize a failing position of a power source by providing a formation means sand a display means for a distribution image of resistance values of wirings of the power source in every minute area. SOLUTION: A CPU 11 carries out operations for a pseudo three-dimensional display and transmits the data to a graphic display processor 361. Because of a plotting treatment by the processor 361, data of a pseudo three-dimensional image are formed in a frame buffer 364 and displayed at a CTR display 366 via a dot shifter 365. The position of a bump of an LSI to be measured and the resistance value are respectively indicated by an X-Y coordinate and a Z coordinate at the CRT 366. A falling position displayed in the pseudo three- dimensional display image, namely, a position where the resistance value minimum is a failing position corresponding to the position where a shortcircuited resistor is present. A Z-axis indicates the resistance value which falls differently spending on a value of the shortcircuited resistor. The failing position of power source of the LSI to be measured can be visually recognized from the pseudo three-dimensional display image.

8. 发明专利

JPH06177233A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH06177233A
公开(公告)日：1994-06-24
申请号：JP32218592
申请日：1992-12-02
申请人： HITACHI LTD
发明人： KAWAJI MOTONORI , NISHIZAWA HIROTAKA , HANABUSA YOSHIAKI , TANBA NOBUO , HIRAMOTO TOSHIRO , IKEDA TAKAHIDE
IPC分类号： H01L21/762 , H01L21/76 , H01L27/00 , H01L27/12
摘要： PURPOSE:To suppress or prevent cations from entering an element forming region in a semiconductor integrated circuit device of an SOI(silicon-on-insulator) structure. CONSTITUTION:A semiconductor integrated circuit device 1 having an SOI structure comprises a laminated structure of an insulating layer 6a made of SiO2 and an insulating layer 6b made of Si3N4 having properties capable of transmitting no cation in an insulting layer 6 between a support board 5 and a semiconductor layer 7.

9. 发明专利

JPH02116145A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH02116145A
公开(公告)日：1990-04-27
申请号：JP26803788
申请日：1988-10-26
申请人： HITACHI LTD
发明人： HANABUSA YOSHIAKI , UCHIUMI YASUYUKI
IPC分类号： H01L21/52 , H01L21/301 , H01L21/78
摘要： PURPOSE:To improve the throughput of a manufacturing line and avoid material waste by a method wherein alignment marks and error indication marks indicating the discrepancy error of dicing are provided on a semiconductor wafer for obtaining a plurality of chips from the semiconductor wafer by dicing. CONSTITUTION:Two sets of mark groups for confirming lengthwise and breadthwise dicing positions are provided on a semiconductor wafer. Although only the mark group for confirming the lengthwise position is shown in the figures, the similar mark group is provided for confirming the breadthwise position too. The mark group is composed of one alignment mark 1, two dicing width indication marks 2 indicating a normal dicing width and two pairs of error indication marks 3 and 4 indicating the discrepancy error of dicing. The marks 1, 2, 3 and 4 are so arranged as to form an isosceles triangle. Further, pairs of the marks 2, 3 and 4 are so arranged as to be symmetrical with the mark 1 as the center and the marks 1 and 2 are so arranged as to disappear after dicing.

10. 发明专利

JPS63104451A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS63104451A
公开(公告)日：1988-05-09
申请号：JP24964386
申请日：1986-10-22
申请人： HITACHI LTD
发明人： HANABUSA YOSHIAKI , OWADA NOBUO
IPC分类号： H01L21/768 , H01L23/522
摘要： PURPOSE:To reduce the parasitic capacitance of a wiring part at a semiconductor device by a method wherein a second wiring part which is extended in the same direction as a first wiring part is laid out by being extended in the middle of the two adjacent first wiring parts. CONSTITUTION:A wiring part 19a among wiring parts 19a-19c is laid out in such a way that it is extended directly above the center between wiring parts 17a and 17b in the region from a connecting hole to another connecting hole, both of which connect the wiring part 19a and the wiring part 18. That is to say, the wiring part is laid out in such a way that the center of the wiring part 19a in the transverse direction exists above the center between the wiring parts 17a and 17b. In the same manner, a wiring part 19b is laid out by being extended directly above the middle between wiring parts 17b and 17c while a wiring part 19c is laid out by being extended directly above the middle between wiring parts 17c and 17d. By this method, the overlapped area of wiring parts 17a-17d and wiring parts 19a-19c becomes small, and the interwiring capacitance between these wiring parts is reduced. The interval between the wiring parts for 17a-17d may be wider than the wiring width of the wiring parts for 19a-19c.

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