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1. 发明专利

JP2001013259A SEABED SEDIMENTARY LAYER PARAMETER-ESTIMATING DEVICE USING GENETIC ALGORITHM 失效
公开(公告)号：JP2001013259A
公开(公告)日：2001-01-19
申请号：JP18329699
申请日：1999-06-29
申请人： HITACHI LTD
发明人： HINO KAZUHIKO , SATO KAZUO , OIWA MASANORI , ASANO KENICHI
IPC分类号： G01B17/02 , G01V1/30
摘要： PROBLEM TO BE SOLVED: To obtain a seabed sedimentary layer parameter-estimating device for stably estimating the value of parameters for indicating the characteristics of a seabed sedimentary layer from actual measurement data. SOLUTION: An observation characteristic value operation part 2 obtains a characteristic value C0 of an elastic wave being propagated on a seabed sedimentary layer from data obtained by observing the target seabed sedimentary layer. A gene operation part 10 performs a genetic operation to an individual by a genetic algorithm with the combination of the candidate values of a plurality of parameters for indicating the physical characteristics of the seabed sedimentary layer as the individual to allow it to evolve into a next-generation individual. An estimation characteristic value operation part 4 estimates a characteristic value C of an elastic wave theoretically for the individual. A degree-of-conformance operation part 3 obtains the degree of conformance for indicating the degree of conformance between a characteristic value C and the characteristic value C0 and sets a candidate for composing an individual with the highest degree of conformance as the solution of the value of parameters.

2. 发明专利

JPH04293332A BIT PHASE SYNCHRONIZING CIRCUIT 失效
公开(公告)号：JPH04293332A
公开(公告)日：1992-10-16
申请号：JP5856991
申请日：1991-03-22
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： OZAKI NAOHIKO , ASANO KENICHI , AIKI KIYOSHI , MIZUKAMI MASAO
IPC分类号： H04L7/02 , H03L7/06 , H04L25/493
摘要： PURPOSE:To suppress increase in power consumption and further to easily distribute a high speed clock in the bit phase synchronizing circuit comprising a bit phase adjustment circuit, a bit change point detection circuit and a bit phase control circuit. CONSTITUTION:The bit phase synchronizing circuit consists of a bit phase adjustment circuit changing a delay quantity of an input data, a bit change point detection circuit 2 detecting a relation of a phase of the input data with a phase of a reference clock and generating a change point detection signal representing it that the phase is deviated from the allowable range, and a bit phase control circuit 3 giving a control signal for selecting the delay quantity to the bit phase adjustment circuit 1 according to the change detection signal, and the bit phase control circuit 3 is operated by a clock whose speed is lower than that of the reference clock. Thus, the power consumption is suppressed by decreasing the speed of the bit phase control circuit. Moreover, circuits for high speed clock operation are limited to facilitate clock distribution.

3. 发明专利

JPS6330099A CHANNEL MEMORY OPERATION CONTROL SYSTEM FOR TIME DIVISION SWITCH 失效
公开(公告)号：JPS6330099A
公开(公告)日：1988-02-08
申请号：JP17164786
申请日：1986-07-23
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： ASANO KENICHI , AMADA EIICHI , SHIBUKAWA MASARU
IPC分类号： H04Q3/52 , H04Q11/04
摘要： PURPOSE:To attain low power by storing idle/busy management information of an output channel in a 2nd storage means for designating the read address of a 1st storage means for storing digital information by one inputted frame to replace the channel and reading the 1st storage means in case of the occupied state only thereby reducing the operating rate of the channel memory of the time division switch. CONSTITUTION:A one-frame serial signal from input highways 100-107 is subjected to serial/parallel conversion at each channel by variable delay shift registers 130-137 and outputted to a selector 122 and fed to a speech path memory 120 while being selected sequentially. Then the read address is controlled by a control memory 121 to repace the channels. When information is written in the memory 120, the selector 124 selects a H-level fixed signal 127 and in case of data readout, the selector selects an idle/busy management bit 128 of the memory 121. AND gates 150-157 use the output of bit 128 and the memory 120 to bring all bits of idle output channels to a L level. Shift registers 140-147 apply serial convertion to parallel data being outputs of the memory 120 to apply output phase adjustment among output highways 110-117.

4. 发明专利

JPH09214497A ATM CELL MULTIPLEX CIRCUIT 失效
公开(公告)号：JPH09214497A
公开(公告)日：1997-08-15
申请号：JP1501196
申请日：1996-01-31
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： ASANO KENICHI , SAIKOUJI SHIYUNSUKE , OZAKI NAOHIKO , KANO TETSUO
IPC分类号： H04Q3/00 , H04L12/28
摘要： PROBLEM TO BE SOLVED: To simplify a multiplex circuit and to reduce the power consumption of a circuit by providing barrel shifters and buffer memories before and after the barrel shifters. SOLUTION: The ATM cell multiplex circuit is provided with the barrel shifters 7-1 to 7-4 and 8-1 and 8-4 exchanging the bit positions of cells between input/output terminals. Then the plural first buffer memories 5-1 to 5-16 shifting bits to the direction of a time axis at every input cell in the front stage of the barrel shifters 7-1 to 7-4 and 8-1 to 8-4, plural second buffer memories 9-1 to 9-16 arranging the bits of the cells, which are multiplexed in the post stages of the barrel shifters 7-1 to 7-4 and 8-1 to 8-4, and a means for switching the bit position exchanging operation of the barrel shifters 7-1 to 7-4 and 8-1 to 8-4 in accordance with the parallel multiplex speed of input highways 1-1 to 1-16 are provided. Thus, a shift register and a delay circuit are not necessary and power consumption can be reduced with a small circuit scale.

5. 发明专利

JPH07123094A BUFFER CONTROL CIRCUIT 失效
公开(公告)号：JPH07123094A
公开(公告)日：1995-05-12
申请号：JP26334993
申请日：1993-10-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SAIKOUJI SHIYUNSUKE , ASANO KENICHI , NAKAMURA MASARU , FUJITA TOSHIHIKO
IPC分类号： H04Q3/00 , H04L12/28 , H04Q3/52
摘要： PURPOSE:To attain buffer control at a higher speed when the data cycle is equal to the clock cycle by using a specific address of buffer memory as a dummy address and avoiding the invalid cells with a clock kept always in the buffer memory. CONSTITUTION:A cell is supplied to a terminal D1 of a buffer memory 1, and at the same time a write enable (WE) signal is supplied to a terminal WE of a flag deciding circuit 24. The WE signal shows a valid state and an invalid state with levels '1' and '0' respectively. When '1' is supplied to a terminal S1 from the circuit 24, a selector 23 selects an address sent from a writing pointer 21. Meanwhile, the selector 23 selects dummy address and sends it to a terminal WA of the memory 1 when '0' is supplied to the terminal S1. In such a constitution, the invalid cells are written in the dummy cell and deleted without stopping the clocks.

6. 发明专利

JPH06224883A PARITY CHECK CIRCUIT 失效
公开(公告)号：JPH06224883A
公开(公告)日：1994-08-12
申请号：JP815093
申请日：1993-01-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： ASANO KENICHI , SAIKOUJI SHIYUNSUKE , NAKANO YUKIO , ASHI MASAHIRO
IPC分类号： G06F11/10 , H03M13/00 , H04L1/00
摘要： PURPOSE:To reduce the number of gates at an LSI and power consumption by repeating parity decision for each bit to be inputted and deciding the parity result when the final line of a frame is received. CONSTITUTION:An input frame 20 is inputted to a parity decision circuit 1 in the form of parallel (m) bitsX(n) lines. Corresponding to the input signal of (m+1) bits, the parity decision circuit 1 outputs an odd-number deciding signal 30 and an even-number deciding signal 31. The even-number deciding signal is fed back while being delayed for one clock by a latch 3, subjected to AND with a TOP signal by an AND gate 2 and inputted to the parity decision circuit 1. In this case, since the decision is repeated (n) times to the n-th line, when the n-th line at the end of the frame is inputted, the odd-number decision signal 30 and the even-number decision signal 31 are outputted corresponding to (mXn) bits from the 1st line to n-th line of the frame.

7. 发明专利

JP2006046986A Sensor information unifying/analyzing device and method 审中-公开
标题翻译：传感器信息统一/分析装置和方法
公开(公告)号：JP2006046986A
公开(公告)日：2006-02-16
申请号：JP2004225173
申请日：2004-08-02
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： TAZAWA ISAO , HINO KAZUHIKO , ASANO KENICHI , TAKAHASHI HIROSHI
IPC分类号： G01S15/66
摘要： PROBLEM TO BE SOLVED: To provide an analysis device for a plurality of pieces of sensor information to reduce load, required for estimating various parameters on a plurality of acoustic sensors.
SOLUTION: The plurality of acoustic sensors are grouped, and it is assumed that one virtual acoustic sensor exists at an average position of acoustic sensors in each group. Optimization of the parameters for fictitious acoustic sensors is performed for each of the fictitious acoustic sensors. The parameters of acoustic sensors included in each group are set to be the same as the parameters of a fictitious acoustic sensor of a relevant group.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供用于多个传感器信息的分析装置，以减少用于估计多个声学传感器上的各种参数所需的负载。解决方案：多个声学传感器被分组，并且假设每个组中的声学传感器的平均位置处存在一个虚拟声学传感器。对于每个虚构声学传感器执行虚拟声学传感器参数的优化。每个组中包括的声学传感器的参数被设置为与相关组的虚拟声学传感器的参数相同。版权所有（C）2006，JPO＆NCIPI

8. 发明专利

JP2005024354A Parallel sound field calculator 审中-公开
标题翻译：并行声场计算器
公开(公告)号：JP2005024354A
公开(公告)日：2005-01-27
申请号：JP2003189156
申请日：2003-07-01
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： MAKIMOTO NOBUO , HINO KAZUHIKO , ASANO KENICHI , TAKAHASHI HIROSHI
IPC分类号： G01H17/00 , G06F17/16
摘要： PROBLEM TO BE SOLVED: To simulate an underwater sound field at high speed as to the areas of remote sensing and underwater acoustic information processing.
SOLUTION: Correspondently to a sound wave propagation model, processing is divided for parallel execution. That is, a multitude of characteristic values and characteristic vectors are parallel calculated as to a normal mode method. As to an FDTD (Finite Difference Time Domain) method, a domain is divided and parallel calculation is performed while suitably exchanging boundary data. Sound field calculation can be speeded up to facilitate the actualization of repetitive simulation and real-time simulation.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了模拟遥感和水下声学信息处理领域的高速水下声场。解决方案：对应于声波传播模型，处理被划分为并行执行。也就是说，对于正常模式方法，并行计算多个特征值和特征向量。对于FDTD（有限差分时域）方法，分割域并且在适当地交换边界数据的同时执行并行计算。声场计算可以加快，以便实现重复仿真和实时仿真。版权所有（C）2005，JPO＆NCIPI

9. 发明专利

JP2004077401A Multistatic sensor operation method 审中-公开
公开(公告)号：JP2004077401A
公开(公告)日：2004-03-11
申请号：JP2002241301
申请日：2002-08-22
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： MAKIMOTO NOBUO , HINO KAZUHIKO , ASANO KENICHI
IPC分类号： G08G3/00 , G01S13/46 , G01S15/46
摘要： PROBLEM TO BE SOLVED: To compute a multistatic sensor arrangement suitable for a purpose of a search in constant formation.
SOLUTION: A search area per unit time is formulated as an index of purpose achievement, and such a sensor arrangement as increases the index is sought.
COPYRIGHT: (C)2004,JPO

10. 发明专利

JP2004077400A Sensor information integrating system 审中-公开
公开(公告)号：JP2004077400A
公开(公告)日：2004-03-11
申请号：JP2002241300
申请日：2002-08-22
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： TAZAWA ISAO , HINO KAZUHIKO , ASANO KENICHI
IPC分类号： G01S13/04 , G01S13/66 , G01S15/04 , G01S15/66
摘要： PROBLEM TO BE SOLVED: To provide a sensor information integrating system to work with an integration processing device for sensor signals having a finite computing ability and communication ability, capable of reducing the data transmitting amount to the integration processing device without reducing the target rate of sensing and of reducing the processing load of the integration processing device.
SOLUTION: The sensor information integrating system comprises a observation part to analyze the observation signal(s) from one or more sensors and determine the observation signal value in each position within the observing region of each sensor, a sensor information processing part to sense a signal possible to be the target signal (target signal candidate) on the basis of the obtained observation signal value, and the integration processing part to integrate the observation information of the target signal candidates. Therein a plurality of such sensors, a plurality of sensor information processing parts, and a plurality of integration processing parts are connected in stories, and the observation signals of the sensors are integrated in hierarchy. Among the target signal candidates given by a plurality of sensor information processing parts or a plurality of other integration processing parts, the integration processing part concerned selects only the target signal candidates having a high correlation and integrates them, and emits the data in which unnecessary observation information is reduced through integration to the next stage integration processing part.
COPYRIGHT: (C)2004,JPO

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