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1. 发明专利

JPS6257354A SYSTEM FOR SETTING ACTIVE UNIT IN DUPLEX CONSTITUTING DEVICE 失效
公开(公告)号：JPS6257354A
公开(公告)日：1987-03-13
申请号：JP19588985
申请日：1985-09-06
申请人： HITACHI LTD , HITACHI VLSI ENG , HITACHI TSUSHIN SYSTEM , RINKU KK
发明人： IZUMIDA YUJI , KUWABARA HIROSHI , SHIBUKAWA MASARU , OOTOU SHIYUUZOU , OGINO MINEO
IPC分类号： G06F11/20 , H04M3/22
摘要： PURPOSE:To improve the reliability at open cable between units by allowing both units to keep a state before the opened cable at the opened cable between the units. CONSTITUTION:Since fault information display signal lines 32, 31 are cut off at the open cable, an input to other unit fault supervisory sections 14, 24 has a high impedance. Further, open cable detection signal lines 35, 36 are cut off at the same time and open cable detection sections 15, 25 detect the open cable and give cable cut-off information to state control sections 16, 26. The state control section 16 gives priority to the cable fault information over other unit fault information, cable failure information and other unit in operation detection and keeps the level of the state display signal 33 unchanged (as L level) so as to keep a basic equipment 11 in the operating state. Further, the state control section 26 gives the priority to the cable open information similarly over the other information and keeps the state display signal 34 unchanged (as H level) thereby keeping the basic equipment 21 inoperative.

2. 发明专利

JPS6251399A FRAME SIGNAL SUPPLY CIRCUIT IN TIME-DIVISION EXCHANGE 失效
公开(公告)号：JPS6251399A
公开(公告)日：1987-03-06
申请号：JP18965885
申请日：1985-08-30
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SHIBUKAWA MASARU , KUWABARA HIROSHI , IZUMIDA YUJI
IPC分类号： H04Q11/04
摘要： PURPOSE:To decrease the disturbance of a period signal due to system changeover and signal missing by suppressing a preceding frame signal to frame signals closed together against the disturbance of frame signals due to changeover of a duplex system and applying self-running of a counter with respect to a missing frame signal to generate a frame signal at each frame period. CONSTITUTION:Each frame signal and a clock are received from a frame signal source and a clock signal source of duplicated constitution. Signals from a frame signal source 6-a of the system 0, a frame signal source 7-a of the system 1, a clock source 8-a of the system 0 and a clock source 9-a of the system 1 are inputted respectively to selectors 4, 5 via lines 6-b-9-b. The selector 4 is used for changeover of the frame signal and the selector 5 is used for changeover of the clock signal. Either of the selectors of the systems 0, 1 is selected by using a changeover control signal 10.

3. 发明专利

JPS62178035A BIT SYNCHRONIZING CIRCUIT 失效
公开(公告)号：JPS62178035A
公开(公告)日：1987-08-05
申请号：JP1793786
申请日：1986-01-31
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SHIBUKAWA MASARU , AMADA EIICHI , ASANO KENICHI
IPC分类号： H03K5/00 , G01R31/3185 , H04L7/00 , H04L7/02
摘要： PURPOSE:To attain on-line monitor by operating a bit synchronizing circuit independently of an input data by the external direct start and observing the result externally so as to reduce the test pattern of check at manufacture. CONSTITUTION:When the level of a control signal SEL selecting a bit synchronizing circuit is logical '1' and the level of a write/read designation signal R/S is logical '0', the output of an AND gate 316 goes to logical '1' and external write is applied in this case. The logical '1' of the gate 316 resets a FF 308. The internal state is read by bringing the level of the signal SEL and the signal R/W to logical '1' so as to bring tri-state gates 336-340 to the output state and to output the output of FFs 319, 324, 332 and 312 to a data bus DB. As to the function test of the counter, the operation of the counter is observed directly externally by applying directly a TEST signal to a clock terminal (NAND gate 313) of the counter and outputting the state of the count-up of the counter to the bus DB in the read mode of a processor depending on the change in the TEST signal.

4. 发明专利

JPS6294050A SWITCHING SYSTEM FOR DUPLICATING DEVICE 失效
公开(公告)号：JPS6294050A
公开(公告)日：1987-04-30
申请号：JP23329485
申请日：1985-10-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KUWABARA HIROSHI , SHIBUKAWA MASARU , IZUMIDA YUJI
IPC分类号： H04Q11/04 , G06F11/20 , H04B1/74 , H04M3/22
摘要： PURPOSE:To eliminate such a trouble that master and slave devices come to be present systems by providing a means setting an opposite side slave device to be duplicated in a standby state to each duplication slave device with the aid of information from the master device through a data highway. CONSTITUTION:The master device 1 and the slave devices 2-1 and 2-2 are linked through the highway 3 being a common communication line. The devices 2-1 and 2-2 are equipped with lead wires 4 and 5 generating an RST signal making either one of the devices 2-1 and 2-2 into an auxiliary system when the remaining device is switched to a present system with the aid of a present/ auxiliary switching information from the device 1. When the input part of the slave device through the highway 3 develops troubles with the device 2-2 automatically becomes an auxiliary system by resetting 4 if switching information making the device 2-1 into a present system is transmitted to the device 2-1 from the device 1. Accordingly such a trouble that both devices become present systems can be avoided.

5. 发明专利

JPS6330099A CHANNEL MEMORY OPERATION CONTROL SYSTEM FOR TIME DIVISION SWITCH 失效
公开(公告)号：JPS6330099A
公开(公告)日：1988-02-08
申请号：JP17164786
申请日：1986-07-23
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： ASANO KENICHI , AMADA EIICHI , SHIBUKAWA MASARU
IPC分类号： H04Q3/52 , H04Q11/04
摘要： PURPOSE:To attain low power by storing idle/busy management information of an output channel in a 2nd storage means for designating the read address of a 1st storage means for storing digital information by one inputted frame to replace the channel and reading the 1st storage means in case of the occupied state only thereby reducing the operating rate of the channel memory of the time division switch. CONSTITUTION:A one-frame serial signal from input highways 100-107 is subjected to serial/parallel conversion at each channel by variable delay shift registers 130-137 and outputted to a selector 122 and fed to a speech path memory 120 while being selected sequentially. Then the read address is controlled by a control memory 121 to repace the channels. When information is written in the memory 120, the selector 124 selects a H-level fixed signal 127 and in case of data readout, the selector selects an idle/busy management bit 128 of the memory 121. AND gates 150-157 use the output of bit 128 and the memory 120 to bring all bits of idle output channels to a L level. Shift registers 140-147 apply serial convertion to parallel data being outputs of the memory 120 to apply output phase adjustment among output highways 110-117.

6. 发明专利

JPH04177527A ARITHMETIC PROCESSING CIRCUIT 失效
公开(公告)号：JPH04177527A
公开(公告)日：1992-06-24
申请号：JP30538690
申请日：1990-11-09
申请人： HITACHI LTD
发明人： SHIBUKAWA MASARU
IPC分类号： G06F9/22 , G06F7/00
摘要： PURPOSE:To execute the data transfer at high speed by providing a transfer path for transferring data inputted to an arithmetic part in parallel to the arithmetic part, and an output selecting part which can output alternatively an output signal of the arithmetic part and a transfer signal of the transfer path in response to a control signal. CONSTITUTION:By providing a transfer path 100 for transferring data inputted to an arithmetic part which can execute an arithmetic processing of input data, in parallel to the arithmetic part, and also, an output selecting part 101 which can output alternatively an output signal of the arithmetic part and a transfer signal of the transfer path in response to a control signal, an arithmetic circuit is constituted. That is, by the transfer path 100, transfer data is transferred in parallel to the arithmetic part, and by the output selecting part 101, a transfer signal of this transfer path 100 is selected. In such a way, the data transfer can be executed without passing through the arithmetic part, and the data transfer can be executed at a high speed.

7. 发明专利

JPS5879329A CLOCK SYNCHRONISM CIRCUIT 失效
公开(公告)号：JPS5879329A
公开(公告)日：1983-05-13
申请号：JP17749981
申请日：1981-11-05
申请人： HITACHI LTD
发明人： SHIBUKAWA MASARU , NAKAMURA HIDEO
IPC分类号： H04L7/02 , G06F1/12 , H03K5/00
摘要： PURPOSE:To simplify the constitution and to improve the tracking at the changeover of a clock selection signal, by directly synchronizing an asynchronous clock with a basic clock. CONSTITUTION:Flip-flops F21, F22 and F23 in a synchronizing circuit are normally reset. On the other hand, the leading of an external clock phiE is detected with a delay circuit 11, an inverter 12 and an AND gate 13 and the F21 is set. When an internal clock phi1 is ''0'', that is, when the clock is ''1'' at an inverter 14, after the F21 is set, the output of the F21 is fetched and set at the F22 of the next stage. The F23 latches the content of the F22 when the phi1 is ''0'' and a phi2 is ''1''. The F22 and F23 are to be fetched when the clocks are ''1'' at phi1=''0'' and phi2=''1'', and when the phiE is changed at this time, the F21-F23 are conductive and the change in the phiE is directly transmitted. When the F23 is set, the F22 is reset at phi2=''1'' at the latter half the phiE=''1'' afterward.

8. 发明专利

JPS5731055A Program control system 失效
标题翻译：程序控制系统
公开(公告)号：JPS5731055A
公开(公告)日：1982-02-19
申请号：JP10498980
申请日：1980-08-01
申请人： Hitachi Ltd
发明人： NAKAMURA HIDEO , SHIBUKAWA MASARU , KIHARA TOSHIMASA
IPC分类号： G06F11/22 , G06F9/48
CPC分类号： G06F9/4812
摘要： PURPOSE:To simplify an auxiliary program such as diagnosis of a fault, etc., by providing in advance at least two interruption addresses on an interruption address generation device, and selecting a program jump destination by a mode designating signal from the outside. CONSTITUTION:A mode signal MODE is inputted to one 2 input AND gate 14, and an inverted signal by an inverter 13 is inputted to the other 2 input AND gate 15. To the other input terminal of these gates 14, 15 is inputted a software interruption request SWI, and an output of the gate 14 and an output of the gate 15 control an AND gate 16 and an AND gate 17, respectively. In this case, when the interruption SWI has been generated by a mode ''1'' from the outside, a jump destination address in an address memory 20 is outputted through the gate 16, and when the interruption SWI has been generated by a mode ''0'', a jump destination address in an address memory 21 is outputted through the AND gate 17.
摘要翻译：目的：通过提前在中断地址生成装置上提供至少两个中断地址来简化诸如故障诊断等辅助程序，并且通过来自外部的模式指定信号来选择程序跳转目的地。构成：模式信号MODE被输入到一个2输入与门14，并且反相器13的反相信号被输入到另一个2输入与门15.对这些门14,15的另一输入端输入软件中断请求SWI，门14的输出和门15的输出分别控制与门16和与门17。在这种情况下，当从外部通过模式“1”产生中断SWI时，通过门16输出地址存储器20中的跳转目标地址，并且当通过模式生成中断SWI时 “0”，通过与门17输出地址存储器21中的跳转目标地址。

9. 发明专利

JPS5458184A SEQUENCE CONTROL CIRCUIT 失效
公开(公告)号：JPS5458184A
公开(公告)日：1979-05-10
申请号：JP12451577
申请日：1977-10-19
申请人： HITACHI LTD
发明人： YAMAGUCHI NOBORU , KIDA YUUZOU , SHIBUKAWA MASARU , MINORIKAWA KAZUO
IPC分类号： G05B19/02
摘要： PURPOSE:To enable the sequence cntrol circuit to be constituted without a logic change even when the object is changed by means of capabling of changing over a clock added to the timer of a sequence control circuit into whether a fixed frequency or a frequency proportional to an inherent constant of the control object. CONSTITUTION:1 is a timer for the purpose of progressing sequence control, and 2 is a multipex circuit, and a clock of a fixed frequency is added on a terminal 3, and a clock of a frequency proportional to an inherent constant of the control object, is added. A terminal 5 is the one to select whichever clock may be used, and when this terminal is zero, a clock from the teminal 3 is added, and when this terminal is 1, a clock from the terminal 4. is added to the timer 1.

10. 发明专利

JPH04216213A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH04216213A
公开(公告)日：1992-08-06
申请号：JP41053890
申请日：1990-12-14
申请人： HITACHI LTD
发明人： SHIBUKAWA MASARU
IPC分类号： H01L21/822 , G06F1/06 , H01L27/04 , H03K5/15 , H03K5/156
摘要： PURPOSE:To stablize a non-overlap clock regardless of the dispersion of elements or the change of operational environment. CONSTITUTION:A detection part 50 is provided to detect deviation information from prescribed non-overlap clock generation timing, and a correction part 60 is provided to correct the non-overlap clock generation timing based on this detected result. Thus, the non-overlap clock can be stablized regardless of the dispersion of elements or the operational environment change.

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