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1. 发明专利

JPH05188985A SPEECH COMPRESSION SYSTEM, COMMUNICATION SYSTEM, AND RADIO COMMUNICATION DEVICE 失效
公开(公告)号：JPH05188985A
公开(公告)日：1993-07-30
申请号：JP2327492
申请日：1992-01-13
申请人： HITACHI LTD
发明人： AKIYAMA HIROKI
IPC分类号： G10L15/02 , G10L19/00 , G10L25/00 , H04B1/38 , H04B1/3822 , H04B1/66 , H04K1/00
摘要： PURPOSE:To obtain technique for reducing the amount of information in speech signal transmission. CONSTITUTION:A speech recognition part 13 extracts feature parameters of a speech from a speech signal to be transmitted and a coding part 14 codes the speech recognition result corresponding to previously defined character codes or word codes to greatly decrease the amount of information. Further, the speech compression system which extracts the feature parameters of the speech from the speech signal and codes them is employed as the communication system to improve the efficiency of a communication. This communication system is applied to the radio communication device to improve the efficiency of a radio communication and increase speech channels.

2. 发明专利

JPH0371723A CODEC 失效
公开(公告)号：JPH0371723A
公开(公告)日：1991-03-27
申请号：JP20678689
申请日：1989-08-11
申请人： HITACHI LTD
发明人： AKIYAMA HIROKI
IPC分类号： H03M1/02
摘要： PURPOSE:To attain echo suppression at a pre-stage of an A/D converter by providing a gain adjustment means attaining the gain adjustment of a transfer function in a pre-balance circuit as an echo suppression circuit. CONSTITUTION:The balance circuit (BN) coefficient setting control is implemented automatically by a decision control circuit 50 at BN coefficient mode setting. The decision control circuit 50 is provided with a difference detection system 51 obtaining the difference of the result of echo suppression as to 2 kinds of BN coefficients and a BN controller 27 controlling a BN coefficient ROM 12 and selectors 6, 19, 23 and deciding a proper BN coefficient in the line based on the result of difference detection. Moreover, a pre BN controller 28 controlling the gain adjustment of a transfer function in the pre- balance circuit 30 is provided. Thus, the gain of the transfer function is adjusted and the gain adjustment in response to the frequency characteristic of the echo transfer function is attained. Thus, the effect of echo suppression at the pre- stage of the A/D converter is improved.

3. 发明专利

JPH06303268A PHASE COMPARATING CIRCUIT AND DEMODULATING CIRCUIT PROVIDING THE SAME 失效
公开(公告)号：JPH06303268A
公开(公告)日：1994-10-28
申请号：JP31060693
申请日：1993-12-10
申请人： HITACHI LTD
发明人： MATSUBARA OSAMU , YOKOTA MITSUKUNI , IGARASHI YUUKI , ISHIHARA HAYATO , YAMAKIDO KAZUO , OKAZAKI TAKAO , FURUKAWA KATSUHIRO , AKIYAMA HIROKI
IPC分类号： H03D3/00 , H03D3/14 , H04L27/22 , H04L27/227
摘要： PURPOSE:To execute phase comparison with high precision in a phase comparing circuit. CONSTITUTION:The circuit is the phase comparing circuit for detecting phase difference between an input signal VIN and a referring signal LO to be reference. It is provided with a phase difference detecting means 20 outputting a pulse with pulse width corresponding to phase difference between the input signal VIN and the referring signal LO, a voltage converting means 11 converting the pulse outputted from the phase difference detecting means 20 into a voltage value corresponding to the pulse width of the pulse, an analog/ digital converting means 13 converting the voltage value outputted from the voltage converting means 11 into a digital value based on the voltage value to be reference, an adjusting means 12 adjusting the voltage value to be reference in the analog/digital converting means 13 and a control means 41 controlling the adjusting means to execute adjustment and outputting an adjusting signal for adjustment.

4. 发明专利

JPH03211718A METHOD OF MARKING 失效
公开(公告)号：JPH03211718A
公开(公告)日：1991-09-17
申请号：JP572090
申请日：1990-01-13
申请人： HITACHI CABLE , HITACHI LTD
发明人： KASHIWA MIKIO , AKIYAMA HIROKI , SASAKI YUKIO , KAWAI NAOYUKI
IPC分类号： B41M5/00 , B41M5/26 , B44B7/00 , H01L21/02
摘要： PURPOSE:To facilitate marking and removal of deposit by making a groove composing an identification pattern in the specified region in a wafer and chemically corroding a section including the specified region in the direction of the depth of the groove. CONSTITUTION:The surface of a GaAs wafer of 3 inches in diameter is processed by mirror finish, the rear thereof is finished by etching after lapping, and the surface is marked. A YAG laser is used as a laser and beams are applied and scanned to the face of the wafer 1 for marking. After the marking, the surface of the wafer is removed by a thickness of 45mum by etching and mirror finish. In this case, in spite of removal of the surface having an about 5mum deep groove by a thickness of 45mum, the groove advances in the direction of the depth and is kept as deep as in the marking and widened only a little because of chemical polishing in the etching and mirror finish and no trouble such as unclear marking is caused.

5. 发明专利

JPS62293660A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS62293660A
公开(公告)日：1987-12-21
申请号：JP13591186
申请日：1986-06-13
申请人： HITACHI LTD
发明人： AKIYAMA HIROKI , NISHIHARA TATSUYA
IPC分类号： H01L21/822 , H01L21/82 , H01L27/02 , H01L27/04
摘要： PURPOSE:To perform development accompanied by change in specifications efficiently, by arranging the sides of a plurality of functional circuit blocks having the same length at the neighboring positions, and making it possible to perform movement as a circuit block unit such as addition and removal of the circuit blocks. CONSTITUTION:This device is divided into two parts, i.e., analog circuits A1-A3 and digital circuits D1-D4. The layout of internal circuits is set so that the longitudinal lengths of the blocks A1-A3 and the blocks D1-D4 become equal. The blocks D1-D4 are connected with an interconnection area DL, and the blocks A1-A3 are connected with an interconnection area AL. When the blocks A2 and D3 are removed, the block A1 is moved to contact with the block A3, and the block D4 is moved to contact with the block D2. Then the lateral lengths of the areas AL and DL and a guard interconnection GR are shortened in correspondence with the lateral lengths of the blocks A2 and D3. Therefore the layout at the time of change becomes easy.

6. 发明专利

JPH04296118A REFERENCE VOLTAGE CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE USING SAME 失效
公开(公告)号：JPH04296118A
公开(公告)日：1992-10-20
申请号：JP6148491
申请日：1991-03-26
申请人： HITACHI LTD
发明人： SUGITA TOMOAKI , YAMAGUCHI TOSHIO , MORITA MASAYUKI , AKIYAMA HIROKI
IPC分类号： H03M1/10 , H03M1/12 , H03M1/18 , H03M1/66
摘要： PURPOSE:To realize a semiconductor integrated circuit device by forming a circuit forming a reference voltage with a variable reference voltage circuit so as to conduct the test of a built-in conversion circuit even at an aging test. CONSTITUTION:A variable reference voltage voltage 9 converting an analog signal inputted to a CODEC into a relevant digital signal consists of a comparator circuit CMP 1, a voltage conversion circuit CNV coupled with one input terminal (positive terminal) of the CMP 1 and a variable resistor circuit 16 coupled with an output terminal of the CMP 1, The other input terminal (negative terminal) and in which control terminals CT1, CT2 are connected. In this case, since the resistace of the resistor connected between an output terminal and the other input terminal of the comparator circuit CMP 1 and the resistance of the resistor connected between the other input terminal (negative terminal) and the ground potential of the circuit are varied by a control signal fed to the control terminals CT1, CT2, the reference voltage outputted from the comparator circuit CMP 1 is varied.

7. 发明专利

JPH0321149A PULSE GENERATING CIRCUIT 失效
公开(公告)号：JPH0321149A
公开(公告)日：1991-01-29
申请号：JP15456189
申请日：1989-06-19
申请人： HITACHI LTD
发明人： AKIYAMA HIROKI , NISHIHARA TATSUYA
IPC分类号： H04M3/02 , H03K21/40 , H03K23/66 , H04M1/00
摘要： PURPOSE:To prevent the generation of noise at the time of switching a tone by comparing the value of a counter with a tone specification code by a comparator, and when both the values coincide with each other, resetting the counter to determine the frequency of a generated pulse. CONSTITUTION:If the output of a coincidence detecting circuit 7 is turned to a high level when '1010' is inputted to a latch circuit 6, the output Qa of a flip flop FFa is turned to the high level and the counter 1 is reset. Since the value of the counter 1 is changed, the output of the circuit 7 is immediately turned to the low level. On the other hand, the output Qa of the FFa is supplied to a frequency dividing circuit 8 as a clock. Thereby, a coincidence detecting signal is outputted in each time required for the counter 1 to count up the value inputted to a latch circuit 6 and pulse string P to be changed at 16 times the period of the signal is outputted from the circuit 8. Since a speaker is driven based upon the pulse string P, the tone of frequency f1 corresponding to a code in the latch circuit 6 is generated.

8. 发明专利

JPH02250406A SIGNAL GENERATING CIRCUIT 失效
公开(公告)号：JPH02250406A
公开(公告)日：1990-10-08
申请号：JP7061989
申请日：1989-03-24
申请人： HITACHI LTD
发明人： AKIYAMA HIROKI , NISHIHARA TATSUYA
IPC分类号： H03B28/00
摘要： PURPOSE:To prevent malfunction by connecting half latch circuits in cascade to constitute a shift register, and operating each half latch circuit with at least 3 clocks of equal phase having a pulse width whose duty ratio is

9. 发明专利

JPS63232607A AMPLITUDE CONTROL DEVICE FOR PERIODICAL FUNCTION SIGNAL 失效
公开(公告)号：JPS63232607A
公开(公告)日：1988-09-28
申请号：JP6391387
申请日：1987-03-20
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： YAMAMOTO TADATAKA , NISHIHARA TATSUYA , AKIYAMA HIROKI , YAMAKIDO KAZUO , MASUMURA ATSUO
IPC分类号： H03G3/00 , H03G3/02 , H04M15/00
摘要： PURPOSE:To improve the S/N by providing plural signal attenuation elements attenuating an analog periodical function signal level, a switch element selecting each signal attenuation element and a control means applying gradual increase/ decrease control to a prescribed phase of the analog periodical function signal in nearly ramp shape so as to miniaturize the circuit scale. CONSTITUTION:In instructing the output start of a sine wave signal to an up- down counter COUNT 1, switch control signals phi0-phin are brought into a high level in a form of pulse alternately in the order from all low levels to the phin-phi0. Switch elements SWn-SW0 are subject to switch control in order to control the amplitude of the sine wave signal Vin. Then, an output analog signal Vout increased gradually in nearly ramp shape of a stepwise shape is obtained at an output terminal of an inverting amplifier circuit 1 in the amplitude of the sine wave signal Vin. Thus, the production of overshoot and undershoot at the start and the end of the output sine wave signal Vout is prevented.

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