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1. 发明专利

JP2006080354A Manufacturing method of misfet 审中-公开
标题翻译： MISFET的制造方法
公开(公告)号：JP2006080354A
公开(公告)日：2006-03-23
申请号：JP2004263783
申请日：2004-09-10
申请人： Toshiba Corp , 株式会社東芝
发明人： AKASAKA YASUSHI , MIYAGAWA KAZUHIRO , SASAKI TAKAOKI
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/49
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of an MISFET having high current driving ability and low power consumption in the MISFET provided with a gate electrode of damascene structure.
SOLUTION: Source/drain diffusion layers (14, 15) are formed on the surfaces of a silicon substrate 1, and a silicide layer 17 is formed on the surface thereof. Then, an interface layer 21 is formed on the silicon substrate 1 at the bottom of a gate opening groove 20 partitioned by gate side walls (12, 13) at a temperature ≤550°C, a High-k film 22 is deposited to cover the interface layer 21 and an interlayer insulating film 19 in the gate opening groove 20, and a heat treatment is carried out at a temperature ≤550°C. Then, after a conductor film 23 and a metal film 24 covering the whole surface are formed, unnecessary portion on the interlayer insulating film 19 is polished and removed by CMP method to form the MISFET provided with the metal gate electrode of damascene structure.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种在具有镶嵌结构的栅电极的MISFET中具有高电流驱动能力和低功耗的MISFET的制造方法。解决方案：在硅衬底1的表面上形成源极/漏极扩散层（14,15），并且在其表面上形成硅化物层17。然后，在栅极开口槽20的底部，在硅衬底1上形成界面层21，栅极开口槽20在温度≤550℃下被栅极侧壁（12,13）分隔，高K膜22沉积到覆盖层界面层21和栅极开口槽20中的层间绝缘膜19，并且在≤550℃的温度下进行热处理。然后，在形成覆盖整个表面的导体膜23和金属膜24之后，通过CMP方法对层间绝缘膜19上的不需要的部分进行抛光和去除，以形成设置有镶嵌结构的金属栅电极的MISFET。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2006108602A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006108602A
公开(公告)日：2006-04-20
申请号：JP2004354791
申请日：2004-12-08
申请人： Toshiba Corp , 株式会社東芝
发明人： AKASAKA YASUSHI , MIYAGAWA KAZUHIRO , SASAKI TAKAOKI
IPC分类号： H01L27/092 , C23C16/34 , H01L21/28 , H01L21/8238 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L29/517 , H01L21/28088 , H01L21/823842 , H01L21/823857 , H01L29/4958 , H01L29/4966 , H01L29/7833
摘要： PROBLEM TO BE SOLVED: To form a high performance complementary MISFET by increasing both electron and hole mobilities of a MISFET using a high-k film. SOLUTION: A p well layer 2 and an n well layer 3 are formed in the front surface of a silicon substrate 1. In an n channel MISFET partitioned by an element isolation region 4; an n channel interface layer 5 without nitrogen addition, an n channel high dielectric gate insulating film 6 without the nitrogen addition, and an n channel gate electrode 7, are formed. And, an n-type source/drain diffusion layer 8 is prepared. With respect to this, in a p channel MISFET; a p channel interface layer 9 with nitrogen addition, a p channel high dielectric gate insulating film 10, and a p channel gate electrode 11, are formed. And, a p-type source/drain diffusion layer 12 is prepared. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过增加使用高k膜的MISFET的电子和空穴迁移率来形成高性能互补MISFET。解决方案：在硅衬底1的前表面中形成p阱层2和n阱层3.在由元件隔离区4分隔的n沟道MISFET中; 没有氮添加的n沟道界面层5，没有氮添加的n沟道高介电栅极绝缘膜6和n沟道栅电极7。并且，制备n型源极/漏极扩散层8。关于此，在p沟道MISFET中; 形成具有氮添加的p沟道界面层9，p沟道高介电栅极绝缘膜10和p沟道栅电极11。并且，制备p型源极/漏极扩散层12。版权所有（C）2006，JPO＆NCIPI

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