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1. 发明专利

JP2004080334A Packet transfer circuit in ip over atm 审中-公开
标题翻译： ATM中的IP分组传输电路
公开(公告)号：JP2004080334A
公开(公告)日：2004-03-11
申请号：JP2002237347
申请日：2002-08-16
申请人： Fujitsu Ltd , Nippon Telegr & Teleph Corp , 富士通株式会社 , 日本電信電話株式会社
发明人： KOTANI KUNIHIRO , SUZUKI KAZUYUKI , OMOTANI MASAAKI , UGA MASANORI , SHIOMOTO KOHEI
IPC分类号： H04L12/951 , H04L12/66 , H04L13/08 , H04L12/56
摘要： PROBLEM TO BE SOLVED: To obtain a packet transfer circuit in IP over ATM exhibiting a maximum packet transfer capacity by performing read, write and refresh within a predetermined period using an SDRAM. SOLUTION: A packet processing section comprises a buffer memory consisting of a plurality (n) of SDRAMs accessible in parallel, a serial/parallel converter receiving input packets in series and delivering them in parallel, and a parallel/serial converter for storing a plurality of parallel signals read out from the buffer memory and generating an output packet. Three operations, i.e. an operation for storing packets in the serial/parallel converter and writing them simultaneously in parallel into respective SDRAMs, an operation for storing signals read out from the SDRAMs in the parallel/serial converter, and a refresh operation, are performed within the refresh period. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：通过使用SDRAM在预定时段内执行读，写和刷新，以获得具有最大分组传送容量的ATM中的IP中的分组传送电路。解决方案：分组处理部分包括由可并行访问的多个（n个）SDRAM组成的缓冲存储器，串行/并行传输输入数据包的串行/并行转换器，以及并行传送它们的并行/串行转换器从缓冲存储器读出的多个并行信号并产生输出分组。三个操作，即将串行/并行转换器中的数据包存储在各个SDRAM中并行并行写入的操作，用于存储从并行/串行转换器中的SDRAM读出的信号的操作和刷新操作，刷新周期。版权所有（C）2004，JPO

2. 发明专利

JP2004158903A Packet processing apparatus 有权
公开(公告)号：JP2004158903A
公开(公告)日：2004-06-03
申请号：JP2002319917
申请日：2002-11-01
申请人： Fujitsu Ltd , 富士通株式会社
发明人： SUZUKI KAZUYUKI , URYU SHIRO
IPC分类号： H04L12/70 , H04L12/44 , H04L12/56
CPC分类号： H04L49/602 , H04L45/7453 , H04L49/3009 , H04L49/3027
摘要： PROBLEM TO BE SOLVED: To provide a packet processing apparatus for enhancing entire the relay processing performance by using a plurality of packet analysis modules to process the received packets distributedly. SOLUTION: The packet processing apparatus includes: a distribution means for attaching a serial number to the received packet and distributing the resulting packets; a plurality of packet analysis means 22 1 to 22a for executing information analysis processing of the packets distributed from the distribution means in parallel; and a sequence correction means 24 receiving the packets from a plurality of the packet analysis means, sorting the packets in the orders of the serial numbers attached to the packets, and providing an output. Thus, a plurality of the packet analysis means process the received packets distributedly to enhance the entire relay processing performance. COPYRIGHT: (C)2004,JPO

3. 发明专利

JP2004343422A Atm device provided with header conversion function 审中-公开
公开(公告)号：JP2004343422A
公开(公告)日：2004-12-02
申请号：JP2003137520
申请日：2003-05-15
申请人： Fujitsu Ltd , 富士通株式会社
发明人： SUZUKI KAZUYUKI
IPC分类号： H04L12/70 , H04L12/56
摘要： PROBLEM TO BE SOLVED: To perform the housing change of an input identifier (address value) including the change of the using length of the VPI/VCI of an input cell in an online state (cell conducting state) and to quicken the housing change relating to an ATM device provided with a header conversion function using the input identifier for which input header information is degenerated. SOLUTION: The ATM device is provided with means 1-2a and 1-2b for holding input identifier generation information for generating two kinds of the input identifiers from the VPI/VCI of the input cell, means 1-1a and 1-1b for generating the two kinds of the input identifiers according to the two kinds of the input identifier generation information, a means 1-3 for selecting and outputting one of the two kinds of the input identifiers, a header information storage memory 1-6 having two surfaces of address spaces corresponding to the two kinds of the input identifiers and storing header information data after header conversion with the respective input identifiers as addresses, and means 1-7 and 1-8 for transferring stored data between the surfaces for the header conversion information storage memory. COPYRIGHT: (C)2005,JPO&NCIPI

4. 发明专利

JP2000031971A LINE ADAPTOR 失效
公开(公告)号：JP2000031971A
公开(公告)日：2000-01-28
申请号：JP19289998
申请日：1998-07-08
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD
发明人： AMANO MITSUHARU , TOMONAGA HIROSHI , SUZUKI KAZUYUKI , MATSUO SATOSHI , OMOTANI MASAAKI , GENDA KOICHI , DOI YUKIHIRO , WATABE KAZUO , TSUCHIDA TOMOHIRO
IPC分类号： H04L1/22 , H04L12/28 , H04L12/70 , H04L12/713 , H04L12/775 , H04L12/935 , H04Q3/00
摘要： PROBLEM TO BE SOLVED: To prevent missing, duplication of cells and inversion of cell sequence in a switching state of a duplicate system in the case that the line adaptor provided to an ATM exchange, and composed of active/standby systems adds system identification information to a cell received by each system, writes the cell to a storage means, and reads the cell therefrom and outputs it. SOLUTION: The line adaptor 100 is provided with a read end detection means 110 that monitors cells arriving before switching which have been stored in storage means 102 of both the systems and detects that all the cells having arrived before switching are read when receiving an instruction externally to switch an operating state of both systems. An each-system identifier addition means 101 revises system identification information to be added to each cell, with a read stop means 120 that stops reading of cells stored in the storage means when the means 110 detects that all the cells having arrived before switching are read, and a read restart means 130 that restores reading of cells stored in each storage means when the means 120 stops reading of the cells stored in the storage means 102 of both the systems.

5. 发明专利

JPH11355292A ATM LAYER PROTECTION SYSTEM AND ITS DEVICE 失效
公开(公告)号：JPH11355292A
公开(公告)日：1999-12-24
申请号：JP16187598
申请日：1998-06-10
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , HITACHI LTD
发明人： KAWARAI KENICHI , SUZUKI KAZUYUKI , GENDA KOICHI , DOI YUKIHIRO , HAGIO MASAMI , AZUMA TAKAAKI , MORIWAKI NORIHIKO , MAKIMOTO AKIO
IPC分类号： H04Q3/00 , H04L12/28 , H04L12/707 , H04L12/711 , H04L12/713
摘要： PROBLEM TO BE SOLVED: To efficiently perform high-reliability ATM layer protection with a simple constitution and easy control with respect to a ATM layer protection system and its device. SOLUTION: In the ATM layer protection system which protects a protection section against communication interference by an ATM layer, plural nodes 10A and 10B are provided which mutually hold connection information of an active system and a standby system for the protection section, and the fault detection node 10B which have detected the communication interference of the active system connection at the end point of the protection section generates a connection switching request cell specifying the faulty connection and transmits the cell to the counter node 10A, and the fault detection node and the counter node switch the faulty connection to the standby system connection at the timings of transmission and reception of the connection switching request cell.

6. 发明专利

JPH0730555A CELL ABORT DEVICE 失效
公开(公告)号：JPH0730555A
公开(公告)日：1995-01-31
申请号：JP17339893
申请日：1993-07-13
申请人： NEC CORP , NIPPON TELEGRAPH & TELEPHONE , HITACHI LTD , FUJITSU LTD , OKI ELECTRIC IND CO LTD
发明人： HONDA MASAHIKO , SUZUKI KOJI , SHIOMOTO KOHEI , SUGANO TAKAYUKI , SUZUKI KAZUYUKI , KIMURA NAOHIRO , ARAI KAZUHIRO
IPC分类号： H04Q3/00 , H04L12/24 , H04L12/26 , H04L12/28 , H04Q11/04
摘要： PURPOSE:To recognize the kind of a cell fault and the frequency of occurrence of the fault in details by checking abort causes of a call in an abort cell storage memory and totalizing the check results. CONSTITUTION:The write from a fault cell detection line 13 to an abort cell storage memory 2 is attained only to an area not in use in the abort cell storage memory 2 or an area whose read is already finished by the software. Then a processor 4 reads a count of a reduction cell counter 3 through an interface signal line 42. Furthermore, the processor 4 clears the count of the reduction cell counter 3 through the interface signal line 42, and an overflowed count is prevented by clearing the count at a proper period. The exchange software obtains the count of the counter 3 and the cell control information stored in the memory 2 as information as to the abort of the fault cell. Thus, the kind and the frequency of occurrence of a fault is recognized in details as to the cell.

7. 发明专利

JPH03126147A TEST SYSTEM FOR EXTERNAL STORAGE DEVICE 失效
公开(公告)号：JPH03126147A
公开(公告)日：1991-05-29
申请号：JP26460889
申请日：1989-10-11
申请人： FUJITSU LTD
发明人： SUZUKI KAZUYUKI
IPC分类号： G06F12/16 , G06F11/22
摘要： PURPOSE:To save a memory and to shorten a test time by suppressing write of check bits to write only data at the time of reading out data written in an external storage device to write it in the test data area of the memory and detecting data error at the time of reading out data from the test data area by a processor. CONSTITUTION:Data to be written in an external storage device 12 is generated in a test data area of a memory means 13 by a processor 11 and is written in the external storage device 12; and when written data is read out and is written in the test data area 21 of the memory means 15, write of data bits is suppressed by a suppressing means 17 and only data is written in a data part 14 of the memory means 13. When the processor 11 reads out the test data area 21 of the memory means 13, data error is detected in an error detecting means 16 by noncoincidence between the data part 14 of the memory means 13 and a check bit part 15 in the case of abnormality of data. The external storage device 12 is tested in this manner. Since it is sufficient if one test data area 21 is reserved, the memory is saved and the test time is shortened.

8. 发明专利

JP2000115273A DATA TRANSFER EQUIPMENT 失效
公开(公告)号：JP2000115273A
公开(公告)日：2000-04-21
申请号：JP27811198
申请日：1998-09-30
申请人： NEC CORP , NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD , OKI ELECTRIC IND CO LTD
发明人： YOKOUCHI HIDEAKI , MINAMIMURA KEIZO , GENDA KOICHI , OMOTANI MASAAKI , SUZUKI KAZUYUKI , MATSUO SATOSHI , UCHINO KENICHI
IPC分类号： G06F13/38 , G06F1/12 , H04L25/02 , H04L25/40 , H04L29/02
摘要： PROBLEM TO BE SOLVED: To reduce the number of terminals of an LSI or a printed board by making a clock signal and a synchronous signal of a control information signal common with a clock signal and a synchronous signal of a user information signal. SOLUTION: This data transfer equipment is provided with a cell data transmission processing part 20 on a master side to transmit and receive a user information signal, a cell data reception processing part 23 at the master side, a control bus transmission control part 22 on the master side to transmit and receive the control information signal and a control bus reception control part 28 at the master side. And the clock signal and the synchronizing signal of the control information signal are made common with the clock signal and the synchronizing signal of the user information signal. Namely, a cell transmission clock signal and a cell synchronizing signal are used as a clock signal for transmission of the control signal and a synchronizing signal for the control signal when the control bus signal is transmitted by the control bus transmission control part 22 on the master side. Therefore, the cell transmission clock signal and the cell synchronizing signal are supplied to the control bus transmission control part 22 at the master side as the control bus synchronizing signal 21 by the cell data transmission processing part 20 on the master side.

9. 发明专利

JPH10233781A ATM CHANNEL INTERFACE 失效
公开(公告)号：JPH10233781A
公开(公告)日：1998-09-02
申请号：JP3579097
申请日：1997-02-20
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , NEC CORP , FUJITSU LTD , OKI ELECTRIC IND CO LTD
发明人： KOBASHI ICHIRO , MIYAGI MORIHITO , NAGATO YUJI , TAKAGI KOJI , MORIZAKI SHIGEKI , TADOKORO NAOAKI , SETO HAJIME , SUZUKI KAZUYUKI , KOIKE TAKESHI
IPC分类号： H04Q3/00 , H04L12/26 , H04L12/28
摘要： PROBLEM TO BE SOLVED: To realize diagnosis of normality of duplicated speech channels by a simple configuration without giving effect on a speech channel of an active system in the case that one end of the interface connects to a channel and the other end is connected to an ATM switch. SOLUTION: The ATM channel interface 2 having two systems, active system (r) and standby system (w) is divided into a plurality of function blocks 3, 4, and one function block is provided with a test function section 41 that generates/ inserts a test cell and extracts/checks the test cell reflected from an external circuit and with a multiplex selector 42 that selects both the test cell and a speech channel signal cell of the active system (r) and passes them. A function aborting the test cell is provided for the function block of the active system connecting to an active system channel 9r.

10. 发明专利

JPH06131301A TERMINAL CONNECTION MANAGING DEVICE 失效
公开(公告)号：JPH06131301A
公开(公告)日：1994-05-13
申请号：JP27640392
申请日：1992-10-15
申请人： FUJITSU LTD
发明人： MURAMATSU NORIAKI , SHIMOZAWA YASUO , SUZUKI KAZUYUKI
IPC分类号： G06F1/00 , G06F15/00 , G06F21/20
摘要： PURPOSE:To check a connectable terminal for each application program at every time zone by refusing a processing request, which does not satisfy access permission conditions set to a table, concerning the processing request accessed through a terminal equipment. CONSTITUTION:A time zone table, day of the week table or specified day table is provided for each processing function part 6, and a terminal ID or personal ID connectable to this table is registered. When the processing function part 6 of a host computer 1 is accessed from any terminal, the time, day of the week and date, when the access is performed, is read from the calendar table of an OS and it is checked by the relevant table whether the terminal ID or personal ID is registered on the relevant table and the access is enabled at that access time or not. Thus, it is not necessary to stop/restart the processing function part and further, the processing function part 6 can be prevented from being accessed by anybody excepting for the person concerned without permission.

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