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1. 发明专利

JPH10233781A ATM CHANNEL INTERFACE 失效
公开(公告)号：JPH10233781A
公开(公告)日：1998-09-02
申请号：JP3579097
申请日：1997-02-20
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , NEC CORP , FUJITSU LTD , OKI ELECTRIC IND CO LTD
发明人： KOBASHI ICHIRO , MIYAGI MORIHITO , NAGATO YUJI , TAKAGI KOJI , MORIZAKI SHIGEKI , TADOKORO NAOAKI , SETO HAJIME , SUZUKI KAZUYUKI , KOIKE TAKESHI
IPC分类号： H04Q3/00 , H04L12/26 , H04L12/28
摘要： PROBLEM TO BE SOLVED: To realize diagnosis of normality of duplicated speech channels by a simple configuration without giving effect on a speech channel of an active system in the case that one end of the interface connects to a channel and the other end is connected to an ATM switch. SOLUTION: The ATM channel interface 2 having two systems, active system (r) and standby system (w) is divided into a plurality of function blocks 3, 4, and one function block is provided with a test function section 41 that generates/ inserts a test cell and extracts/checks the test cell reflected from an external circuit and with a multiplex selector 42 that selects both the test cell and a speech channel signal cell of the active system (r) and passes them. A function aborting the test cell is provided for the function block of the active system connecting to an active system channel 9r.

2. 发明专利

JPS52104010A DRIVING SYSTEM FOR LOAD SIDE DEVICE ELECTRONIC EXCHANGER 失效
公开(公告)号：JPS52104010A
公开(公告)日：1977-09-01
申请号：JP1993476
申请日：1976-02-27
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： SEKI SHIGEO , YOSHIDA HIRONOBU , HATAKEYAMA HIDEHISA , KANEDA YOSHIHITO , YANAGIDA AKIRA , MUNAKATA KOUICHI , KAWATANI IKUO , TANABE SENICHI , SETO HAJIME , TSUCHIYA KENICHI
IPC分类号： H04Q1/20 , H04Q3/545
摘要： PURPOSE:To prevent the delay of normal operation of a system, by means of making the drive system usable even if in the case of load side trouble.

3. 发明专利

JPS57108942A ADDRESS STOP SYSTEM FOR OVERLAY PROGRAM 失效
公开(公告)号：JPS57108942A
公开(公告)日：1982-07-07
申请号：JP18474880
申请日：1980-12-25
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： SETO HAJIME , TANAKA TOSHIROU
IPC分类号： G06F11/28 , G06F11/36
摘要： PURPOSE:To improve debugging efficiency by stopping an address when a discrimination number given to each overlay program unit coincides with the address. CONSTITUTION:In a register PRR, a number with which an overlay program where an entry is passed is discriminated is stored by an execution control program EP. To a register SMR, an address and a program number are inputted. Then, a comparing circuit MAT generates an output only when the address reaches the specific address of a specific program, setting an inter- ruption flip-flop ISF. Then, the program being executed is stopped and the contents of various registers, a flip-flop group or a main storage device in a CPU are typed out.

4. 发明专利

JPS60175154A REPLACING METHOD OF INSTRUCTION 失效
公开(公告)号：JPS60175154A
公开(公告)日：1985-09-09
申请号：JP3101684
申请日：1984-02-21
申请人： FUJITSU DAIICHI TSUSHIN SOFT , FUJITSU LTD
发明人： SETO HAJIME , MIZUTA KAZUO , YONEZAKI WATARU
IPC分类号： G06F9/48 , G06F11/28 , G06F11/36
摘要： PURPOSE:To remove an interruption generating cause and to advance efficiently debugging by previously registering an instruction to be an instruction generating cause and setting up processing corresponding to an instruction registered in a replaced address information storing register. CONSTITUTION:If an instruction is executed when there is no speech path SP, I/O device I/O, or the like, the instruction to be an interruption generating cause is inputted and registered to/in a replaced instruction storing register (FNCR) 2. In addition, processing in stead of the instruction is registered in a registered address information storing register (PROR) 6 and its leading address is stored in a replaced address register (PRAR) 4. The contents of the intruction stored in an instruction storing register (IR) 1 are compared with that of the register ENCR2 by an instruction comparing function (COM) 3 every execution of the intruction. At the time of coincidence, the processing is executed in accordance with the contents of the register PROR6.

5. 发明专利

JPS5920064A Running route check system of overlay program 失效
标题翻译：运行路由检查系统的覆盖程序
公开(公告)号：JPS5920064A
公开(公告)日：1984-02-01
申请号：JP12989382
申请日：1982-07-26
申请人： Fujitsu Ltd
发明人： SETO HAJIME
IPC分类号： G06F11/28 , G06F11/34
CPC分类号： G06F11/34
摘要： PURPOSE:To record the running route in the range of designated address of an overlay program, by providing a function checking an address on an external storage device of the designated overlay program. CONSTITUTION:The address range of running route check is set to overlay program FM address designating registers OR1, OR2. On the other hand, pieces of command information at overlay lifting are stored in lifting information storage registers FMR1, FMR2 and TMR1. A running address storage condition control block 6 confirms the two conditions of FMR1
摘要翻译：目的：通过提供检查指定覆盖程序的外部存储设备上的地址的功能来记录覆盖程序的指定地址范围内的运行路由。规定：运行路由检查的地址范围设置为覆盖程序FM地址指定寄存器OR1，OR2。另一方面，在提升信息存储寄存器FMR1，FMR2和TMR1中存储叠加提升的命令信息。运行地址存储条件控制块6确认FMR1 <= OR1 <= FMR2和FMR1 <= OR2 <= FMR2的两个条件，并将运行地址存储在将地址转换成FM地址之后的时间点到存储存储器因此，通过检查存储器7的内容容易地识别指定的重叠程序的运行状态。

6. 发明专利

JPS62210553A TABLE ADDITION PROCESSING SYSTEM 失效
公开(公告)号：JPS62210553A
公开(公告)日：1987-09-16
申请号：JP5320286
申请日：1986-03-11
申请人： FUJITSU LTD , FUJITSU DAIICHI TSUSHIN SOFT
发明人： SETO HAJIME , YONEZAKI WATARU , TADA YOSHINORI
IPC分类号： H04M3/00 , G06F12/00 , G06F12/02 , G06F12/06 , H04Q3/545
摘要： PURPOSE:To add a bit of patch information without changing a table by rewriting an address based on the added position and the number of words of the bit of patch information, and the front/end address of the table. CONSTITUTION:When bits of patch information C', D', and E' are added between bits of information C and D in a table 1, first of all, they are stored at a patch information storage area 2. Next, a 1003rd address, 3 words, a 100B-th address, and a 2000-th address are accumulated respectively at an additional address storage register (INSR) 4, an additional word number storage register (WORD) 5, a table final address register (TBER) 6, and a patch forefront address storage register (PATR) 7. Next, the address value of a memory address register (MAR) 3 is decided through a rewrite execution deciding part (EXCJ) 11, and a comparison deciding part (COMP) 9 decides the moving range of bits of information D-I, and an address rewrite and the addition of the bit of patch information is performed by a memory address rewriting part (MARJ) 10.

7. 发明专利

JPS6075954A TRAP SYSTEM DURING ACCESS OF IO DEVICE 失效
公开(公告)号：JPS6075954A
公开(公告)日：1985-04-30
申请号：JP18371983
申请日：1983-09-30
申请人： FUJITSU LTD
发明人： SETO HAJIME
IPC分类号： G06F13/10 , G06F9/48 , G06F13/12
摘要： PURPOSE:To read the execution state of a central processor in a transmission mode of instruction by transmitting a trap signal from an IO device when the coincidence is obtained between an address which received an access from the central processor and a designated address. CONSTITUTION:When a central processor 3 gives an access to an IO device 8 via a data channel device 4, an IO device 5 produces a trap signal in case the coincidence is obtained between the relevant address and the address stored previously in a designated address store register 7. This trap signal is sent to the processor 3 via the device 4. The processor 3 stops its procesing when it receives the trap signal. Therefore it is possible to read the execution state of the processor 3 when an access is given to a specific address of the device 8 by reading the contents of an execution state store register 2 when the processor 3 stops its actuation.

8. 发明专利

JPH0553845A SYSTEM FOR TRANSFERRING INFORMATION BETWEEN FILE MEMORIES 失效
公开(公告)号：JPH0553845A
公开(公告)日：1993-03-05
申请号：JP20967991
申请日：1991-08-22
申请人： FUJITSU LTD
发明人： SETO HAJIME
IPC分类号： G06F11/16 , G06F11/20 , G06F12/00
摘要： PURPOSE:To shorten time for transferring information between file memories having duplex constitution concerning the system for transferring the information between the file memories. CONSTITUTION:The system equipped with the file memories having the duplex constitution is provided with a unit identifying means 1 to divide the information of the file memories into units, to store the information by adding numbers, to identify and output the unit number according to an address, unit reload display means 2 to identify the unit reloading the information when one file is off-lined, write processing means 3 to execute the write processing of the file in the case of receiving a file write instruction when one file is off-lined and to set reloading display to the relevant unit number of the unit reload display means 2, and transfer processing means 4 to confirm whether the reload of the transfer unit is displayed or not through the unit reload display means 2 in the case of receiving a file information transfer instruction when one file is off-lined and to transfer the information only when the reload is displayed.

9. 发明专利

JPS5839361A STOPPING SYSTEM FOR PROCESSOR 失效
公开(公告)号：JPS5839361A
公开(公告)日：1983-03-08
申请号：JP13666681
申请日：1981-08-31
申请人： FUJITSU LTD
发明人： OOMA TOSHIO , SETO HAJIME
IPC分类号： G06F12/16 , G06F11/07 , G06F11/28 , G06F15/16 , G06F15/177
摘要： PURPOSE:To reproduce fault occurrence conditions efficiently and securely, by stopping all processors from performing processing operation when specific data is written or readout to a specified address of a storage device. CONSTITUTION:To examine the cause of a fault in debugging operation, a specific address and specific data are set in the address specifying register 30 and data specifying register 11 of a storage device 60 from one of processors 1-1- 1-n. The device 60 transfers an address and data to coincidence detecting circuits 50 and 51 respectively every time the address and data from the processors 1-1-1-n are set in an address register 7 and a data register respectively. The circuit 50 compares the received access address with the specific address set in the register 30, and the circuit 51 compares the received data with the specific data in the register 10; when they coincide with each other, the circuits 51 and 51 output coincidence signals respectively. On receiving the signals, a gate 12 sends an operation stop signal to the processors 1-1-1-n.

10. 发明专利

JPS57113145A BIT-CORRESPONDENCE PROCESSING SYSTEM OF FLIP-FLOP GROUP 失效
公开(公告)号：JPS57113145A
公开(公告)日：1982-07-14
申请号：JP18828780
申请日：1980-12-29
申请人： FUJITSU LTD
发明人： SETO HAJIME
IPC分类号： G06F9/48 , G06F11/28 , G06F13/24
摘要： PURPOSE:To achieve correspondence processing by fractionizing the state of peripheral equipment by previously specifying the group number of a flip-flop and a bit position in it, and then generating an interruption signal to a CPU only when the state of the equipment is coincident. CONSTITUTION:A specifying register IDR is stored with a flip-flop group number and information on the specification of a bit position in the same group. A setting specifying part ST inputs the input information to a specification information terminal IDT and when a register-storage command terminal RST is specified, this input information is stored in the register IDR. With a set key STB pressed, the circuit of a condition discriminating part CDD starts to compare the states of flip-flops, which correspond to devices, from a terminal FFGm with the contents of the register IDR. Then when a flip-flop group bit coincident with the specified contents of the register IDR turns on, the output CCS of the discrimination part CDD is used as the interruption signal to the CPU, which is then stopped.

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