专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JPH11355292A ATM LAYER PROTECTION SYSTEM AND ITS DEVICE 失效
公开(公告)号：JPH11355292A
公开(公告)日：1999-12-24
申请号：JP16187598
申请日：1998-06-10
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , HITACHI LTD
发明人： KAWARAI KENICHI , SUZUKI KAZUYUKI , GENDA KOICHI , DOI YUKIHIRO , HAGIO MASAMI , AZUMA TAKAAKI , MORIWAKI NORIHIKO , MAKIMOTO AKIO
IPC分类号： H04Q3/00 , H04L12/28 , H04L12/707 , H04L12/711 , H04L12/713
摘要： PROBLEM TO BE SOLVED: To efficiently perform high-reliability ATM layer protection with a simple constitution and easy control with respect to a ATM layer protection system and its device. SOLUTION: In the ATM layer protection system which protects a protection section against communication interference by an ATM layer, plural nodes 10A and 10B are provided which mutually hold connection information of an active system and a standby system for the protection section, and the fault detection node 10B which have detected the communication interference of the active system connection at the end point of the protection section generates a connection switching request cell specifying the faulty connection and transmits the cell to the counter node 10A, and the fault detection node and the counter node switch the faulty connection to the standby system connection at the timings of transmission and reception of the connection switching request cell.

2. 发明专利

JPH0730555A CELL ABORT DEVICE 失效
公开(公告)号：JPH0730555A
公开(公告)日：1995-01-31
申请号：JP17339893
申请日：1993-07-13
申请人： NEC CORP , NIPPON TELEGRAPH & TELEPHONE , HITACHI LTD , FUJITSU LTD , OKI ELECTRIC IND CO LTD
发明人： HONDA MASAHIKO , SUZUKI KOJI , SHIOMOTO KOHEI , SUGANO TAKAYUKI , SUZUKI KAZUYUKI , KIMURA NAOHIRO , ARAI KAZUHIRO
IPC分类号： H04Q3/00 , H04L12/24 , H04L12/26 , H04L12/28 , H04Q11/04
摘要： PURPOSE:To recognize the kind of a cell fault and the frequency of occurrence of the fault in details by checking abort causes of a call in an abort cell storage memory and totalizing the check results. CONSTITUTION:The write from a fault cell detection line 13 to an abort cell storage memory 2 is attained only to an area not in use in the abort cell storage memory 2 or an area whose read is already finished by the software. Then a processor 4 reads a count of a reduction cell counter 3 through an interface signal line 42. Furthermore, the processor 4 clears the count of the reduction cell counter 3 through the interface signal line 42, and an overflowed count is prevented by clearing the count at a proper period. The exchange software obtains the count of the counter 3 and the cell control information stored in the memory 2 as information as to the abort of the fault cell. Thus, the kind and the frequency of occurrence of a fault is recognized in details as to the cell.

3. 发明专利

JPH10233781A ATM CHANNEL INTERFACE 失效
公开(公告)号：JPH10233781A
公开(公告)日：1998-09-02
申请号：JP3579097
申请日：1997-02-20
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , NEC CORP , FUJITSU LTD , OKI ELECTRIC IND CO LTD
发明人： KOBASHI ICHIRO , MIYAGI MORIHITO , NAGATO YUJI , TAKAGI KOJI , MORIZAKI SHIGEKI , TADOKORO NAOAKI , SETO HAJIME , SUZUKI KAZUYUKI , KOIKE TAKESHI
IPC分类号： H04Q3/00 , H04L12/26 , H04L12/28
摘要： PROBLEM TO BE SOLVED: To realize diagnosis of normality of duplicated speech channels by a simple configuration without giving effect on a speech channel of an active system in the case that one end of the interface connects to a channel and the other end is connected to an ATM switch. SOLUTION: The ATM channel interface 2 having two systems, active system (r) and standby system (w) is divided into a plurality of function blocks 3, 4, and one function block is provided with a test function section 41 that generates/ inserts a test cell and extracts/checks the test cell reflected from an external circuit and with a multiplex selector 42 that selects both the test cell and a speech channel signal cell of the active system (r) and passes them. A function aborting the test cell is provided for the function block of the active system connecting to an active system channel 9r.

4. 发明专利

JPH09247164A ATM EXCHANGE 失效
公开(公告)号：JPH09247164A
公开(公告)日：1997-09-19
申请号：JP5024196
申请日：1996-03-07
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NEC CORP , HITACHI LTD
发明人： SUZUKI KAZUYUKI , TAKAGI KOJI , DOI YUKIHIRO , MORISHITA YUKIO , MORIZAKI SHIGEKI , SUGANO TAKAYUKI
IPC分类号： H04M3/26 , H04L12/28 , H04L12/70 , H04Q3/00
摘要： PROBLEM TO BE SOLVED: To extend the range of route for a continuity test and a function test or the like through the same test route and to easily locate a fault by providing a test function section to each of a line adaptor section connecting to an ATM switch section. SOLUTION: Each of test function sections TCC1-TCC4 is provided to each of line adaptor sections LU1-LU4 connecting to an ATM switch section SW. Each test function section TCC is provided with a test cell extract section and a test cell insert section with respect to a main signal, the extract section connects to a test cell check section and a test cell generating section is connected to the insert section. In test routes 2, 3, cells generated by the cell generating section in the function sections TCC1, 2 of the adaptor sections LU1, 2 are inserted to the main signal by the cell insert section and the resulting cell is sent and the extract section in the function sections TCC2, TVV1 of the other adaptor sections extracts the cell and a cell check section checks the continuity of the test cell. Thus, the cell is tested through the same test route as the user cell.

5. 发明专利

JP2000031971A LINE ADAPTOR 失效
公开(公告)号：JP2000031971A
公开(公告)日：2000-01-28
申请号：JP19289998
申请日：1998-07-08
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD
发明人： AMANO MITSUHARU , TOMONAGA HIROSHI , SUZUKI KAZUYUKI , MATSUO SATOSHI , OMOTANI MASAAKI , GENDA KOICHI , DOI YUKIHIRO , WATABE KAZUO , TSUCHIDA TOMOHIRO
IPC分类号： H04L1/22 , H04L12/28 , H04L12/70 , H04L12/713 , H04L12/775 , H04L12/935 , H04Q3/00
摘要： PROBLEM TO BE SOLVED: To prevent missing, duplication of cells and inversion of cell sequence in a switching state of a duplicate system in the case that the line adaptor provided to an ATM exchange, and composed of active/standby systems adds system identification information to a cell received by each system, writes the cell to a storage means, and reads the cell therefrom and outputs it. SOLUTION: The line adaptor 100 is provided with a read end detection means 110 that monitors cells arriving before switching which have been stored in storage means 102 of both the systems and detects that all the cells having arrived before switching are read when receiving an instruction externally to switch an operating state of both systems. An each-system identifier addition means 101 revises system identification information to be added to each cell, with a read stop means 120 that stops reading of cells stored in the storage means when the means 110 detects that all the cells having arrived before switching are read, and a read restart means 130 that restores reading of cells stored in each storage means when the means 120 stops reading of the cells stored in the storage means 102 of both the systems.

6. 发明专利

JP2000115273A DATA TRANSFER EQUIPMENT 失效
公开(公告)号：JP2000115273A
公开(公告)日：2000-04-21
申请号：JP27811198
申请日：1998-09-30
申请人： NEC CORP , NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD , OKI ELECTRIC IND CO LTD
发明人： YOKOUCHI HIDEAKI , MINAMIMURA KEIZO , GENDA KOICHI , OMOTANI MASAAKI , SUZUKI KAZUYUKI , MATSUO SATOSHI , UCHINO KENICHI
IPC分类号： G06F13/38 , G06F1/12 , H04L25/02 , H04L25/40 , H04L29/02
摘要： PROBLEM TO BE SOLVED: To reduce the number of terminals of an LSI or a printed board by making a clock signal and a synchronous signal of a control information signal common with a clock signal and a synchronous signal of a user information signal. SOLUTION: This data transfer equipment is provided with a cell data transmission processing part 20 on a master side to transmit and receive a user information signal, a cell data reception processing part 23 at the master side, a control bus transmission control part 22 on the master side to transmit and receive the control information signal and a control bus reception control part 28 at the master side. And the clock signal and the synchronizing signal of the control information signal are made common with the clock signal and the synchronizing signal of the user information signal. Namely, a cell transmission clock signal and a cell synchronizing signal are used as a clock signal for transmission of the control signal and a synchronizing signal for the control signal when the control bus signal is transmitted by the control bus transmission control part 22 on the master side. Therefore, the cell transmission clock signal and the cell synchronizing signal are supplied to the control bus transmission control part 22 at the master side as the control bus synchronizing signal 21 by the cell data transmission processing part 20 on the master side.

7. 发明专利

JP2001345824A TAG-CONVERTING DEVICE 失效
公开(公告)号：JP2001345824A
公开(公告)日：2001-12-14
申请号：JP2000168367
申请日：2000-06-06
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： SUZUKI KAZUYUKI , MATSUO SATOSHI , OMOTANI MASAAKI , SENMARU TAKESHI
IPC分类号： H04L12/28
摘要： PROBLEM TO BE SOLVED: To provide a tag converting device, with which the loss of cells does not occur, when switching from an active system to a reserve system. SOLUTION: A first packet synthesizing means 1 and a second packet synthesizing means 2 generate first and second packets by synthesizing inputted cells. When switching of the active system and the reserve system is requested, a selection information generating means 3 generates selection information showing which of first and second packets is to be selected. A first packet disassembling means 4 and a second packet disassembling means 5 generate the first and second cells by disassembling the first and second packets. A first cell storage means 6 and a second cell storage means 7 store the first and second cells separately for each class of these cells. A first cell read means 8 and a second cell read means 9 successively read out the first and second cells stored in the first and second cell storage means for each class, and when the selection information is generated by the selection information generating means 3, the timing for reading out the cells is controlled according to the control of a timing control means 10.

8. 发明专利

JPH09162891A ATM EXCHANGE 失效
公开(公告)号：JPH09162891A
公开(公告)日：1997-06-20
申请号：JP32424995
申请日：1995-12-13
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： SUZUKI KAZUYUKI , TAKAGI KOJI , YAMANAKA NAOAKI
IPC分类号： H04Q3/00 , H04L12/26 , H04L12/28 , H04L12/70
摘要： PROBLEM TO BE SOLVED: To self-diagnose the function of a test function by connecting a test cell generation part and a test cell inspection part with a return means and giving a test cell generated in the test cell generation part to the test cell inspection part. SOLUTION: At the time of self-diagnose, selectors SEL1-4 are switched so that a route B is selected with the control signal of MPU. In a transmission part 4, the test cell generated in the test cell generation part GEN is transmitted not to a test cell insertion part INS but to a return buffer 6. The test cell is given to the test cell inspection part CHK via the return buffer 6 and the selector SEL1 of a reception part 1, and the test cell is inspected. The relation of a transmission part 2 and a reception part 3 is the same. The test cell generated in the test cell generation part GEN is transmission from the selector SEL2 to a return buffer 7. The test cell is given from the return buffer 7 to the test cell inspection part CHK via the selector SEL3 of the reception part 3.

9. 发明专利

JP2004158903A Packet processing apparatus 有权
公开(公告)号：JP2004158903A
公开(公告)日：2004-06-03
申请号：JP2002319917
申请日：2002-11-01
申请人： Fujitsu Ltd , 富士通株式会社
发明人： SUZUKI KAZUYUKI , URYU SHIRO
IPC分类号： H04L12/70 , H04L12/44 , H04L12/56
CPC分类号： H04L49/602 , H04L45/7453 , H04L49/3009 , H04L49/3027
摘要： PROBLEM TO BE SOLVED: To provide a packet processing apparatus for enhancing entire the relay processing performance by using a plurality of packet analysis modules to process the received packets distributedly. SOLUTION: The packet processing apparatus includes: a distribution means for attaching a serial number to the received packet and distributing the resulting packets; a plurality of packet analysis means 22 1 to 22a for executing information analysis processing of the packets distributed from the distribution means in parallel; and a sequence correction means 24 receiving the packets from a plurality of the packet analysis means, sorting the packets in the orders of the serial numbers attached to the packets, and providing an output. Thus, a plurality of the packet analysis means process the received packets distributedly to enhance the entire relay processing performance. COPYRIGHT: (C)2004,JPO

10. 发明专利

JP2004080334A Packet transfer circuit in ip over atm 审中-公开
标题翻译： ATM中的IP分组传输电路
公开(公告)号：JP2004080334A
公开(公告)日：2004-03-11
申请号：JP2002237347
申请日：2002-08-16
申请人： Fujitsu Ltd , Nippon Telegr & Teleph Corp , 富士通株式会社 , 日本電信電話株式会社
发明人： KOTANI KUNIHIRO , SUZUKI KAZUYUKI , OMOTANI MASAAKI , UGA MASANORI , SHIOMOTO KOHEI
IPC分类号： H04L12/951 , H04L12/66 , H04L13/08 , H04L12/56
摘要： PROBLEM TO BE SOLVED: To obtain a packet transfer circuit in IP over ATM exhibiting a maximum packet transfer capacity by performing read, write and refresh within a predetermined period using an SDRAM. SOLUTION: A packet processing section comprises a buffer memory consisting of a plurality (n) of SDRAMs accessible in parallel, a serial/parallel converter receiving input packets in series and delivering them in parallel, and a parallel/serial converter for storing a plurality of parallel signals read out from the buffer memory and generating an output packet. Three operations, i.e. an operation for storing packets in the serial/parallel converter and writing them simultaneously in parallel into respective SDRAMs, an operation for storing signals read out from the SDRAMs in the parallel/serial converter, and a refresh operation, are performed within the refresh period. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：通过使用SDRAM在预定时段内执行读，写和刷新，以获得具有最大分组传送容量的ATM中的IP中的分组传送电路。解决方案：分组处理部分包括由可并行访问的多个（n个）SDRAM组成的缓冲存储器，串行/并行传输输入数据包的串行/并行转换器，以及并行传送它们的并行/串行转换器从缓冲存储器读出的多个并行信号并产生输出分组。三个操作，即将串行/并行转换器中的数据包存储在各个SDRAM中并行并行写入的操作，用于存储从并行/串行转换器中的SDRAM读出的信号的操作和刷新操作，刷新周期。版权所有（C）2004，JPO

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式