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1. 发明专利

JPS57124950A Duplicated bus connecting system 失效
标题翻译：复用总线连接系统
公开(公告)号：JPS57124950A
公开(公告)日：1982-08-04
申请号：JP1045381
申请日：1981-01-27
申请人： Fujitsu Ltd , Hitachi Ltd , Nec Corp , Nippon Telegr & Teleph Corp , Oki Electric Ind Co Ltd
发明人： KAWANOBE TADASHI , EBIHARA MAKOTO , INUI YOSHIO , AMANO YUTAKA , TAKAHASHI RIYOUICHI
IPC分类号： H04L1/22 , G06F11/18 , G06F13/00 , G06F13/40 , H04L12/40
CPC分类号： H04L12/40 , G06F13/4022
摘要： PURPOSE:To prevent system down caused by the failure of a bus transmission line, providing a duplicated bus transmission line. CONSTITUTION:An access device 11 selects either one of gate 101 and 102 through the instruction of a bus route control circuit 301 and transmits the transmission data to a bus transmission line 31 or 32 via an interface section 51 or 52. On the other hand, an access device 21 to be accessed receives the data on the bus transmission line 31 or 32 via an interface section 71 or 72 according to the instruction of a bus route control circuit 401, selects it with a gate 201 or 202, and fetches it in the device as a reception data. Thus, since there are two routes to connect an arbitrary access device and the access device to be accessed, the dererioration in the economy of device due to increase in the interface is prevented and the lowering in the system reliability can be avoided.
摘要翻译：目的：为了防止总线传输线路故障导致的系统故障，提供复制的总线传输线。构成：接入装置11通过总线路径控制电路301的指示选择门101,102中的任一个，经由接口部51或52将发送数据发送到总线传输线31或32。另一方面，要访问的访问装置21根据总线路径控制电路401的指令经由接口部分71或72在总线传输线31或32上接收数据，用门201或202选择它，并将其取出该设备作为接收数据。因此，由于存在连接任意访问装置和要访问的访问装置的两条路由，所以防止了由于界面增加引起的设备经济性的下降，并且可以避免系统可靠性的降低。

2. 发明专利

JPS5247339A SIGNAL BUS BAR TRANSMISSION SYSTEM 失效
公开(公告)号：JPS5247339A
公开(公告)日：1977-04-15
申请号：JP12338075
申请日：1975-10-13
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , HITACHI LTD , FUJITSU LTD
发明人： TAJIMA KIYOHIDE , IRITA YUKIO , FUJII SHIGERU , AMANO YUTAKA , IZAWA EIICHI
IPC分类号： G06F3/00 , G06F13/00
摘要： PURPOSE:The air-to-ground balance signal is transmitted to between-frame transmission section of signal bus bar, and air-to-ground unbalance signal is transmitted to inside transmission section. In such a way, the transmission of high dependability is ensured.

3. 发明专利

JPS5245858A CONTROL SYSTEM OF DOUBLE STABILIZED CIRCUIT 失效
公开(公告)号：JPS5245858A
公开(公告)日：1977-04-11
申请号：JP12137775
申请日：1975-10-09
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： TSUJIMURA ATSUHIKO , ISHIKAWA TSUTOMU , HATAKEYAMA SHIGEMITSU , AMANO YUTAKA , TEJIMA TOORU
IPC分类号： H03K3/02 , H03K3/037 , H03K3/286 , H03K23/40
摘要： PURPOSE:Using one control signal, information input signal can be directly stored without any logic time lag. At the same time, input signal can be correctly stored even though in much noise, and further a free clearing is possible.

4. 发明专利

JPS57127991A REFRESH CONTROLLING SYSTEM 失效
公开(公告)号：JPS57127991A
公开(公告)日：1982-08-09
申请号：JP1045481
申请日：1981-01-27
申请人： NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： KAWANOBE TADASHI , MIWA RIYOUJI , EBIHARA MAKOTO , SAKURAI YOSHIO , AMANO YUTAKA , INOUE SABUROU
IPC分类号： G11C11/401 , G11C11/406 , G11C29/00
摘要： PURPOSE:To prevent all information stored in a storage device from being destroyed with a failure of a single section, by starting refresh operation at the same time from a plurality of refresh operation starting devices. CONSTITUTION:To a storage device 31 requiring refresh operation each specified period, refresh operation is instructed from a plurality of refresh starters 11, 12 at the same time. A storage device 31 receiving the instruction of this operation checks if a respective refresh start signal receivaing the said plurality of refresh operation starters 11, 12 satisfies the specified period or not. Through the logical sum of a start signal in which the result of check is normal, the refresh operation in the storage device 31 is started. For example, a refresh operation start signal reception control section 51 consisting of refresh operation start signal monitor circuits 81, 82, logical product gates 91, 92 and logical sum gate 93, is provided for the said control.

5. 发明专利

JPS57109195A MEMORY FAILURE PROCESSING SYSTEM 失效
公开(公告)号：JPS57109195A
公开(公告)日：1982-07-07
申请号：JP18559780
申请日：1980-12-26
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , HITACHI LTD , FUJITSU LTD
发明人： SAKURAI YOSHIO , KAWAKAMI MASAHARU , NIHEI TOSHIHIKO , AMANO YUTAKA , TAKAHASHI RIYOUICHI
IPC分类号： G06F12/16 , G06F11/16 , G11C29/00
摘要： PURPOSE:To reduce the intermittent failure processing time and to enable data processing with high reliability, by copying one read-in information of duplicated main storage devices to the main storage device at failure generation, at the generation of failure. CONSTITUTION:For the operation of douplicated main storage devices 2a, 2b synchronizingly, a control device 1 transmits access request signals 4a, 4b to the devices 2a, 2b at the same time and instructs the reception of information on a memory bus 3. The devices 2a, 2b start the operation according to the content of control designation included in the bus 3, and in case of write-in, both systems make write-in operation at the same time and guarantee the identity of the stored content. In case of readout, the both make read-in operation at the same time, and the response to the controller 1 is made by the existing system main storage device only when route selection signals 5a, 5b are on-state, and in case of normal read-in operation, the main storage device of a spare system is not responded to the controller 1.

6. 发明专利

JPS5563451A MEMORY CONTROL SYSTEM 失效
公开(公告)号：JPS5563451A
公开(公告)日：1980-05-13
申请号：JP13583078
申请日：1978-11-06
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： AMANO YUTAKA , KOIKE HIDEYUKI , MATSUMOTO AKIRA , SATOU HITOSHI , URUSHIBARA TETSUO
IPC分类号： G06F12/00 , G06F13/00
摘要： PURPOSE:To start the read-in and write-in, by providing simple logical product and sum circuits when the address flag signal is received and the data flag signal is received respectively. CONSTITUTION:In case of read-in, the unit designation signal 1, read-in designation signal 4, address information 10, and address flag signal 3 are delivered, the timing circuit 11 is started. The circuit 11 produces the row designation timing signal 13 and the column designation signal 12, and the memory element 17 outputs the read-in data 16. In case of write-in, the signal 1, write-in designation signal 6, and infomation 10 are delivered, and the circuit 11 is started when the data flag signal 5 is delivered, and the element 17 stores the write-in data. Since the data flag signal can be started as timing, no timing circuit is required.

7. 发明专利

JPS5264836A DATA SENDDOUT SYSTEM 失效
公开(公告)号：JPS5264836A
公开(公告)日：1977-05-28
申请号：JP14080575
申请日：1975-11-26
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： AMANO YUTAKA , OONISHI NOBORU , KAWASHIMA YOUICHI , SUZUKI TOSHIJI , IZAWA EIICHI
IPC分类号： G11C7/00 , G06F13/00 , G11C11/34
摘要： PURPOSE:The logical product between output of semiconductor memory element and output of timin generator circuit is given waveform shaping in order that the product may fit to transmission pulse conditions, hen, to be output from memory system. As a result, data sending of reduced signal propagation delay time becomes possible.

8. 发明专利

JPS5264829A NOISE SUPPRESSION SYSTEM 失效
公开(公告)号：JPS5264829A
公开(公告)日：1977-05-28
申请号：JP14080675
申请日：1975-11-26
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： AMANO YUTAKA , ISHIKAWA TSUTOMU , KAWASHIMA YOUICHI , ISAZAKI KIYONOBU , TAGA KAZUYUKI
IPC分类号： H04B1/10 , G06F1/00 , G06F1/18 , G06F1/26
摘要： PURPOSE:The circuit which detects power source output is installed within memory to perform output control of detection circuit based on the power source output preference order at power source throw-in and cutoff tine. Then, the input of open collector IC is grounded. As a result, the noise is prevented from being sent out onto bus.

9. 发明专利

JPS5247338A SIGNAL BUS BAR CONNECTION SYSTEM 失效
公开(公告)号：JPS5247338A
公开(公告)日：1977-04-15
申请号：JP12337975
申请日：1975-10-13
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , HITACHI LTD , FUJITSU LTD
发明人： TAJIMA KIYOHIDE , OONISHI NOBORU , TSUJIMURA ATSUHIKO , AMANO YUTAKA , TOYAMA TSUGIO
IPC分类号： G06F12/06 , G06F3/00 , G06F13/00
摘要： PURPOSE:In order to secure betterment of transmission quality, the signal bus bar connection unit, which is corresponding to centrol unit and is shared with plural memories, is installed within memory frame.

10. 发明专利

JPS5559525A ORDER CONTROL SYSTEM 失效
公开(公告)号：JPS5559525A
公开(公告)日：1980-05-06
申请号：JP13260078
申请日：1978-10-30
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： YASUDA KENICHI , MORIKAWA YUUICHI , YAZAWA KATSUHIKO , AMANO YUTAKA , YASUI YUTAKA
IPC分类号： G06F13/10 , G06F3/00 , G06F9/06
摘要： PURPOSE:To reduce the execution time of the input/output order by securing the reading of the order word at the I/O unit during the order word reading cycle. CONSTITUTION:Central controller CC transmits the address onto data bus DTB and at the same time transmits continuously order latch signal IFETCH onto inductive line IFE during the cycle of the address sending cycle (input/output order reading cycle TR). At the same time, address flag ADRFLG is sent onto lead wire ADF and accordingly memory device MM transmits the input/output order word to DTB in response to ADRFLG, and at the same time transmits data flag DTFLG onto lead wire DTF. Thus the CC completes TR. In this latch cycle the I/O reads out the order word tranmitted from the MM through the logic circuit of IFETCH and DTFLG, and the operation code can be received through the I/O. In other words, the operation code sending cycle, which is so far carried out in the 2nd cycle of the conventional method, can be omitted, thus reducing the execution time for the input/output order.

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