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1. 发明专利

JPS5264836A DATA SENDDOUT SYSTEM 失效
公开(公告)号：JPS5264836A
公开(公告)日：1977-05-28
申请号：JP14080575
申请日：1975-11-26
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： AMANO YUTAKA , OONISHI NOBORU , KAWASHIMA YOUICHI , SUZUKI TOSHIJI , IZAWA EIICHI
IPC分类号： G11C7/00 , G06F13/00 , G11C11/34
摘要： PURPOSE:The logical product between output of semiconductor memory element and output of timin generator circuit is given waveform shaping in order that the product may fit to transmission pulse conditions, hen, to be output from memory system. As a result, data sending of reduced signal propagation delay time becomes possible.

3. 发明专利

JPS5222425A METHOD OF INSTALLING CARDS FOR LOADING CIRCUITS 失效
公开(公告)号：JPS5222425A
公开(公告)日：1977-02-19
申请号：JP9829875
申请日：1975-08-13
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD
发明人： IZAWA EIICHI , KAWANOBE TADASHI , OOBA SADAO , ABE MASAAKI , ARAI YUUJI
IPC分类号： G06F1/18 , G06F1/00
摘要： PURPOSE:To reduce the number of backboard and the lengths of signal line and to improve the transmission characteristic by arranging the shelf for interface and the shelf for circuits at both sides of backboards.

4. 发明专利

JPS5222426A METHOD OF INSTALLING INTERFACE CIRCUIT SECTION 失效
公开(公告)号：JPS5222426A
公开(公告)日：1977-02-19
申请号：JP9829975
申请日：1975-08-13
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD
发明人： IZAWA EIICHI , AIBA KEIJI , KAWANOBE TADASHI , OOBA SADAO , SATOU HITOSHI , HAYASHI SHIGEO
IPC分类号： G06F1/18 , G06F1/00
摘要： PURPOSE:To reduce the pattern length and to prevent delays of sinals by installing a case on which connectors are provided all round and in which interface circuits and interface card groups with through patterns on one side of the frame.

5. 发明专利

JPS5247339A SIGNAL BUS BAR TRANSMISSION SYSTEM 失效
公开(公告)号：JPS5247339A
公开(公告)日：1977-04-15
申请号：JP12338075
申请日：1975-10-13
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , HITACHI LTD , FUJITSU LTD
发明人： TAJIMA KIYOHIDE , IRITA YUKIO , FUJII SHIGERU , AMANO YUTAKA , IZAWA EIICHI
IPC分类号： G06F3/00 , G06F13/00
摘要： PURPOSE:The air-to-ground balance signal is transmitted to between-frame transmission section of signal bus bar, and air-to-ground unbalance signal is transmitted to inside transmission section. In such a way, the transmission of high dependability is ensured.

6. 发明专利

JPS5222443A METHOD OF CHECKING REFRESH OPERATION 失效
公开(公告)号：JPS5222443A
公开(公告)日：1977-02-19
申请号：JP9872675
申请日：1975-08-13
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , HITACHI LTD , FUJITSU LTD
发明人： SATOU HITOSHI , WAKABAYASHI YOSHIO , TSUJIMURA ATSUHIKO , ARAI YUUJI , IZAWA EIICHI
IPC分类号： G06F12/16 , G11C11/401 , G11C11/406 , G11C29/00
摘要： PURPOSE:To immediately process any trouble detected by the checking of the normalcy of the refresh operation by monitoring the output of a chip enable signal to be supplied to the memory element.

7. 发明专利

JPS5222439A METHOD OF GENERATING TIMING OF MEMORY 失效
公开(公告)号：JPS5222439A
公开(公告)日：1977-02-19
申请号：JP9871975
申请日：1975-08-13
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , HITACHI LTD , FUJITSU LTD
发明人： NAKANO YOSHIO , FUKUDA HARUYUKI , OOBA SADAO , SUEMORI NOBORU , IZAWA EIICHI
IPC分类号： G06F12/06 , G06F1/04 , G06F1/06 , G06F13/00 , G11C7/00 , G11C11/34
摘要： PURPOSE:To make high speed processing operations possible by starting the memory with OR of tow timing chain operated alternately with a memory which performs overlap operations.

9. 发明专利

JPS57176454A MICROPROGRAM PROCESSING SYSTEM 失效
公开(公告)号：JPS57176454A
公开(公告)日：1982-10-29
申请号：JP6212581
申请日：1981-04-24
申请人： FUJITSU LTD
发明人： IZAWA EIICHI , OSADA TAKATOSHI
IPC分类号： G06F9/22 , G06F11/20
摘要： PURPOSE:To prevent function stop of a central processing unit, by duplicating a control memory and its peripheral circuit completely and operating another system if a failure takes place in a system in operation immediately through the provision of a failure detection circuit. CONSTITUTION:A control memory CM, an address generating circuit AD, a microinstruction register MIR, and error detection circuits CKA and CKD are completely duplicated. A control circuit CTL drives either register MIR0 and MIR1 microinstruction selected with switching circuit SW. Taking that the system 0 is in operation and the microinstruction of the MIR0 is transmitted to the control circuit CTL. When a switching control circuit SWC receives the information that the detection circuits CKA0 and CKD0 detect errors in microinstruction outputted from the CM0 or the address inputted to the CM0, the SWC drives the switching circuit SW and if required, required data is set to the address generating circuit AD1 and starts the operation of the system 1.

10. 发明专利

JPS5532228A MEMORY UNIT 失效
公开(公告)号：JPS5532228A
公开(公告)日：1980-03-06
申请号：JP10361278
申请日：1978-08-25
申请人： FUJITSU LTD
发明人： IZAWA EIICHI , IGI YOUZOU
IPC分类号： G06F12/06 , G11C8/12
摘要： PURPOSE:To prevent address regions in memory card mounting from overlapping by controlling the unit memory driver circuit of the memory card by providing a unit memory selector circuit. CONSTITUTION:Driver circuit control signal output terminals G, H and J for memory cards 21-1 to 21-4 of the same constitution are grounded with cards mounted when one of input driver circuit control output terminals A to F of driver circuit control gates 17-1 to 17-4 forming the unit memory selector circuit is at the earth level, memory driver circuits 16-1 to 16-4 generate no driving signal, so that unit memories 13-1 to 13-4 of respective cards 21-1 to 21-4 will never be addressed. In this constitution, cards 21-1 to 21-4 are mounted at positions A1 to A4 of prescribed initial addresses of the mount frame and fixed connections are made between terminals of cards 21-1 to 21-4, e.g. G and A, H and D, and J and F of cards 21-1 and 21-2, so that since no driving signal is generated by corresponding circuits 16-1 to 16-4, address regions M0 to M6 will be prevented from overlapping.

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