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1. 发明专利

JPS5794973A CONTROL SYSTEM FOR BUFFER MEMORY 失效
公开(公告)号：JPS5794973A
公开(公告)日：1982-06-12
申请号：JP17124680
申请日：1980-12-04
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： HATSUTORI AKIRA , TAKAHASHI MASANORI , HIGASHIDA MASANOBU , TAJIRI KAZUO
IPC分类号： G06F13/12 , G06F12/08 , G06F12/12
摘要： PURPOSE:To prevent the processing speed of a CPU from decreasing by preventing a change in the replacement priority level of a block which contains a readout request address from a channel device when the block is stored in a buffer memory. CONSTITUTION:When an access readout request from a channel 4 to a buffer memory 2 is detected at a memory port 28 for channels, an update logical circuit 5 is inhibited through a signal line 29 from operating. Therefore, if an access request block from the channel is in a buffer, the expelling priority level of the block is not changed. When it is not in the buffer, the block is substituted for the oldest block, but since the update logic circuit 5 is not in operation at this time, the channel uses only the way position where the oldest block was resident, so that a CPU is not interrupted.

2. 发明专利

JPS60229153A CONSTITUTION CONTROL SYSTEM OF COMPUTER SYSTEM 失效
公开(公告)号：JPS60229153A
公开(公告)日：1985-11-14
申请号：JP8438784
申请日：1984-04-26
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： TAJIRI KAZUO , INOUE MASANOBU , SUMIMOTO TSUTOMU , IKEDA HITOSHI
IPC分类号： G06F12/16 , G06F12/06
摘要： PURPOSE:To prevent program control from complexity due to the difference in memory constitution by dividing plural memory devices into plural sets and previously preparing plural modes for the combination of address numbers to be assigned to respective constitutional units. CONSTITUTION:Four constitutional units consisting of machine numbers 0-3 are prepared in a memory device MEM5 and four constitutional units consisting of machine numbers 8-11 are prepared in a memory device MEM6. If a single computer system is to be constituted by all devices shown in a Fig., a service processor SVP9 connects memory devices MCUs 7, 8, CPUs 1, 2, data transfer devices DCHs 3, 4, and the MEMs 5, 6 respectively to initialize the system. To obtain a continuous real address space, address numbers 0-7 are assigned to eight machine Nos. in the MEMs 5, 6. Therefore, the SVP9 selects one mode out of four address number assigning modes to assign the address number. If independent processing is started due to a trouble or the like, it is necessary to stop the use of respective devices, but the specification of an address number may be stopped in the MEM6.

3. 发明专利

JPS6230655B2 失效
公开(公告)号：JPS6230655B2
公开(公告)日：1987-07-03
申请号：JP19204682
申请日：1982-11-01
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： TAJIRI KAZUO
IPC分类号： G06F9/34 , G06F9/355 , G06F12/02 , G06F12/10

4. 发明专利

JPS6024493B2 失效
公开(公告)号：JPS6024493B2
公开(公告)日：1985-06-13
申请号：JP8396880
申请日：1980-06-23
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： TAJIRI KAZUO , SHIOKAWA SHIZUO , FUKUMURA YOSHIMI
IPC分类号： G06F11/10 , G06F11/00 , G06F12/16

5. 发明专利

JPS5712495A MEMORY CONTROL SYSTEM 失效
公开(公告)号：JPS5712495A
公开(公告)日：1982-01-22
申请号：JP8396880
申请日：1980-06-23
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： TAJIRI KAZUO , SHIOKAWA SHIZUO , FUKUMURA YOSHIMI
IPC分类号： G06F11/10 , G06F11/00 , G06F12/16
摘要： PURPOSE:To strengthen the protection for breakdown of information on a main storage, by checking whether plural storage divices having the same real address have some error or not or securing a normal continuation of process if a correctable erroneous information exists. CONSTITUTION:In case a correction of error is impossible in a mechanism (ECC mechanism) 31 that detects or correct an error and no error is detected or an error can be corrected in an ECC mechanism 30, a selector 34 selcts a new information obtained from the mechanism 30 to send it to a CPU or a channel. At the same time, this information is sent to a memory unit having a correction unable information via a selector 33 to perform a writing action. In such way, the correct information can be sent to the access originator when no error is detected in either one of the mechanisms 30 and 31 or an error correction is possible, and at the same time the information with which an error correction is impossible with use of an error correction code can be restored in a correct way.

6. 发明专利

JPH03269629A KNOWLEDGE REFLINEMENT PROCESSING SYSTEM USING EXAMPLE 失效
公开(公告)号：JPH03269629A
公开(公告)日：1991-12-02
申请号：JP6944190
申请日：1990-03-19
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： UCHIHASHI TOMOTAKA , TAJIRI KAZUO , KIYAMA YOSHIHIRO , ANZAI TAKASHI
IPC分类号： G06F9/44 , G06N5/04
摘要： PURPOSE:To improve the knowledge refining efficiency by tracing a decision tree and a sorting tree for inspection of the conclusion drawn with combination of conditional values and updating the knowledge after designing the undesigned conditional value or adding the conditions. CONSTITUTION:When a user 8 inputs a question to a knowledge base system 1, an inference mechanism 5 performs the inference processing based on a generated decision tree 12 and draws a conclusion. An example arrangement part 13 generates a sorting tree 19 from the examples stored in an example base 6. A knowledge refining mechanism 4 performs comparison between both trees 12 and 19, i.e., the knowledges stored in a knowledge base 3 and detects four patterns. For instance, the tree 19 contains the combination of the conditional values included in the tree 12 and at the same time the conclusion drawn by the relevant combination detects a pattern included in the tree 12. Thus a conclusion adding part 15 shows the corresponding combination of conditional values stored in the tree 19 to the user 8 to instruct the user 8 to input the information on the definition of conclusion for addition of conditions to a conclusion definition knowledge 11 and the tree 12. As a result, the knowledges are freeely extracted out of the examples.

7. 发明专利

JPS62194755A SKEW COMPENSATION SYSTEM 失效
公开(公告)号：JPS62194755A
公开(公告)日：1987-08-27
申请号：JP3668286
申请日：1986-02-21
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： TAJIRI KAZUO
IPC分类号： H04L7/00
摘要： PURPOSE:To improve a transmission speed by connecting the same number of FIFO memories as that of signal lines to the reception side so as to compensate the skew. CONSTITUTION:A data identified and recovered from 8 signal lines is supplied to terminals D11-81 of FIFO memories 10-80 corresponding to each signal line and written in the 1st clock extracted from each signal line and given to terminals W12-82. When all FIFO memories are written, an AND gate 2 is opened and the 2nd clock from a clock generator 1 is supplied to terminals R14-84 through an AND gate 3 and data of the 8 FIFO memories is read simultaneously onto output lines 13-83 at the same time and fed to the processing unit 4. Even when the write timing to each FIFO memory depends on the skew, it is compensated at read. The period of the read clock is not required to be 2 times or over the skew time as a conventional device.

8. 发明专利

JPS586572A DEBUG INTERRUPTING SYSTEM 失效
公开(公告)号：JPS586572A
公开(公告)日：1983-01-14
申请号：JP10537081
申请日：1981-07-06
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： TAJIRI KAZUO , NISHIZAWA MAMORU
IPC分类号： G06F9/48 , G06F9/46 , G06F11/28 , G06F12/08 , G06F12/10 , G06F13/00
摘要： PURPOSE:To limitlessly attain the setting of interrupting point and to decrease the hardware, by making arbitrarily a flag memory correspond to a page where a debugged program is assigned. CONSTITUTION:In the accessing from an information processor, a display bit 6 for debug corresponding to a virtual page of an address conversion buffer 5 is set and the address of the virtual page is registrated in a debug page address register 7 or 8, and when the flag bit of information unit accessed with a flag memory 9 or 10 corresponding to the register 7 or 8 is set, a debug interruption signal 25 is generated. If the address of the virtual pag is not registrated in the registers 7 and 8 regardless that the debug display bit 6 is set, a program interruption signal 30 is generated. Thus, the virtual page being the objective of debug is designated with the bit 6 and the register 7 or 8 and the setting of an arbitrary interrupting point can be made in a page designated with the memories 9 and 10.

9. 发明专利

JPS5982686A SEGMENT CONNECTING SYSTEM 失效
公开(公告)号：JPS5982686A
公开(公告)日：1984-05-12
申请号：JP19204582
申请日：1982-11-01
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： TAJIRI KAZUO
IPC分类号： G06F12/10 , G06F9/34 , G06F12/02
摘要： PURPOSE:To offer system for limiting the generation of an effective address EA into a segment or a segment group designated by a program, by providing plural connection designating register for holding a connecting bit and connecting range information. CONSTITUTION:A register BR of a number designated by an instruction word 1 is selected from a BR group 2, and a base address BS is read out to a register 4. The number of connection designating registers (LR) 5 is the same as the number of segments. The LR sets in advance by a program a designated connecting bit E and connecting range information L to a segment having the same number as the register number, and the LR having a segment number to which the base address BS designated by the bit number of the register 4 belongs is selected, and is read out to a digit designating register DR 6. The E bit and L designated to the segment to which the read-out BS belongs are read out to the DR 6. They are prepared in advance in a table having en entry in accordance with a segment for converting a virtual address to a read address, and can be loaded to the LR by an instruction.

10. 发明专利

JPS5981742A ADDRESS EXTENDING SYSTEM 失效
公开(公告)号：JPS5981742A
公开(公告)日：1984-05-11
申请号：JP19204682
申请日：1982-11-01
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： TAJIRI KAZUO
IPC分类号： G06F9/34 , G06F9/355 , G06F12/02 , G06F12/10
摘要： PURPOSE:To extend an address by adding a register to hold the upper bits of an extended index, and controlling the mode of extension by the ON/OFF state of an extended display bit of an extended base register designated by an instruction word. CONSTITUTION:The extended base addresses of base addresses BSH, BSM and BS, the extended indexes of indexes IXH, IXM and IX and a displacement DP of 12 bits are added 10 together regardless of modes and registered 11. Bits 40- 63 of the register 11 are stored as they are in an effective address register EAR of a register 9. While bits 32-39 are stored in the register EAR of the register 9 by a medium bit selecting circuit 12 in the case of E=1 (new mode) with the extended base register. The register EAR is set at 0 with E=0. A selecting circuit 17 selects bits 8-31 with E=1 and E=0 of the register 11. This facilitates an easy extension of address.

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