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1. 发明专利

JP2005080037A Overhead transparent transmission method and device 审中-公开
标题翻译：超透明传输方法和设备
公开(公告)号：JP2005080037A
公开(公告)日：2005-03-24
申请号：JP2003309543
申请日：2003-09-02
申请人： Fujitsu Ltd , 富士通株式会社
发明人： MATSUNAGA KOJI , SHIODA KAZUNARI , TAKADA ISAO , MIYAKE MASATO , SATO MASAKI
IPC分类号： H04J3/00 , H04L12/66 , H04L12/70 , H04L12/56
摘要： PROBLEM TO BE SOLVED: To enable a high-speed transmission between branch line networks by transparently transmitting the information byte of the overhead of the SDH of a branch line used for an operation and a maintenance on a backbone network in the transmission device of a backbone (2.4 Gbps) network connected to a plurality of branch line (150 Mbps) networks. SOLUTION: Backbone SDH transmission devices 1-1 and 1-4 collectively terminate the information byte of an SDH overhead arriving from transmission lines of a backbone network and a branch line network. When the mutual entry of the SDH overhead is performed between the branch line system and the backbone system, the unused byte region (e.g. Z byte or the like) of the SDH overhead of the backbone system is utilized, and the byte of the overhead of the branch line system is mapped into the unused byte region of the SDH overhead of the backbone system to perform a transparent transmission. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：通过透明地传输用于操作的分支线的SDH的开销的信息字节和在发送设备中的骨干网上的维护，来实现分支线路网络之间的高速传输连接到多个分支线路（150Mbps）网络的骨干网（2.4Gbps）网络。解决方案：骨干SDH传输设备1-1和1-4共同终止从骨干网络和分支线路网络的传输线路到达的SDH开销的信息字节。当在分支线路系统和主干系统之间进行SDH开销的相互入口时，主干系统的SDH开销的未使用字节区域（例如Z字节等）被利用，并且开销的字节分支线路系统被映射到骨干系统的SDH开销的未使用字节区域，以执行透明传输。版权所有（C）2005，JPO＆NCIPI

2. 发明专利

JP2009075963A Data creation device and data creation program 有权
标题翻译：数据创建设备和数据创建程序
公开(公告)号：JP2009075963A
公开(公告)日：2009-04-09
申请号：JP2007245890
申请日：2007-09-21
申请人： Fujitsu Ltd , 富士通株式会社
发明人： MOROI KANICHI , TAKADA ISAO
IPC分类号： G06F17/50
摘要： PROBLEM TO BE SOLVED: To provide a data creation device or the like which reliably updates the version number of a circuit.
SOLUTION: The data generation device which generates configuration data to be fetched into a programmable logic device is provided with: a logic generation part which receives function information in which the logical function of the circuit is described and generates logic circuit information showing connection of an element; and a layout wiring part which performs arrangement and wiring according to the logic circuit information to generate the configuration data. The logic generation part is provided with a first version number update part which updates version number information showing the number of version of the logic circuit information every time the logic circuit information is generated. The logic generation part generates the logic circuit information including a version number storage circuit in which the updated version number information is stored so as to be read from the outside of a programmable logic device.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供可靠地更新电路的版本号的数据创建装置等。解决方案：生成要提取到可编程逻辑器件中的配置数据的数据生成装置具有：逻辑生成部，其接收描述了电路的逻辑功能的功能信息，生成表示连接的逻辑电路信息的元素以及布局布线部，其根据逻辑电路信息执行布置和布线以生成配置数据。逻辑生成部具备第一版本号更新部，每当生成逻辑电路信息时，更新表示逻辑电路信息的版本数的版本号信息。逻辑生成部生成逻辑电路信息，该逻辑电路信息包括版本号存储电路，其中存储更新的版本号信息以便从可编程逻辑器件的外部读取。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2004112264A Transmitting apparatus 审中-公开
公开(公告)号：JP2004112264A
公开(公告)日：2004-04-08
申请号：JP2002271217
申请日：2002-09-18
申请人： Fujitsu Ltd , 富士通株式会社
发明人： TAKADA ISAO , MATSUMOTO TAKESHI
IPC分类号： H04J3/00
摘要： PROBLEM TO BE SOLVED: To provide a transmitting apparatus that can speedily process the overhead and can simplify wiring on a backboard.
SOLUTION: The transmitting apparatus comprises a plurality of transmission and reception units for interfacing a synchronous frame composing of the overhead and a payload, a plurality of overhead data termination processing units for processing the overhead, a payload processing unit for processing the payload, and the backboard for connecting the units. The transmission and reception unit includes a separation section for separating the received overhead data of the synchronous frame for each type; and a multiplexing section that accommodates the overhead data outputted from the separation section to an overhead serial data frame for each kind of overhead data, a code for data frame synchronization detection, and an error detection code for outputting to an appropriate signal line for each appropriate kind. The transmission and reception unit directly connects respective transmission and reception units and at least one overhead data termination processing unit by the signal line provided on the backboard.
COPYRIGHT: (C)2004,JPO

4. 发明专利

JP2009271649A Data processor, data processing method, and data processing program 有权
标题翻译：数据处理器，数据处理方法和数据处理程序
公开(公告)号：JP2009271649A
公开(公告)日：2009-11-19
申请号：JP2008120136
申请日：2008-05-02
申请人： Fujitsu Ltd , 富士通株式会社
发明人： HARADA YOSHIHIRO , TAKAO SHINJI , KITAMURA KIYOSHI , TAKADA ISAO
IPC分类号： G06F17/50
CPC分类号： G01R31/31721 , G01R21/01
摘要： PROBLEM TO BE SOLVED: To save any labor and operation costs required for development of a package.
SOLUTION: A data processor stores, for each device which executes respectively assigned data processing, pieces of configuration data defining respective logic circuits that demonstrate different processing performance when they are designed on the pertinent device and reads a piece of the configuration data for each device from among the pieces of the configuration data, and respectively inputs the read pieces of the configuration data to the devices, and designs a logic circuit for each device, and measures total power consumption required in executing the data processing by the devices, and determines, from among the combinations of the designed logic circuits, a combination in which the actually measured value of the measured total power consumption falls within the predetermined target value of the total power consumption, which demonstrates the optimal processing performance as the logic circuits to be designed onto the devices in actually executing the data processing.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：节省开发包装所需的任何劳动和运营成本。解决方案：数据处理器为执行分配的数据处理的每个设备存储定义相应的逻辑电路的配置数据，当它们在相关设备上被设计时，其显示不同的处理性能，并且读取一条配置数据每个设备从配置数据中分别输入配置数据的读取部分到设备，并为每个设备设计一个逻辑电路，并且测量由设备执行数据处理所需的总功耗;以及从所设计的逻辑电路的组合中确定测量的总功耗的实际测量值落在总功耗的预定目标值内的组合，这表明作为逻辑电路的最佳处理性能设计在实际执行数据处理的设备上。版权所有（C）2010，JPO＆INPIT

5. 发明专利

JP2005092303A Digital circuit device with disturbance detection function for clock signal 审中-公开
标题翻译：具有时钟信号干扰检测功能的数字电路设备
公开(公告)号：JP2005092303A
公开(公告)日：2005-04-07
申请号：JP2003321100
申请日：2003-09-12
申请人： Fujitsu Ltd , 富士通株式会社
发明人： TAKADA ISAO , TOYOZUMI TATSUYA , YOSHII YUKIE
IPC分类号： G06F1/04 , H03K5/19
摘要： PROBLEM TO BE SOLVED: To detect a signal error or malfunction inside a digital circuit device at low cost to improve reliability, in the digital circuit device with a disturbance detection function for a clock signal.
SOLUTION: This digital circuit device comprises: a signal pattern generation circuit 1-1 generating a regular cyclic digital signal pattern in synchronization with the clock signal that is a target of disturbance detection; and a signal pattern validity confirmation circuit 1-2 checking whether the cyclic digital signal pattern outputted from the signal pattern generation circuit 1-1 coincides with prescribed regularity or not. The signal pattern generation circuit 1-1 and the signal pattern validity confirmation circuit 1-2 are each configured by use of a flip-flop circuit (FF) 1-3 and a combination logic circuit 1-4, and the clock signal CLK that is the disturbance detection target is inputted to a clock terminal of each the flip-flop circuit (FF). It is decided that clock signal disturbance is absent when the pattern coincides with the prescribed regularity, and it is decided that the clock signal disturbance is present when the pattern does not coincide with the prescribed regularity.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：在具有用于时钟信号的干扰检测功能的数字电路装置中，以低成本检测数字电路装置内的信号错误或故障以提高可靠性。解决方案：该数字电路装置包括：信号图案生成电路1-1，与作为干扰检测对象的时钟信号同步地产生规则的循环数字信号图形; 以及信号图案有效性确认电路1-2，检查从信号图案生成电路1-1输出的循环数字信号图案是否与规定的规律一致。信号图案生成电路1-1和信号图案有效性确认电路1-2分别使用触发电路（FF）1-3和组合逻辑电路1-4以及时钟信号CLK 干扰检测目标被输入到每个触发器电路（FF）的时钟端。当图案与规定的规律一致时，判断为不存在时钟信号干扰，并且当图案不符合规定的规律性时，判断为存在时钟信号干扰。版权所有（C）2005，JPO＆NCIPI

6. 发明专利

JPH08106428A CPU SYSTEM 失效
公开(公告)号：JPH08106428A
公开(公告)日：1996-04-23
申请号：JP24011794
申请日：1994-10-04
申请人： FUJITSU LTD
发明人： TAKADA ISAO
IPC分类号： G06F13/14
摘要： PURPOSE: To provide the CPU system in which an active insertion unit can be incorporated. CONSTITUTION: In the CPU system wherein >=1 CPU units 1 and 34 and an I/O unit 31 are connected to a system bus 50 and the CPU unit 1 serves as a managing unit while the units 31 and 34 operate as managed units, the managed units 31 and 34 inform the managing unit 1 of their unit address information at the time of active insertion into the system and the managing unit 1 manages the managed units 31 and 34 with the unit address information. The managed units 31 and 34 report the unit address information in response to their power-ON reset signals generated at the time of the active insertion into the system, but are stopped from reporting their unit address information with a system reset signal generated by the managing unit 1 when the power system is powered ON. The managing unit 1 stores the unit address information on all the managed units 31 and 34 in a rewritable nonvolatile memory in advance.

7. 发明专利

JP2000269910A TRANSMITTER AND METHOD FOR TERMINATING DATA 失效
公开(公告)号：JP2000269910A
公开(公告)日：2000-09-29
申请号：JP6900099
申请日：1999-03-15
申请人： FUJITSU LTD
发明人： KAWAMURA HIDETOSHI , MIYAHARA SEIJI , SHIODA KAZUNARI , TAKADA ISAO , OKA AKIHIKO
IPC分类号： H04J3/00
摘要： PROBLEM TO BE SOLVED: To obtain a backbone transmitter with a large capacity and containing a plurality of channels. SOLUTION: The backbone transmitter of a large capacity consists of line interface sections 321-32n that interface communication channels, a main signal processing section 54 that branches, inserts, exchanges signals and an overhead data termination section 34 that applies termination processing to an overhead of a received signal. The overhead data termination section 34 consists of an OH-ASIC 51 which is a serial link interface section and a CPU 52 which controls the OH-ASIC 51. Serial links, consisting of serial data lines each having a plurality of layers and clock lines, are placed between the line interface sections 321-32n and the overhead data terminating section 34.

8. 发明专利

JPH04349560A BUS MASTER ARBITRATION SYSTEM 失效
公开(公告)号：JPH04349560A
公开(公告)日：1992-12-04
申请号：JP12350391
申请日：1991-05-28
申请人： FUJITSU LTD
发明人： TAKADA ISAO
IPC分类号： G06F13/362 , G06F13/366
摘要： PURPOSE:To provide the bus arbitration system which can shorten a period for detecting whether a signal input exists or not by executing a pass without giving a clock pulse for checking whether a bus use request signal exists or not to an unused terminal, with regard to a system for arbitrating a bus use request in a data processor in which plural bus masters are connected to one bus. CONSTITUTION:In bus use request terminals 21, 22... 2n, 2(n+1)... 2p of a bus use request priority deciding part 2, 2(n+1)... 2p which are not connected to bus masters 11, 12... 1n in order to input a bus use request signal are fixed in advance to a level being different from a level of the bus use request terminals 21, 22... 2n connected to the bus masters 11, 12... 1n at the time of resetting the bus masters 11, 12... 1n. At the time of resetting the bus masters 11, 12... 1n, a level of the bus use request terminals 21, 22... 2n, 2(n+1) ...2p is checked, and as for the terminals 2(n+1)... 2p being in a fixed level, whether an input of a bus use request signal exists or not is not checked thereafter.

9. 发明专利

JPH0628207A COMPUTER SYSTEM WITH INDEPENDENT OPERATION GUARANTEEING FUNCTION 失效
公开(公告)号：JPH0628207A
公开(公告)日：1994-02-04
申请号：JP17865292
申请日：1992-07-06
申请人： FUJITSU LTD
发明人： TAKADA ISAO , TERADA NOBUYUKI
IPC分类号： G06F11/20 , G06F13/00 , G06F13/36
摘要： PURPOSE:To provide the computer system with the independent operation guaranteeing function which enables plural extension systems to operate independently even in case of abnormality of a basic system such as a power-source disconnection and a cable disconnection by detecting the abnormality of the basic system. CONSTITUTION:The basic system 1 and extension systems 6 are connected with a data communication bus and the basic system is equipped with a bus priority deciding means 4 which decides the right to use the bus and an abnormal state detecting means 5 which detects the abnormality of the basic system 1. Further, each of the extension systems 6 is equipped with an abnormal state detecting means 11 which detects an abnormality information signal sent out of the basic system 1, a bus priority deciding means 9 which controls a use request signal and a bus acquisition signal for the bus, and a bus control deciding means 10 which makes a decision regarding the use of the bus.

10. 发明专利

JP2001326664A RING CONFIGURATION METHOD AND ITS NODE UNIT 失效
公开(公告)号：JP2001326664A
公开(公告)日：2001-11-22
申请号：JP2000225728
申请日：2000-07-26
申请人： FUJITSU LTD
发明人： UEMATSU KUMIKO , KANZAWA HIROSHI , HONDA TAKASHI , MORIYAMA JUNICHI , SHIODA KAZUNARI , KAWAMURA HIDETOSHI , TAKADA ISAO , YOSHIHARA YUKIE , NAITO KANJI
IPC分类号： H04L12/24 , H04L12/42 , H04L12/43 , H04L12/437
摘要： PROBLEM TO BE SOLVED: To provide a ring configuration method that can configure a topology required for BLSR in an open ring and conduct switching by a BLSR switching protocol in the open ring, and to provide its node unit. SOLUTION: In the ring configuration method, where topology data are circulated to each of nodes in a network of a ring configuration in which the nodes are linearly connected to collect connection information of each of the nodes being components of the ring, thereby configuring the topology of the ring, a flag to instruct presence/absence of collection of the connection information in each node is provided to the topology data, terminal stations at both end nodes of the open ring invert the flag and loop back the topology data. The nodes, which not are the end stations, pass the data without modifying the flag and each node adds connection information to the topology data according to the flag to configure the topology. Thus, the topology required for the BLSR can automatically be configured in the open ring, and a squelch table can be configured on the basis of the configuration topology.

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