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1. 发明专利

JPS6121637A Timing generating device 失效
标题翻译：时序生成装置
公开(公告)号：JPS6121637A
公开(公告)日：1986-01-30
申请号：JP14136784
申请日：1984-07-10
申请人： Fujitsu Ltd
发明人： YAMASHITA ATSUSHI , KATOU TADAYOSHI
IPC分类号： H04J3/06 , G06F13/42 , H04B7/15 , H04B7/212
CPC分类号： G06F13/4221
摘要： PURPOSE:To attain the processing with flexibility such as using a part where a program of identical patterns is used repetitively as a subroutine by decoding control information relating to the memory access order read from a storage means to change the order of memory access and generating a timing signal based on the timing information read from the storage means. CONSTITUTION:A timing generating circuit 3 by a frame pulse is started, an instrucion decoder 301 reads an instruction word from a RAM2, its content is decoded and when the instruction word is a JMP instruction of a command mode, a jump destination address is designated to the RAM2 via an address counter 304 to read to the instruction word of the jump destination address at the next cycle. When the instruction word is in, e.g., a RAM count mode, an output port number included in the instruction word is set to a decoder 303 to designate an output port from which the timing pulse is outputted. The timing pulse length of the content of the next address is set to the counter 302 at the next cycle and an output is transmitted from a designated output port.
摘要翻译：目的：通过解码与从存储装置读取的存储器存取顺序相关的控制信息来重复地使用相同模式的程序作为子程序的部分，以灵活性来实现处理，以改变存储器访问的顺序并产生基于从存储装置读取的定时信息的定时信号。构成：通过帧脉冲开始定时发生电路3，指令解码器301从RAM2读取指令字，对其内容进行解码，当指令字为命令模式的JMP指令时，指定跳转目标地址通过地址计数器304发送到RAM2，以在下一个周期读取跳转目标地址的指令字。当指令字处于例如RAM计数模式时，包括在指令字中的输出端口号被设置到解码器303以指定输出定时脉冲的输出端口。在下一个周期将下一个地址的内容的定时脉冲长度设置到计数器302，并且从指定的输出端口发送输出。

2. 发明专利

JPS60227544A UNIQUE WORD DETECTING DEVICE 失效
公开(公告)号：JPS60227544A
公开(公告)日：1985-11-12
申请号：JP8341684
申请日：1984-04-25
申请人： FUJITSU LTD
发明人： ISHIKAWA HITOSHI , KATOU TADAYOSHI
IPC分类号： H04J3/06 , H03J3/06 , H04B7/155 , H04L7/04 , H04L7/08
摘要： PURPOSE:To attain LSI of the titled device by processing independently a data obtained through parallel expansion of a reception data and a coincident bit or a dissident bit of a unique word UW pattern respectively so as to detect a UW signal at a high speed. CONSTITUTION:Shift registers 1-1-1-2 of a unique word UW detector 1 expand a serial reception data into a parallel data based on a clock signal in synchronizing with the reception data and input the result to dissident bit detecting circuits 3-1-3-2. A prescribed UW pattern from a UW pattern generator 2 is inputted to the detection circuits 3-1-3-2 so as to detect the coincident/dissident bit of the expanded reception data. The bit number of coincidence/dissidence is added by adders 4-1, 4-2 at each channel. The number of additions of coincidence/dissidence from the adders 4-1, 4-2 is outputted externally from an output port 5, fed to a comparator 7 via an adder 6 and the UW signal is detected at a high speed by using tolerance of a tolerance generator 8.

3. 发明专利

JPS60173930A PIPELINE PROCESSING VITERBI DECODER 失效
公开(公告)号：JPS60173930A
公开(公告)日：1985-09-07
申请号：JP2848884
申请日：1984-02-20
申请人： FUJITSU LTD
发明人： YAMASHITA ATSUSHI , KATOU TADAYOSHI , KURIHARA HIROSHI
IPC分类号： G06F11/10 , H03M13/23 , H03M13/41
摘要： PURPOSE:To improve the throughout by executing in parallel the path metric calculation and comparison. CONSTITUTION:The path metric value of added output selected by selectors 37, 38 is compared and path selecting information is outputted to a comparator 41 in adding the next path metric value by adders 31-34. Since the path metric value of the preceding added output is compared by the comparator 41, the pipeline processing is attained.

4. 发明专利

JPS60144026A VITERBI DECODER 失效
公开(公告)号：JPS60144026A
公开(公告)日：1985-07-30
申请号：JP65184
申请日：1984-01-06
申请人： FUJITSU LTD
发明人： YAMASHITA ATSUSHI , KATOU TADAYOSHI
IPC分类号： H03M13/23 , H03M13/41 , H03M13/12
摘要： PURPOSE:To inhibit a metric calculation to a dummy bit without increasing a circuit scale by providing a code converting part for converting an inversion and a non-inversion of a receiving code by receiving a metric calculation inhibiting signal, on a branch metric calculating circuit. CONSTITUTION:At the time of a branch metric calculation, a code is converted immediately before adding a code, dummy bits QR and -QR are set to the same value, and an equal effect to that which has inhibited a metric calculation is given. Code converting parts 767, 768 are added to a branch metric calculating part 76. The code converting part 767 converts a code so as to be I=-I only when a metric calculation inhibiting signal INH from a dummy bit inserting part is active, and outputs I and -I as they are in other case. The code converting part 768 also executes the same. The dummy bit inserting part knows an inserting position of a dummy bit, therefore, the inhibiting signal INH to be inputted to the code converting parts 767, 768 from said part can be generated easily.

5. 发明专利

JPS59134929A Frequency converter group 失效
标题翻译：频率转换器组
公开(公告)号：JPS59134929A
公开(公告)日：1984-08-02
申请号：JP954583
申请日：1983-01-24
申请人： Fujitsu Ltd
发明人： KATOU TADAYOSHI , TAKANO TAKESHI , SHIMA TAKAO
IPC分类号： H04J4/00 , H04B7/185 , H04J1/06
CPC分类号： H04J1/06
摘要： PURPOSE:To attain small size, light weight and low power consumption by providing a crystal oscillator outputting a frequency at equal intervals of an input signal a means obtaining a frequency difference in the order of a local oscillator at equal intervals of frequency difference, a phase comparator and a phase locked loop. CONSTITUTION:The crystal oscilltator 11 is a crystal oscillator highly stable in frequency at equal intervals to an input signal. Signals of inptted frequencies f1 fn are time division multiplex signals having the frequency difference of equal intervals in the order of frequencies. A signal having a frequency difference fL2 -fL1 of local oscillators 7-1, 7-2 is obtained by a frequency converter 8-1, a phase detector 9-1 detects a phase difference between a signal of the difference frequency an output signal of the crystal oscillator 11, this output is applied to a VCO7-2 via loop filter 10-1 and controlled so as to eliminate the said phase difference. Thus, the shift in common frequency of the local oscillator and the frequency difference between the oscillators are suppressed by the characteristic of the crystal oscillator 11 and the difference in the intermediate frequency is eliminated. Thus, the local oscillator is constituted of a microwae oscillator with small-sized and low power consumption, and one crystal oscillator is enough for the circuit.
摘要翻译：目的：通过提供以输入信号等间隔输出频率的晶体振荡器来实现小尺寸，轻量化和低功耗，意味着以等间隔的频差获得本地振荡器的频率差，相位比较器和锁相环。结构：晶体振荡器11是与输入信号等间隔的频率高度稳定的晶体振荡器。已知频率f1 fn的信号是具有按频率顺序的等间隔的频差的时分复用信号。具有本地振荡器7-1,7-2的频率差fL2-fL1的信号由频率转换器8-1获得，相位检测器9-1检测差频信号之间的相位差，晶体振荡器11，该输出通过环路滤波器10-1被施加到VCO7-2，并被控制以消除所述相位差。因此，通过晶体振荡器11的特性来抑制本地振荡器的共频率偏移和振荡器之间的频率差，并且消除了中频的差异。因此，本地振荡器由具有小尺寸和低功耗的微型振荡器构成，并且一个晶体振荡器对于该电路是足够的。

6. 发明专利

JPS59112749A Differential logical circuit for multivalued orthogonal amplitude modulation 失效
标题翻译：用于多变量正交振幅调制的差分逻辑电路
公开(公告)号：JPS59112749A
公开(公告)日：1984-06-29
申请号：JP22262982
申请日：1982-12-18
申请人： Fujitsu Ltd
发明人： KATOU TADAYOSHI
IPC分类号： H04L27/34
CPC分类号： H04L27/34
摘要： PURPOSE:To perform code conversion even in multivalued orthogonal amplitude modulation by providing a logical circuit which superposes signals of the 1st, the 2nd, and the 3rd paths that divide the signal plane of orthogonal amplitude modulation into four quadrants. CONSTITUTION:Binary signals P1 and q1 of the 1st bus which divides the signal plane of orthogonal amplitude modulation into four quadrants are inputted to a four-phase PSK transmitting logical circuit 13, whose output signals P1' and q1' are ORed exclusively by an element E1, whose output is supplied to an inverting logical circuit 15. The circuit 15 inverts binary signals P2 and q2 of the 2nd path which further divides the four- divided quadrants into four in polarity when the output of AND A1 between the E1 output and the output of exclusive OR E2 between the binary signals P2 and q2 is 1. Binary signals P3 and q3 of the 3rd path which further divides quadrants divided by the 2nd path into four are inptted to an inverting logical circuit 17 and ORed E3 exclusively, and when the output of AND A2 between the E3 output and E2 output is 1, the signals P3 and q3 are inverted in polarity. A Gray encoding orthogonal amplitude modulator 11 imposes 64-phase modulation upon outputs of the circuits 13, 15, and 17 to generate an output. The signal is demodulated on a reception side in the reverse route to output signals P1-P3 and q1-q3.
摘要翻译：目的：即使在多值正交幅度调制中执行代码转换，通过提供一个将正交幅度调制信号平面分为四个象限的第一，第二和第三路径的信号叠加的逻辑电路。构成：将正交幅度调制信号平面划分为四个象限的第一总线的二进制信号P1和q1输入到四相PSK发送逻辑电路13，四相PSK发送逻辑电路13的输出信号P1'和q1'由一个元件 E1，其输出被提供给反相逻辑电路15.电路15反转第二路径的二进制信号P2和q2，当二进制信号P2和P2之间的输出与E1输出与二进制信号P2和q2之间的异或E2的输出是1.进一步将第二路径划分为四路的第三路径的二进制信号P3和q3独占地转换为反相逻辑电路17和OR为E3， E3输出和E2输出之间的AND A2的输出为1，信号P3和q3的极性反转。灰度编码正交幅度调制器11对电路13,15和17的输出施加64相位调制以产生输出。该信号在反向路径的接收侧被解调，以输出信号P1-P3和q1-q3。

7. 发明专利

JPS561644A MONITOR SYSTEM FOR COMMUNICATION CIRCUIT QUALITY 失效
公开(公告)号：JPS561644A
公开(公告)日：1981-01-09
申请号：JP7701779
申请日：1979-06-19
申请人： FUJITSU LTD
发明人： TAKENAKA SADAO , KATOU TADAYOSHI
IPC分类号： H04L1/20 , H04L1/00 , H04L1/24 , H04L27/00
摘要： PURPOSE:To realize the quick and high-accuracy measurement for the error rate of the real circuit through the measurement of the false error rate by leading the false error pulse out of the demodulated signal, at the same time simplifying the circuit constitution. CONSTITUTION:The fixed coefficient is multiplied by coefficient units 6-9 to part of demodulated signals (b) and (c) obtained by giving synchronous detection DET to the 4-phase SK wave, and then such partial signals (b) and (c) are supplied to adder/subtractors 10 and 11. Thus base band arithmetic signals (f) and (g) are obtained at the outputs of 10 and 11 each and then receive the discrimination and regeneration through discriminators 12 and 13 to be compared at exclusive logic sum circuits 14 and 15 with signals (d) and (e) which are obtained by giving discrimination and regeneration 4 and 5 to demodulated signals (b) and (c) of the main route. And each cmparison output is supplied to exclusive logic sum circuit 16. Thus false error pulse (l) is obtained from circuit 16, and the false error rate is measured. And error rate Pe of the real circuit is presumed.

8. 发明专利

JPS5558649A ERROR RATE MONITOR UNIT 失效
公开(公告)号：JPS5558649A
公开(公告)日：1980-05-01
申请号：JP13180678
申请日：1978-10-26
申请人： FUJITSU LTD
发明人： KATOU TADAYOSHI , ITAYA EIJI , HARA TAKAO
IPC分类号： H04L1/00 , H04L1/20 , H04L27/00
摘要： PURPOSE:To estimate always a true error rate correctly by comparing output signals of the first demodulator circuit for synchronizing phase detection and the second demodulator circuit for delay detection with each other to obtain a disagreement output. CONSTITUTION:In the first demodulator circuit 1, PSK phase detector 6 performs the synchronizing detection of an inputted four-phase PSK wave, and the output is discriminated by 3 and is subjected to code conversion in 5, and after that, reproducing signals are outputted. Meanwhile, in the second demodulator circuit 2, the input four- phase PSK wave is subjected to delay detection by PSK phase detector 8, and the output is disciminated by 4 and is outputted. Output signals of the first and the second demodulator circuits are compared with each other through exclusive OR circuits 10 and 11 to obtain a disagreement output. As a result, a false error signal having always correspondence relation to the error rate of reproducing signals obtained from the four-phase PSK modulation wave can be obtained, so that a true error rate can be always estimated correctly.

9. 发明专利

JPS54100639A BANDDPASS FILTER CIRCUIT 失效
公开(公告)号：JPS54100639A
公开(公告)日：1979-08-08
申请号：JP749078
申请日：1978-01-26
申请人： FUJITSU LTD
发明人： KURIHARA HIROSHI , KATOU TADAYOSHI
IPC分类号： H03H7/06 , H03H11/04 , H03L7/093 , H03L7/10 , H04B7/155 , H04L27/22
摘要： PURPOSE:To attenuate noise in a narrow band, and also to attain leading-in at a high speed by equipping a loop filter with its charging time constant smaller than discharging one and by controlling a voltage control oscillator by its output voltage. CONSTITUTION:Loop filter 104 composed of semiconductor D1, resistances R1 and R2, and capacitor C is so selected that its charging time constant will be smaller than discharging one. Then, a phase difference between connection points 13 and 14 or that of a regenerated carrier is denoted by (phi), which is in proportion to difference (f-f0) between frequency (f) of an input sine wave at connection point 13 and center frequency (f0) of band-pass filter 102, and the control voltage of voltage control oscillator VCD105 is nearly in proportion to (phi) within the constant operation range of automatic frequency control voltage AFC. By the output voltage of filter 104, oscillator VCO105 is controlled. Consequently, noise can be attenuated in a narrow band, and high-speed leading-in can also be attained.

10. 发明专利

JPS5455355A THREEEPHASE PHASE MODULATOR 失效
公开(公告)号：JPS5455355A
公开(公告)日：1979-05-02
申请号：JP12270377
申请日：1977-10-13
申请人： FUJITSU LTD
发明人： SASAKI SHIYUNROKU , SEKIZAWA TADASHI , TSUJI YOSHITOSHI , KATOU TADAYOSHI
IPC分类号： H04L27/20 , H03C3/00
摘要： PURPOSE:To generate a three-phase PSK signal by using three two-phase modulator with two pahse states and by mixing their outputs. CONSTITUTION:Pieces of binary data S1, S2 and S3 outputted from code converter 2 are led to balanced modulators 3, 4 and 5 composed of ring modulators performing two-pahse mdoulation. On the other hand, balanced modulator 3 is applied with output signal C1 of carrier oscillator 6, balanced modulator 4 is with signal C2 phase-shifted by +60 deg. by phase shifter 7, and balanced modulator 5 is with signal C3 phase-shifted by -60 deg. by phase shifter 8. Outputs P1, P2 and P3 of balanced modulators 3, 4 and 5 are supplied to hybrid 9, where they are mixed together, so that the composite signal will be outputted from output terminal 10. Therefore, the simple constitution using two-phase pahse modulators is able to generate three- phase PSK signals.

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