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1. 发明专利

JPS5432913A ERROR RATE SUPERVISORY SYSTEM 失效
公开(公告)号：JPS5432913A
公开(公告)日：1979-03-10
申请号：JP9928177
申请日：1977-08-19
申请人： FUJITSU LTD
发明人： TSUJI YOSHITOSHI , KATOU TADAYOSHI , HARA TAKAO , YOSHIZAWA RIYUUSHIROU
IPC分类号： H04L1/00 , H04L1/20 , H04L27/00
摘要： PURPOSE:To make an error rate supervision possible by a simple constitution by using one phase detector independently of the number of phases in the N-phase PSK system.

2. 发明专利

JPS53147404A WORD SYNCHRONOUS SYSTEM 失效
公开(公告)号：JPS53147404A
公开(公告)日：1978-12-22
申请号：JP6185177
申请日：1977-05-27
申请人： FUJITSU LTD
发明人： TSUJI YOSHITOSHI , YOSHIZAWA RIYUUSHIROU , HARA TAKAO
IPC分类号： H04L7/00 , H04L7/04 , H04L27/22 , H04L27/227
摘要： PURPOSE:To correctly perform the demodulation of three phase modulation signal, by taking the detection timing of the synchronous word at the head of data as a reference.

3. 发明专利

JPS53147456A ELIMINATION CIRCUIT OF DEMODULATED PHASE UNCERTAINTY 失效
公开(公告)号：JPS53147456A
公开(公告)日：1978-12-22
申请号：JP6185277
申请日：1977-05-27
申请人： FUJITSU LTD
发明人： TSUJI YOSHITOSHI , YOSHIZAWA RIYUUSHIROU , HARA TAKAO
IPC分类号： H04L27/22 , H03D3/00
摘要： PURPOSE:To elininate the demodulated phase uncertainty, by connecting registers and switch circuits corresponding to the number of symbols of synchronous words, controlling the switch circuits with the output of a control signal generating circuit, and picking up demodulation signals from the switch circuits.

4. 发明专利

JPS53147454A CODE CONVERSION SYSTEM 失效
公开(公告)号：JPS53147454A
公开(公告)日：1978-12-22
申请号：JP6185077
申请日：1977-05-27
申请人： FUJITSU LTD
发明人： TSUJI YOSHITOSHI , YOSHIZAWA RIYUUSHIROU , HARA TAKAO , KATOU TADAYOSHI
IPC分类号： H03M5/20 , H04L27/20
摘要： PURPOSE:To rationally execute the three phase shift keying modulation, by converting the binary data in n-bit into the binary signal consisting of m sets of 3-bit with a logical circuit, performing phase designation for the output, and sequentially outputting m sets of signals designated.

5. 发明专利

JPS5125014A FM TSUSHINHOSHIKI 失效
公开(公告)号：JPS5125014A
公开(公告)日：1976-03-01
申请号：JP9764674
申请日：1974-08-26
申请人： FUJITSU LTD
发明人： NAKAMURA HIROSHI , HARA TAKAO , AOKI SHINICHIRO
IPC分类号： H04B1/04 , H03D3/00 , H04B1/00 , H04B1/02 , H04B7/155 , H04B7/165 , H04B14/00

6. 发明专利

JPS5558649A ERROR RATE MONITOR UNIT 失效
公开(公告)号：JPS5558649A
公开(公告)日：1980-05-01
申请号：JP13180678
申请日：1978-10-26
申请人： FUJITSU LTD
发明人： KATOU TADAYOSHI , ITAYA EIJI , HARA TAKAO
IPC分类号： H04L1/00 , H04L1/20 , H04L27/00
摘要： PURPOSE:To estimate always a true error rate correctly by comparing output signals of the first demodulator circuit for synchronizing phase detection and the second demodulator circuit for delay detection with each other to obtain a disagreement output. CONSTITUTION:In the first demodulator circuit 1, PSK phase detector 6 performs the synchronizing detection of an inputted four-phase PSK wave, and the output is discriminated by 3 and is subjected to code conversion in 5, and after that, reproducing signals are outputted. Meanwhile, in the second demodulator circuit 2, the input four- phase PSK wave is subjected to delay detection by PSK phase detector 8, and the output is disciminated by 4 and is outputted. Output signals of the first and the second demodulator circuits are compared with each other through exclusive OR circuits 10 and 11 to obtain a disagreement output. As a result, a false error signal having always correspondence relation to the error rate of reproducing signals obtained from the four-phase PSK modulation wave can be obtained, so that a true error rate can be always estimated correctly.

7. 发明专利

JPS5457905A DELTA MODULATION AND DEMODULATION SYSTEM 失效
公开(公告)号：JPS5457905A
公开(公告)日：1979-05-10
申请号：JP12479777
申请日：1977-10-18
申请人： FUJITSU LTD
发明人： ASAHARA MASARU , YOSHIZAWA RIYUUSHIROU , HARA TAKAO
IPC分类号： H04B14/06 , H04B1/62
摘要： PURPOSE:To suppress the occurrence of cross modulation distortion for two signals without deteriorating the frequency characteristic of a transmission band and S/N, by attenuating enough high-band components of input signals in the SCPC satellite communication system, etc. CONSTITUTION:Input signals, which consist of sound signals or MF signals, from an exchange are coded dependently upon delta modulation in delta modulator 13 after having high-band components suppressed enough by input equalizer 12 which has characteristic A, and the coded output is transmitted through a modulator and a transmitter. In the receiving side, demodulated signals are applied to delta demodulator 16 to reproduce low-frequency signals. Then, original signals are reproduced faithfully by causing these signals to pass through output equalizer 17 which has characteristic B, and the output is transmitted to an exchange.

8. 发明专利

JPS61107836A Communication equipment 失效
标题翻译：通讯设备
公开(公告)号：JPS61107836A
公开(公告)日：1986-05-26
申请号：JP22797984
申请日：1984-10-31
申请人： Fujitsu Ltd
发明人： MISHIRO TOKIHIRO , HARA TAKAO , YOSHIZAWA RYUSHIRO
IPC分类号： H04J3/06 , H04B7/155 , H04J3/00 , H04L7/10
CPC分类号： H04L7/10
摘要： PURPOSE:To detect a unique word correctly with simple means by detecting a non-modulation carrier synchronizing pattern in the TDMA communication system and detecting the unique word incoming after a prescribed time. CONSTITUTION:A received PSK signal passes through a BPF1, noise is eliminated and the result is inputted to a carrier synchronizing pattern detection circuit 2 and a demodulator 4. The demodulator 4 regenerates a reference carrier from the input signal, a unique word detector 5 uses an aperture control signal SC based on the reference carrier to apply aperture window with a prescribed time width and extract the unique word, which is inputted to an AND circuit 6, The circuit 2 applies envelope detection 22 to a signal subject to improvement of the C/N through a narrow band BPF21, and an output signal S22 is compared with a prescribed threshold level by a voltage comparator 23. A signal S23 exceeding the threshold level is retarded for a prescribed time by a delay circuit 3, its output signal S3 is inputted to the circuit 6, from which the unique word detected by the detector 5 is outputted effectively.
摘要翻译：目的：通过检测TDMA通信系统中的非调制载波同步模式，并以规定的时间检测出唯一的字，通过简单的手段正确检测唯一的字。构成：接收的PSK信号通过BPF1，消除噪声，并将结果输入到载波同步模式检测电路2和解调器4.解调器4从输入信号再生参考载波，唯一字检测器5使用基于参考载波的孔径控制信号SC，以施加规定时间宽度的孔径窗口，并提取输入到AND电路6的唯一字。电路2将包络检测22应用于C的改进的信号 / N，并且通过电压比较器23将输出信号S22与规定的阈值电平进行比较。超过阈值电平的信号S23由延迟电路3延迟规定时间，其输出信号S3为输入到电路6，由检测器5检测到的唯一字被有效地输出。

9. 发明专利

JPS5824978B2 失效
公开(公告)号：JPS5824978B2
公开(公告)日：1983-05-24
申请号：JP2261974
申请日：1974-02-26
申请人： FUJITSU LTD
发明人： HARA TAKAO , TSUJI YOSHITOSHI , SAKAMOTO YASUHIKO
IPC分类号： H04J3/00 , H04B7/15 , H04B7/185 , H04J99/00

10. 发明专利

JPS5680940A ALARM DETECTOR OF TDMA MODEN 失效
公开(公告)号：JPS5680940A
公开(公告)日：1981-07-02
申请号：JP15738779
申请日：1979-12-06
申请人： FUJITSU LTD
发明人： HARA TAKAO , ITAYA EIJI
IPC分类号： H04L27/00 , H04B7/15 , H04B7/212 , H04J3/00
摘要： PURPOSE:To detect a fault by supervising states of burst enable and burst signals. CONSTITUTION:During the period of burst enable signal (a) generated by synchronizer 2, modulator 1 generates burst signal (b). During a burst period, signal (b) is converted into a signal of level ''H'', which is delayed. As the exclusive OR output between this signal and signal (a), pulse signal (e) held at level ''H'' in the beginning and ending of signal (a) is generated. Signal (a), on the other hand, is delayed and inputted to alarm generating circuit 7. Flip-flop 72 performs sampling nearly at the rise of signal (a) and, when signal (a) is in an ON state and burst signal (b) is not generated, sends an alarm. Flip-flop 73 performs sampling nealy at the fall of signal (a) and, when signal (a) is off and burst signal (b) is generated, gives the alarm.

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