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1. 发明专利

JP2012234337A Image data processing device and program 有权
标题翻译：图像数据处理设备和程序
公开(公告)号：JP2012234337A
公开(公告)日：2012-11-29
申请号：JP2011102130
申请日：2011-04-28
申请人： Fuji Xerox Co Ltd , 富士ゼロックス株式会社
发明人： OKUYAMA JUNICHI , YAMADA KAZUO
IPC分类号： G06T1/20
CPC分类号： G06F15/7875 , G06T1/20
摘要： PROBLEM TO BE SOLVED: To enhance the speed of a processing more than that of a method for determining image features of an image to be processed and then reconfiguring a circuit structure corresponding to the image features on a reconfigurable circuit.SOLUTION: Use results (for example, use frequencies) of each circuit structure used in each block that has been already processed in the image data are recorded in a reconfiguration result management section 32A. Whenever processing a block, the reconfiguration result management section 32A updates the use results, and a preload determination section 36A refers to the use results and determines a circuit structure that is highly possibly to be used in a next block. Before starting the processing of the next block, the configuration data corresponding to the determined circuit structure is loaded in a configuration memory 16.
摘要翻译：要解决的问题：提高处理速度比用于确定要处理的图像的图像特征的方法的速度高，然后重构与可重构电路上的图像特征相对应的电路结构。解决方案：使用在图像数据中已经处理的每个块中使用的每个电路结构的结果（例如，使用频率）被记录在重新配置结果管理部分32A中。每当处理块时，重新配置结果管理部32A更新使用结果，并且预加载确定部36A参考使用结果并且确定在下一个块中可能被使用的电路结构。在开始处理下一个块之前，将与确定的电路结构对应的配置数据加载到配置存储器16中。（C）2013，JPO＆INPIT

2. 发明专利

JP2008112274A Controller and program 审中-公开
标题翻译：控制器和程序
公开(公告)号：JP2008112274A
公开(公告)日：2008-05-15
申请号：JP2006294043
申请日：2006-10-30
申请人： Fuji Xerox Co Ltd , 富士ゼロックス株式会社
发明人： OKUYAMA JUNICHI , TAMAYA MITSUYUKI
IPC分类号： G06F9/48
摘要： PROBLEM TO BE SOLVED: To allow the suppression of a processing delay and the occurrence of useless processing, even if processing in a target is not performed as predicted.
SOLUTION: An image processor 100 has a host 10 and a target 20. The host 10 performs various kinds of processing for controlling the image processor 100, and requests the target 20 to perform specific image processing. The target 20 performs image processing requested from the host 10, and upon the completion thereof, transmits an interrupt signal to the host 10. When requesting the target 20 to perform image processing, the host 10 calculates a necessary time in the target 20 for the image processing. Then, the host 10 requests the target 20 to perform the image processing and after the necessary time elapses, processing performed in the host 10 is retreated into a memory 12, and made to wait for the transmission of an interrupt signal.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：即使不按预期执行目标处理，也可以抑制处理延迟和无效处理的发生。解决方案：图像处理器100具有主机10和目标20.主机10执行用于控制图像处理器100的各种处理，并请求目标20执行特定的图像处理。目标20执行从主机10请求的图像处理，并且在其完成时向主机10发送中断信号。当请求目标20执行图像处理时，主机10计算目标20中必要的时间图像处理。然后，主机10请求目标20执行图像处理，并且在必要时间过去之后，在主机10中执行的处理被退回到存储器12中，并且等待中断信号的发送。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2009135694A Information processor, and information processing program 有权
标题翻译：信息处理程序和信息处理程序
公开(公告)号：JP2009135694A
公开(公告)日：2009-06-18
申请号：JP2007309182
申请日：2007-11-29
申请人： Fuji Xerox Co Ltd , 富士ゼロックス株式会社
发明人： OKUYAMA JUNICHI
IPC分类号： H04N1/40 , G06T5/40
摘要： PROBLEM TO BE SOLVED: To suppress a storage capacity required for the creation of histogram in image processing.
SOLUTION: When the histogram to a pixel value of a pixel 120 being a processing object is created, partial histogram 130 including coordinates of a nearby range centering around the pixel value is set. When the pixel value of the next pixel 122 is included in the range of the set partial histogram 130, frequency addition is performed here, and when the pixel value is not included in the range of the set partial histogram 130, new partial histogram 132 is set. To a pixel 124, partial histogram 138 which is not overlapped with the set partial histogram 132 is set since a partial histogram 134 centering around the pixel value is overlapped with the set partial histogram 132 when the partial histogram 134 is set. In addition, reading is performed by referring to each partial histogram.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：抑制在图像处理中创建直方图所需的存储容量。解决方案：当对作为处理对象的像素120的像素值进行直方图创建时，设置包括以像素值为中心的附近范围的坐标的局部直方图130。当下一个像素122的像素值被包括在设定的部分直方图130的范围内时，这里执行频率相加，并且当像素值不包括在设定的部分直方图130的范围内时，新的部分直方图132 组。设置与像素124不重叠的部分直方图138，因为当设置部分直方图134时，以像素值为中心的部分直方图134与设定的部分直方图132重叠。另外，通过参照每个部分直方图来执行读取。版权所有（C）2009，JPO＆INPIT

4. 发明专利

JP2007279902A Memory control method, memory control device, image processor and program 有权
标题翻译：存储器控制方法，存储器控制装置，图像处理器和程序
公开(公告)号：JP2007279902A
公开(公告)日：2007-10-25
申请号：JP2006103345
申请日：2006-04-04
申请人： Fuji Xerox Co Ltd , 富士ゼロックス株式会社
发明人： OKUYAMA JUNICHI , TAMAYA MITSUYUKI
IPC分类号： G06T1/20 , H04N1/40
摘要： PROBLEM TO BE SOLVED: To perform high-speed processing with a minimized memory capacity in various image processors using a line memory. SOLUTION: The image processor 100 supplies image data stored in a memory such as DRAM 10 or SRAM 20 to an image processing part 30 to perform predetermined image processing. The DRAM 10 is composed of a plurality of memory banks, a memory control part 50 controls reading and writing of image data to each memory. When input image data is written to the DRAM 10, the memory control part 60 writes division image data obtained by dividing the image data in predetermined units to the DRAM 10 so that each of the division image data continued in the line direction or row direction is not stored in the same memory bank. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：使用行存储器在各种图像处理器中以最小的存储容量执行高速处理。解决方案：图像处理器100将存储在诸如DRAM10或SRAM20的存储器中的图像数据提供给图像处理部分30以执行预定的图像处理。 DRAM10由多个存储体构成，存储器控制部分50控制对每个存储器的图像数据的读取和写入。当输入图像数据被写入DRAM10时，存储器控制部分60将以预定单位划分图像数据而获得的分割图像数据写入到DRAM10中，使得在行方向或行方向上继续的分割图像数据为不存储在同一个存储器中。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP2005275680A Information processing method and information processor, and program 有权
标题翻译：信息处理方法和信息处理程序及程序
公开(公告)号：JP2005275680A
公开(公告)日：2005-10-06
申请号：JP2004086522
申请日：2004-03-24
申请人： Fuji Xerox Co Ltd , 富士ゼロックス株式会社
发明人： OKUYAMA JUNICHI , MAEDA YASUYORI
IPC分类号： G06F21/24 , G06F12/14 , G06F13/00 , G06F15/00
摘要： PROBLEM TO BE SOLVED: To provide an information processor for performing predetermined information processing accompanied with the transmission/reception of data between information terminals, the information processor in which address selection is facilitated, and the leakage of address information is prevented. SOLUTION: An address information acquiring part 120 acquires address information for specifying the transmission/reception destination of data from another terminal. An address information classifying part 230 classifies the acquired address information based on the processing contents of data transmission/reception in an information processing part 110, and group-classifies the address information based on marker information attached to the address information. An address information presenting part 260 extracts only the address information relevant to the processing contents when an information processing part 110 performs data transmission/reception from among the address information acquired by the address information acquiring part 120 based on each classification result, and presents it to an operation panel part 600a or the like. After using the address information, an address information erasure control part 170 erases the registration or display of the address information to the address information storing part 130. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于执行伴随信息终端之间的数据的发送/接收的预定信息处理的信息处理器，其中有助于地址选择的信息处理器，并且防止了地址信息的泄露。解决方案：地址信息获取部分120从另一终端获取用于指定数据的发送/接收目的地的地址信息。地址信息分类部230基于信息处理部110中的数据发送/接收的处理内容对获取的地址信息进行分类，并且基于附加到地址信息的标记信息对地址信息进行分组分类。当信息处理部分110基于每个分类结果从地址信息获取部分120获取的地址信息中执行数据发送/接收时，地址信息呈现部分260仅提取与处理内容相关的地址信息，并将其呈现给操作面板部600a等。在使用地址信息之后，地址信息擦除控制部分170将地址信息的登记或显示擦除到地址信息存储部分130.版权所有：（C）2006，JPO＆NCIPI

6. 发明专利

JP2013125419A Hardware-software collaborative design device and program 有权
标题翻译：硬件协同设计设计与程序
公开(公告)号：JP2013125419A
公开(公告)日：2013-06-24
申请号：JP2011273842
申请日：2011-12-14
申请人： Fuji Xerox Co Ltd , 富士ゼロックス株式会社
发明人： OKUYAMA JUNICHI , YAMADA KAZUO
IPC分类号： G06F17/50 , G06F9/50
CPC分类号： Y02D10/22 , Y02D10/36
摘要： PROBLEM TO BE SOLVED: To perform a design for reducing the power consumption of a hardware-software collaborative system while satisfying the target performance of the system.SOLUTION: A code structure analysis part 101 detects an execution unit of a program code 302 by granularity. A code load analysis part 103 estimates the calculation volume of each of the execution units. A HW-converting target selection part 104 selects, as HW-converting targets, execution units whose calculation volumes each exceeds a predetermined threshold ratio to the entire calculation volume of the program code 302 in an ascending order of granularity. A HW block synthesis part 106 synthesizes the selected execution unit as a HW block on a reconfigurable circuit 204. In accordance with the synthesis result, a HW/SW collaborative operation part 108 configures a target system 200 as a HW/SW collaborative system, causes process-target data 304 to be processed and measures an actual system performance at the processing. A HW/SW design completion determination part 110 determines to be a design complete in the case of determining that the actually measured performance has realized the target performance.
摘要翻译：要解决的问题：为了在满足系统的目标性能的同时执行降低硬件 - 软件协同系统的功耗的设计。解决方案：代码结构分析部件101通过粒度来检测程序代码302的执行单元。代码负载分析部件103估计每个执行单元的计算量。 HW转换目标选择部分104按照粒度的升序选择其计算量各自超过程序代码302的整个计算量的预定阈值比的执行单元作为HW转换目标。 HW块合成部分106将所选择的执行单元合成为可重构电路204上的HW块。根据合成结果，HW / SW协作操作部分108将目标系统200配置为HW / SW协作系统，导致处理目标数据304并且在处理时测量实际的系统性能。在确定实际测量的性能已经实现了目标性能的情况下，HW / SW设计完成确定部件110确定为设计完成。版权所有（C）2013，JPO＆INPIT

7. 发明专利

JP2010003035A Data processor 审中-公开
标题翻译：数据处理器
公开(公告)号：JP2010003035A
公开(公告)日：2010-01-07
申请号：JP2008160082
申请日：2008-06-19
申请人： Fuji Xerox Co Ltd , 富士ゼロックス株式会社
发明人： YAMADA KAZUO , NAITO TAKAO , TAMAYA MITSUYUKI , OKUYAMA JUNICHI , MATSUMOTO DAISUKE
IPC分类号： G06F12/04 , G06T1/20 , H04N5/92
摘要： PROBLEM TO BE SOLVED: To reduce the use amount of external memory while suppressing the reduction in data processing performance without increasing hardware resources, in a data processor having an accelerator system configuration. SOLUTION: A stream to be compressed is specified for each reconfigured stage so that local memory does not become over-capacity based on a non-accumulation type stream, an accumulation type stream, and an available capacity of the local memory, and the existence of application of compression processing or extension processing is controlled in relation to the stream to be compressed. For example, a compression threshold TH is calculated for each stage (S1010), and a compressor and an extending apparatus are inserted into the stage if possible (S1022). When over-capacity occurs during image processing applied with the compression processing, primary fall back processing is applied (S1042). When over-capacity occurs even by application of the primary fall back processing, a secondary fall back processing is applied (S1046). COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：在具有加速器系统配置的数据处理器中，为了在不增加硬件资源的同时抑制数据处理性能的降低，减少外部存储器的使用量。解决方案：为每个重新配置的级指定要压缩的流，以便本地存储器不会基于非累积类型流，累积类型流和本地存储器的可用容量而变为过大容量，以及相对于要压缩的流来控制压缩处理或扩展处理的应用的存在。例如，对于各级计算压缩阈值TH（S1010），如果可能，则将压缩机和扩展装置插入到该级（S1022）。当在压缩处理应用的图像处理期间发生过度容量时，应用主回退处理（S1042）。当即使通过应用主回落处理也发生过度容量时，应用二次倒退处理（S1046）。版权所有（C）2010，JPO＆INPIT

8. 发明专利

JP2009025953A Arithmetic processing unit and arithmetic processing program 有权
标题翻译：算术处理单元和算术处理程序
公开(公告)号：JP2009025953A
公开(公告)日：2009-02-05
申请号：JP2007186848
申请日：2007-07-18
申请人： Fuji Xerox Co Ltd , 富士ゼロックス株式会社
发明人： OKUYAMA JUNICHI , TAMAYA MITSUYUKI
IPC分类号： G06F9/38 , G06F9/50
摘要： PROBLEM TO BE SOLVED: To provide an arithmetic processing unit for shortening a whole processing time required for a plurality of processings.
SOLUTION: A plurality of floor plan layouts in which areas to be used by a reconfigurable circuit are different are stored for every process belonging to each task. Then, the process is set until the number of use areas exceeds the number of all division areas in the order of the performance object process of a high priority task (S54 to S66). Then, the floor plan layout in which the use areas are not overlapped is selected with respect to the set process (S68 to S74), and the reconfigurable circuit is reconfigured with corresponding configuration data.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于缩短多个处理所需的整个处理时间的算术处理单元。解决方案：对于属于每个任务的每个进程，存储多个平面图布局，其中由可重构电路使用的区域不同。然后，按照高优先级任务的执行对象处理的顺序，使处理被设定为使用面积的数量超过所有划分区域的数量（S54〜S66）。然后，相对于设定处理选择使用区域不重叠的平面图布局（S68〜S74），并且通过对应的配置数据对可重构电路进行重新配置。版权所有（C）2009，JPO＆INPIT

9. 发明专利

JP2008035455A Image processing apparatus and program 有权
标题翻译：图像处理设备和程序
公开(公告)号：JP2008035455A
公开(公告)日：2008-02-14
申请号：JP2006209461
申请日：2006-08-01
申请人： Fuji Xerox Co Ltd , 富士ゼロックス株式会社
发明人： OKUYAMA JUNICHI
IPC分类号： H04N1/387 , G06T1/20 , G06T3/40
摘要： PROBLEM TO BE SOLVED: To provide an image processing apparatus for reducing access amounts to a memory. SOLUTION: A shared memory 18 is accessed from a CPU or an image processing part 16 through a shared bus 12. The shared memory 18 stores image data 50 in which pixel data rows generated by scanning and stretching in a main scanning direction lie in a sub scanning direction. When the image processing part 16 performs reducing processing of the image data 50, a sub scanning line extraction part 20 reads the pixel data rows by thinning out in the sub scanning direction. Then, a sub scanning interpolation part 28 interpolates in the sub scanning direction, and a main scanning interpolation part 36 interpolates in the main scanning direction to generate the reduced output image data 39. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于减少对存储器的访问量的图像处理装置。解决方案：通过共享总线12从CPU或图像处理部分16访问共享存储器18.共享存储器18存储图像数据50，其中通过扫描和拉伸在主扫描方向上产生的像素数据行为在副扫描方向。当图像处理部分16执行图像数据50的减少处理时，副扫描线提取部分20通过在副扫描方向上稀疏地读取像素数据行。然后，副扫描插补部28在副扫描方向进行插补，主扫描插补部36在主扫描方向内插，生成缩小输出图像数据39.（C）2008，JPO＆INPIT

10. 发明专利

JP2006268092A Image processor 有权
标题翻译：图像处理器
公开(公告)号：JP2006268092A
公开(公告)日：2006-10-05
申请号：JP2005081452
申请日：2005-03-22
申请人： Fuji Xerox Co Ltd , 富士ゼロックス株式会社
发明人： OKUYAMA JUNICHI , MITSUTAKE KATSUYA
IPC分类号： G06T1/20
摘要： PROBLEM TO BE SOLVED: To minimize a memory size of a hardware for executing part of image processing processes, and reducing an affect on an application by the image processing processes.
SOLUTION: An attention is focused on that a load applied on a CPU 21 is greatly lighter in polling from the CPU to a processor 22 than in interruption from the processor 22 to the CPU 21, and image processing of which a processing time by the processor 22 can be calculated is controlled by polling processing, and other processing is controlled by the interruption. Therefore, the load on the CPU 21 can be reduced.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了最小化用于执行图像处理过程的一部分的硬件的存储器大小，并且通过图像处理处理减少对应用的影响。
解决方案：关注的是，从CPU到处理器22的轮询中，从处理器22到CPU 21的中断处理中，施加在CPU 21上的负载大大降低，而处理时间可以通过轮询处理来控制处理器22的计算，并且通过中断来控制其他处理。因此，可以减少CPU 21上的负载。版权所有（C）2007，JPO＆INPIT

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