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    • 1. 发明专利
    • Apparatus for testing semiconductor, and method of testing parasitic effect of semiconductor device
    • 用于测试半导体的装置和测试半导体器件的PARASITIC效应的方法
    • JP2009168630A
    • 2009-07-30
    • JP2008007218
    • 2008-01-16
    • Fuji Electric Device Technology Co Ltd富士電機デバイステクノロジー株式会社
    • MIYAZAWA SHIGEMIFUJIHIRA TATSUHIKOKUMAGAI NAOKIHENMI TOKUYUKIISHII KENICHI
    • G01R31/26
    • PROBLEM TO BE SOLVED: To provide a semiconductor testing apparatus capable of applying stress to a power IC, while freely controlling the stress which causes parasitic effect.
      SOLUTION: An inductance current I
      L is caused to flow in an inductor 4 by applying an on-signal P1 to a G terminal of an IGBT 2 by a pulse generator 5; the inductance current I
      L is commutated to an IGBT 7 by applying an off-signal to the G terminal of the IGBT 2 by the pulse generator 5; a collector current Ic flowing in the IGBT 7 is commutated to the IGBT 2 again by applying an on-signal P2 to the G terminal of the IGBT 2 again by the pulse generator 5; and a trigger for a parasitic effect such as latchup of a firing power IC 9 or the like is generated, by making the IGBT 2 release carriers injected into the IGBT 7 during an off-period of the IGBT 2 as a reverse recovery current I
      R .
      COPYRIGHT: (C)2009,JPO&INPIT
    • 要解决的问题:提供能够对功率IC施加应力的半导体测试装置,同时自由地控制引起寄生效应的应力。 解决方案:通过脉冲发生器5将导通信号P1施加到IGBT2的G端,使电感电流I L 流入电感器4; 电感电流I L 通过脉冲发生器5向IGBT2的G端子施加截止信号而换向IGBT7; 在IGBT7中流动的集电极电流Ic再次通过脉冲发生器5向IGBT2的G端子施加导通信号P2而再次换向IGBT2; 并且通过在IGBT2的截止期间内将IGBT2释放载流子注入到IGBT7中,从而产生诸如点火功率IC9等的寄生效应的触发作为反向恢复电流I < SB> R 。 版权所有(C)2009,JPO&INPIT
    • 2. 发明专利
    • Semiconductor device for igniter
    • IGNITER的半导体器件
    • JP2007165424A
    • 2007-06-28
    • JP2005357160
    • 2005-12-12
    • Fuji Electric Device Technology Co Ltd富士電機デバイステクノロジー株式会社
    • ISHII KENICHIFUJIHIRA TATSUHIKO
    • H01L29/739H01L21/336H01L27/04H01L29/78
    • PROBLEM TO BE SOLVED: To provide a semiconductor device for use of an igniter, including low ON-voltage characteristics, low switching loss characteristics, reverse breakdown voltage characteristic required at least for an igniter circuit, and high surge voltage resistance. SOLUTION: The semiconductor device for use of the igniter includes, on a semiconductor substrate of one conductivity type, an isolation diffusion region of the other conductivity type for connecting one of principal planes of the substrate with the other principal plane, a MOS gate structure, and a pressure-resistant structure surrounding the MOS gate structure on the former principal plane surrounded by the isolation diffusion region. It includes a collector region of the second conductivity type connected at the same potential with the exposed isolation diffusion region, and a field stop layer of the first conductivity type in contact with the semiconductor substrate of the collector region on the other principal plane. COPYRIGHT: (C)2007,JPO&INPIT
    • 要解决的问题:提供一种使用点火器的半导体器件,包括低导通电压特性,低开关损耗特性,至少对于点火器电路所需的反向击穿电压特性和高耐冲击电压电阻。 解决方案:使用点火器的半导体器件包括在一种导电类型的半导体衬底上的另一导电类型的隔离扩散区域,用于将衬底的主平面之一与另一个主面连接,MOS 栅极结构,以及围绕由隔离扩散区围绕的前主体的MOS栅极结构的耐压结构。 它包括与暴露的隔离扩散区域相同的电位连接的第二导电类型的集电极区域和与另一个主平面上的集电极区域的半导体衬底接触的第一导电类型的场阻挡层。 版权所有(C)2007,JPO&INPIT
    • 4. 发明专利
    • Multichip semiconductor device and its manufacturing method
    • 多芯片半导体器件及其制造方法
    • JP2009053081A
    • 2009-03-12
    • JP2007220874
    • 2007-08-28
    • Fuji Electric Device Technology Co Ltd富士電機デバイステクノロジー株式会社
    • OE TAKASATONAKAZAWA HITOAKIIWAMIZU MORIOISHII KENICHISAITO TATSU
    • G01K7/00G01K7/01H01L25/065H01L25/07H01L25/18H02M1/00
    • H01L2224/48091H01L2924/01019H01L2924/13091H01L2924/181H01L2924/00014H01L2924/00012
    • PROBLEM TO BE SOLVED: To provide a multichip semiconductor device, and its manufacturing method, capable of reducing the range of variations in overheat detection temperatures and the range of variations in overcurrent detection values at low cost. SOLUTION: Properties (detecting voltage lines and detecting current lines) of first semiconductor chips formed in a first wafer 41, and properties (detection voltage levels and detection current levels) of second semiconductor chips formed in a second wafer 42 are grouped with respect to each class separately. This grouping is performed for regions (A, B, C) inside the first wafer 41 where the first semiconductor chips have been formed, and for regions (a, b, c) inside the second wafer 42 where the second semiconductor chips have been formed. Out of the first and second semiconductor chips grouped for the regions with respect to each class separately, chips existing in regions where variations in their chip characteristic are mutually canceled are combined with each other. COPYRIGHT: (C)2009,JPO&INPIT
    • 解决的问题:提供能够以低成本降低过热检测温度的变化范围和过电流检测值的变化范围的多芯片半导体器件及其制造方法。 解决方案:形成在第一晶片41中的第一半导体芯片的特性(检测电压线和检测电流线)以及形成在第二晶片42中的第二半导体芯片的特性(检测电压电平和检测电流电平)与 分别尊重每个班级。 对已经形成第一半导体芯片的第一晶片41内部的区域(A,B,C)进行分组,对于形成第二半导体芯片的第二晶片42内的区域(a,b,c) 。 在分别相对于每个类分配的区域的第一和第二半导体芯片中,存在于其芯片特性的变化相互抵消的区域中的芯片彼此组合。 版权所有(C)2009,JPO&INPIT
    • 5. 发明专利
    • Semiconductor integrated circuit device
    • 半导体集成电路设备
    • JP2009284420A
    • 2009-12-03
    • JP2008136868
    • 2008-05-26
    • Fuji Electric Device Technology Co Ltd富士電機デバイステクノロジー株式会社
    • TOYODA YOSHIAKIISHII KENICHIIWAMIZU MORIO
    • H03K17/56H01L21/822H01L21/8234H01L27/04H01L27/06H01L27/088H01L29/739H01L29/78H03K17/695
    • H03K17/0828H03K17/06H03K2017/066
    • PROBLEM TO BE SOLVED: To transfer the state of a power semiconductor element into an off-state by causing a semiconductor element used for pulldown to surely operate in the semiconductor integrated circuit device including the power semiconductor element. SOLUTION: A buffer circuit 29 is provided between a gate terminal of a transistor 26 used for pulldown and a threshold circuit 25 to which a gate signal is input. A voltage applied from an external battery power source 23 to an output terminal of the power semiconductor element 24 is fed to the buffer circuit 29 via a resistor element 28. A level of an on-signal output from the threshold circuit 25 is converted by the buffer circuit 29 into a higher voltage than a threshold of the transistor 26 used for pulldown and thereby even if a level of the gate signal is low, the transistor 26 used for pulldown certainly operates to turn off the power semiconductor element 24. COPYRIGHT: (C)2010,JPO&INPIT
    • 要解决的问题:通过使用于下拉的半导体元件可靠地在包括功率半导体元件的半导体集成电路器件中工作来将功率半导体元件的状态转移到断开状态。 解决方案:缓冲电路29设置在用于下拉的晶体管26的栅极端子和输入栅极信号的阈值电路25之间。 从外部电池电源23施加到电力半导体元件24的输出端子的电压经由电阻元件28被馈送到缓冲电路29.来自阈值电路25的导通信号输出电平由 缓冲电路29的电压高于用于下拉的晶体管26的阈值,因此即使栅极信号的电平低,用于下拉的晶体管26肯定操作以关闭功率半导体元件24。 版权所有(C)2010,JPO&INPIT