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1. 发明专利

JP2011211119A Wafer carrying device and wafer carrying method 有权
标题翻译：波浪携带装置和波形执行方法
公开(公告)号：JP2011211119A
公开(公告)日：2011-10-20
申请号：JP2010079874
申请日：2010-03-30
申请人： Fuji Electric Co Ltd , 富士電機株式会社
发明人： NARUSE MITSUHIRO , NAKAJIMA TSUNEHIRO
IPC分类号： H01L21/677 , B25J15/06 , B65G49/07
摘要： PROBLEM TO BE SOLVED: To provide a wafer carrying device and a wafer carrying method for carrying a wafer without forming a suction mark on nor damaging a surface of the wafer where a device is formed or is to be formed.SOLUTION: Suction holes 32 provided to step parts 24 and pluralities of holes 31 and 33 for ventilation are provided in a carrying hand 30. The step parts 24 are provided at positions which do not overlap with a device surface 2 of a rib wafer 10. The first holes 31 for ventilation are connected to the suction holes 32. The respective first holes 31 for ventilation are independent of each other. The different second holes 33 for ventilation are connected to the respective first holes 31 for ventilation. The second holes 33 for ventilation are coupled to a vacuum generation source 26 through different pipes 25 respectively. Namely, vacuum systems for the plurality of suction holes 32 are provided independently of each other. A suction state of the rib wafer 10 is determined based upon a flow velocity of air flowing in the carrying hand 30.
摘要翻译：要解决的问题：提供一种用于承载晶片的晶片承载装置和晶片承载方法，而不形成吸附标记，也不损坏形成或将要形成装置的晶片的表面。解决方案：提供吸入孔32 在步进部件24和多个用于通风的孔31和33设置有用于通风的孔31和33。台阶部件24设置在不与肋片10的装置表面2重叠的位置。用于通风的第一孔31 连接到吸孔32.用于通风的各个第一孔31彼此独立。用于通风的不同的第二孔33连接到相应的第一孔31用于通风。用于通风的第二孔33分别通过不同的管25耦合到真空产生源26。也就是说，多个吸孔32的真空系统彼此独立地设置。基于在携带手30中流动的空气的流速来确定肋片10的抽吸状态。

2. 发明专利

JP2013211402A Absorber 有权
标题翻译：吸收
公开(公告)号：JP2013211402A
公开(公告)日：2013-10-10
申请号：JP2012080407
申请日：2012-03-30
申请人： Ulvac Japan Ltd , 株式会社アルバック , Fuji Electric Co Ltd , 富士電機株式会社
发明人： HAYASAKA TOMOHIRO , NAKAJIMA TSUNEHIRO
IPC分类号： H01L21/683 , B23Q3/15 , H02N13/00
摘要： PROBLEM TO BE SOLVED: To provide an adsorber which enables a wafer to be easily removed from a stage when an electrostatic chuck is turned off and achieves high adsorption power when the electrostatic chuck is turned on without causing the deterioration and the contamination at the stage.SOLUTION: An electrostatic chuck 10 includes: a stage 11 for fixing a processed wafer 1; a protection film 12 protecting a front surface of the stage 11; conductors 21 selectively provided at the protection film 12; a conductive layer 13 generating a force fixing the processed wafer 1 to the stage 11 between the processed wafer 1 and the stage 11; a cooling part 14 cooling the processed wafer 1; and voltage wiring 15 connecting the conductive layer 13 with a voltage source 16. The conductors 21 provided on the surface of the protection film 12 are covered by an adhesive layer 22. The multiple conductors 21 are disposed on a stage 11 side surface of the protection film 12 at an equal interval in a matrix manner. In this structure, a portion of a surface of the protection film 12, which excludes a portion where the conductors 21 are provided, forms a lattice planar shape.
摘要翻译：要解决的问题：提供一种吸附器，其使得当静电卡盘关闭时能够容易地从晶片上去除晶片，并且当静电卡盘开启时不会导致劣化和污染的阶段，实现高吸附力。解决方案：静电卡盘10包括：用于固定加工晶片1的平台11; 保护台11的前表面的保护膜12; 选择性地设置在保护膜12上的导体21; 导电层13，其产生将经处理的晶片1固定到处理晶片1和台11之间的台11的力; 冷却部件14冷却经处理的晶片1; 以及将导电层13与电压源16连接的电压布线15.设置在保护膜12的表面上的导体21被粘合剂层22覆盖。多个导体21设置在保护层11的侧面11 胶片12以相等的间隔以矩阵方式。在该结构中，不包括设置有导体21的部分的保护膜12的表面的一部分形成晶格平面形状。

3. 发明专利

JP2015035461A 炭化珪素半導体装置の製造方法有权
标题翻译：硅碳化硅半导体器件制造方法
公开(公告)号：JP2015035461A
公开(公告)日：2015-02-19
申请号：JP2013164798
申请日：2013-08-08
申请人：富士電機株式会社 , Fuji Electric Co Ltd , 独立行政法人産業技術総合研究所 , National Institute Of Advanced Industrial & Technology
发明人： NAKAJIMA TSUNEHIRO , IWATANI MASANOBU , IMAI FUMIKAZU
IPC分类号： H01L21/28 , H01L21/336 , H01L29/12 , H01L29/41 , H01L29/78
CPC分类号： H01L21/0485 , H01L21/0475 , H01L21/304 , H01L21/30625 , H01L29/1608 , H01L29/45 , H01L29/66068 , H01L29/7395 , H01L29/7802
摘要：【課題】裏面電極が剥離することを抑制することができる炭化珪素半導体装置の製造方法を提供すること。【解決手段】まず、n+型SiC基板1のおもて面上にn-型SiCエピタキシャル層2を成長させる。このとき、n+型SiC基板1の裏面上にも裏面側n-型SiC蒸着層が成長される。次に、裏面側n-型SiC蒸着層およびn+型SiC基板1の裏面の表面層を研削によって除去する。次に、n+型SiC基板1の研削後の裏面の表面層に生じた変質層を化学機械研磨する。次に、n+型SiC基板1の研磨後の裏面にニッケル膜を形成する。次に、熱処理によりニッケル膜をシリサイド化してニッケルシリサイド層を形成する。次に、ニッケルシリサイド層の表面上に、チタン膜、ニッケル膜および銀膜を順に堆積して裏面電極を形成する。【選択図】図3
摘要翻译：要解决的问题：提供一种能够抑制背面电极剥离的碳化硅半导体器件的制造方法。解决方案：碳化硅半导体器件的制造方法包括以下步骤：首先在n型SiC外延层2的表面上生长n型SiC外延层2 n型SiC衬底1，其中在n型SiC衬底1的背面上生长背面侧n型SiC沉积层; 随后通过研磨去除背面侧n型SiC沉积层和n型SiC衬底1的背面的表面层; 随后对研磨后的n型SiC基板1的背面的表面层上产生的变化层进行化学机械研磨; 随后在研磨后在n型SiC衬底1的背面上形成镍膜; 随后通过热处理将镍膜硅化以形成硅化镍层; 然后依次沉积钛膜，镍膜和银膜以在硅化镍层的表面上形成背电极。

4. 发明专利

JP2011181770A Semiconductor device and method of manufacturing semiconductor device 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：JP2011181770A
公开(公告)日：2011-09-15
申请号：JP2010045740
申请日：2010-03-02
申请人： Fuji Electric Co Ltd , 富士電機株式会社
发明人： WAKIMOTO HIROKI , IGUCHI KENICHI , YOSHIKAWA ISAO , NAKAJIMA TSUNEHIRO , TANAKA SHUNSUKE , OGINO MASAAKI
IPC分类号： H01L29/739 , H01L29/06 , H01L29/78
CPC分类号： H01L21/308 , H01L21/302 , H01L21/78 , H01L29/06
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that is prevented from deteriorating in electric characteristics, and to provide a method of manufacturing the semiconductor device. SOLUTION: At a voltage blocking structure part of a reverse blocking type IGBT, a surface layer on a top side of an n-type drift region 1 is provided with a plurality of field limiting rings (FLR) 2 and a channel stopper 3. A surface layer on a reverse side of the n-type drift region 1 is provided with a p-type collector region 7. An element end part is provided with a p + -type isolation layer 11 for obtaining a voltage blocking capability. Further, a recess part 6 is provided which reaches the p + -type isolation layer 11 from the reverse side of the n-type drift region 1. A surface layer on a side wall and a bottom surface of the recess 6 is provided with a p-type region 8, and the p + -type isolation layer 11 and p-type collector region 7 are electrically connected. Further, the p + -type isolation layer 11 is in contact with the channel stopper 3. Furthermore, the p + -type isolation layer 11 is provided including a cleavage surface 21 having one side at a boundary 20 between the bottom surface and side wall of the recess part 6. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种防止电特性恶化的半导体器件，并提供一种半导体器件的制造方法。解决方案：在反向阻挡型IGBT的电压阻挡结构部分，n型漂移区1的上侧的表面层设置有多个场限制环（FLR）2和沟道阻塞在n型漂移区域1的背面上的表面层设置有p型集电区域7.元件端部设置有用于获得电压阻断能力。此外，设置从n型漂移区域1的反面到达p + SP>型隔离层11的凹部6。在侧壁和底面的表面层凹部6设置有p型区域8，并且p + SP型隔离层11和p型集电极区域7电连接。此外，p + 型隔离层11与通道阻挡件3接触。此外，提供了p

5. 发明专利

JPS6353257A VAPOR DEPOSITING METHOD FOR SEMICONDUCTOR WAFER 失效
公开(公告)号：JPS6353257A
公开(公告)日：1988-03-07
申请号：JP19656286
申请日：1986-08-22
申请人： FUJI ELECTRIC CO LTD
发明人： NISHIZAWA SHIGERU , NAKAJIMA TSUNEHIRO
IPC分类号： C23C14/24 , C23C14/50
摘要： PURPOSE:To uniformly form a relatively thick vapor deposited film in the step parts and rugged parts of wafers as well by specifying the opening angle of a wafer holder and the angle at which the perpendicular center line of the circular conical shape of the wafer holder and the perpendicular running the center of a vapor deposition source intersect with each other. CONSTITUTION:The wafer holder 1 is formed to the circular conical shape having 130-150 deg. opening angle and within 500mm diameter at the time of depositing the Al film, etc., by evaporation on the semiconductor wafers 2 by using a planetary type vacuum deposition device. The vertex of the holder 1 is fixed to 300mm position horizontally from the center of the vapor deposition source and 590mm position perpendicularly therefrom. The wafer holder 1 is so inclined as to attain 48-50 deg. angle at which the perpendicular center line of the circular conical shape of said holder and the perpendicular running the center of the vapor deposition source 3 intersect with each other. The relatively thick vapor deposited Al matter of about 5mum is formed and the good vapor deposited film is formed even in the step parts or rugged parts if the vapor deposition is executed by rotating the wafer holder in this state.

6. 发明专利

JPH0582508A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0582508A
公开(公告)日：1993-04-02
申请号：JP24388191
申请日：1991-09-25
申请人： FUJI ELECTRIC CO LTD
发明人： NAKAJIMA TSUNEHIRO
IPC分类号： H01L21/283 , H01L21/31 , H01L21/318
摘要： PURPOSE:To prevent deterioration of device characteristics by the moisture intruding through cracks in the passivation film covering the electrode on a semiconductor device. CONSTITUTION:After formation of an electrode 4, the whole surface is covered by a film of the same material as that of a passiviation film 3, and a passivation film 3 is formed on the smooth-tapered surface, a side-wall layer 5, with which the overhung generated on the side wall can be filled up, is left on the side face of an anisotropic etching electrode, and then a passivation film 3 is formed on the surface having a smooth face. As a result, the step coverage of the passivation film 3 is improved, and cracks can be prevented.

7. 发明专利

JPH04348527A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH04348527A
公开(公告)日：1992-12-03
申请号：JP12052591
申请日：1991-05-27
申请人： FUJI ELECTRIC CO LTD
发明人： NAKAJIMA TSUNEHIRO
IPC分类号： H01L21/22 , H01L21/225 , H01L21/265 , H01L21/322 , H01L21/336 , H01L29/78
摘要： PURPOSE:To settle problems that the amount of leak current increases when the amount of Au diffusion is increased and variation in characteristics is caused when the amount of Pt diffusion is increased for the sake of lifetime control, an irradiation effect is diminished when the annealing after irradiation of a particle beam is carried out at high temperature and the characteristic varies when the annealing is carried out at low temperature. CONSTITUTION:The life is controlled through heavy metal diffusion together with irradiation of a particle beam so that a desirable switching speed is obtained. By using Pt as heavy metal, the leak current is diminished at the amount of diffusion is reduced so that the variation in characteristics can be controlled. Through the heavy metal diffusion, the life can be reduced to a certain extent, and thereby the annealing temperature can be raised after irradiation with an electron beam and the like. Consequently, the deterioration of characteristics can be prevented in fabrication or reliability test processes.

8. 发明专利

JP2551162B2 失效
公开(公告)号：JP2551162B2
公开(公告)日：1996-11-06
申请号：JP21564689
申请日：1989-08-22
申请人： FUJI ELECTRIC CO LTD
发明人： NAKAJIMA TSUNEHIRO
IPC分类号： H01L29/78 , H01L27/04

9. 发明专利

JPH04212468A HIGH BREAKDOWN STRENGTH SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH04212468A
公开(公告)日：1992-08-04
申请号：JP1813091
申请日：1991-02-12
申请人： FUJI ELECTRIC CO LTD
发明人： NAKAJIMA TSUNEHIRO
IPC分类号： H01L27/04 , H01L21/331 , H01L21/822 , H01L29/06 , H01L29/40 , H01L29/73 , H01L29/732 , H01L29/78
摘要： PURPOSE:To avoid the decline in the breakdown strength due to the bent stretch of a depletion layer by the charge induced to a field plate within the title high breakdown strength semiconductor device provided with a guard ring and the field plate. CONSTITUTION:A field plate 8 is covered with a low resistant film 21 in the seat resistance of 10 -10 so as to relieve the charge induced to the field plate 8 to a main electrode by the low resistant film 21. At this time, the danger of cracking due to the downward stress upon the low resistant film 21 can be avoided by laminating a stress absorbable insulating film 22 on the film 21. Through these procedures, as for the low resistant film 21, a silicon nitride film to be formed by adjusting the specific resistance using plasma CVD process can be used effectively.

10. 发明专利

JPH02155276A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH02155276A
公开(公告)日：1990-06-14
申请号：JP30918088
申请日：1988-12-07
申请人： FUJI ELECTRIC CO LTD
发明人： NAKAJIMA TSUNEHIRO
IPC分类号： H01L29/06 , H01L29/78
摘要： PURPOSE:To reduce a resistance between two main electrodes and to improve breakdown strength by extending a depletion layer due to a voltage applied between both the electrodes to a guard ring part by setting a first conductivity type high impurity concentration only to the surface layer of a region interposed between channel layers of the region exposed on one side surface of original part of a semiconductor substrate. CONSTITUTION:With an SiO2 film 10 as a mask a source electrode contact p type layer 3 and a guard ring p type layer 4 are formed by implanting boron ions. Then, the SiO2 film 10 on the surface between the guard ring layers 4 remains, the SiO2 film on a MOS structure is removed, and an N-type high impurity concentration layer 2 is formed by implanting phosphorus ions. Accordingly, the N-type layer 2 is not formed between the guard rings 4. Thereafter, a new mask is provided, a p-type channel layer 5 and a source layer 6 are formed in a substrate, and a gate electrode 7 is provided on the substrate through a gate oxide film. Thus, when a voltage is applied between the drain electrode and the source electrode, the extension of the surface of a depleted layer is not disturbed, and the function of the guard ring is performed irrespective of the concentration of the surface layer between the channel layers to improve its breakdown strength.

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