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    • 1. 发明专利
    • Semiconductor device
    • 半导体器件
    • JP2003338624A
    • 2003-11-28
    • JP2002145902
    • 2002-05-21
    • Fuji Electric Co LtdNatl Space Development Agency Of Japan宇宙開発事業団富士電機株式会社
    • TAGAMI SABUROKOBAYASHI TAKASHIKIRIHATA FUMIAKIKUBOYAMA TOMOJI
    • H01L29/08H01L29/739H01L29/78
    • H01L29/7816H01L29/0847H01L29/0878H01L29/7802H01L29/7813
    • PROBLEM TO BE SOLVED: To provide a power MOSFET (metal oxide semiconductor field-effect transistor) having sufficient SEB (single event burnout) resistance used for space. SOLUTION: A second N base layer 3 and a first N - base layer 22 are epitaxially grown on a N + drain layer 21 successively, a P base region 23 is selectively formed on its surface, and a N + source region 24 is selectively formed on a surface in it. A gate electrode 26 is formed through a gate dielectric film 25 on a channel region, and a source electrode 27 is formed. A drain electrode 28 is formed on the back of a substrate. The thickness d2 of the second N base layer 3 is not less than 1/2 of a difference between the thickness d1 of the first N - base layer 22 and the thickness shown in VSEB(V)=8x (μm), and a mean impurity concentration is not less than 1×10 15 /cm 3 and not more than 3×10 17 /cm 3 , thereby positive feedback between latch-up in a parasitic npn transistor and a dynamic avalanche near the substrate is hard to break out and SEB resistance is improved. COPYRIGHT: (C)2004,JPO
    • 要解决的问题:提供具有足够的用于空间的SEB(单事件烧尽)电阻的功率MOSFET(金属氧化物半导体场效应晶体管)。 解决方案:第二N基极层3和第一N - / SP>基极层22依次在N + SP +漏极层21上外延生长,P基极区域23 在其表面上选择性地形成,并且在其表面上选择性地形成N + 源极区24。 栅电极26通过沟道区上的栅极电介质膜25形成,形成源电极27。 漏极电极28形成在衬底的背面。 第二N基层3的厚度d2不小于第一N - / SP>基层22的厚度d1和VSEB(V)= 8x所示的厚度之差的1/2 (μm),平均杂质浓度为1×10 3 / SP 3以上3×10 3 / cm 3,因此寄生npn晶体管的闭锁与基板附近的动态雪崩之间的正反馈难以突破,并且提高了SEB电阻。 版权所有(C)2004,JPO
    • 2. 发明专利
    • GATE TURN-OFF THYRISTOR
    • JPH01171272A
    • 1989-07-06
    • JP32914287
    • 1987-12-25
    • FUJI ELECTRIC CO LTD
    • TAGAMI SABURO
    • H01L29/74H01L29/08H01L29/744
    • PURPOSE:To inject electrons fed from a cathode electrode to a P emitter layer in a quantity larger than others, and to improve gate trigger sensibility by making the number of N-type short-circuit layers penetrating the P emitter layer smaller than that of cathode segments. CONSTITUTION:The number of short-circuit layers 22 short-circuiting an N buffer layer 21 and an N base layer 2 with an anode electrode 5, penetrating a P emitter layer 1 is half the number of cathode segments 4, 6. Consequently, distances among the short-circuit layers 22 are brought to twice as long as distances among the cathode segments. When impurity concentration in the buffer layer 21 is kept constant, R increases in proportional to distances among the short-circuit layers 22; when the number of the short-circuit layers is made smaller than that of the cathode segments, distances among the short-circuit layers are lengthened and gate trigger currents can be reduced. As a result, electron currents flowing into the short-circuit layers form the buffer layer are limited by making the number of the short-circuit layers smaller than that of the cathode segments, and injected to the P emitter layer. Accordingly, turn- off loss is reduced, and gate trigger sensibility is improved.
    • 3. 发明专利
    • BIDIRECTIONAL SEMICONDUCTOR SWITCHING ELEMENT
    • JPH07297384A
    • 1995-11-10
    • JP8354494
    • 1994-04-22
    • FUJI ELECTRIC CO LTD
    • TAGAMI SABURO
    • H01L29/747H01L29/861
    • PURPOSE:To improve a surge breakdown resistance amount of a bidirectional semiconductor switching element for a surge absorber, which includes five layers of p-n-p-n-p and two main electrodes that short-circuit two outermost p-type and n-type layers on respectively. CONSTITUTION:A high-resistance region 14 is provided by forming a p-type diffusion region 11 deeper than a first (p) layer 1 in the part of a first (n) layer 2 on the first (p) layer 1 being near to the side whereon the first (n) layer 2 is short-circuited by a main electrode 10, or other means. A potential drop in the high-resistance region 14 by a current of an n-p-n transistor 12 is made large, a potential distribution in the first (n) layer 2 just above the first (p) layer 1 is made uniform relatively, a current density distribution at the time of a thyristor 13 being continuous is made uniform and a surge breakdown resistance amount is improved. A method wherein the concentration of an impurity of an acceptor type of the first (p) layer 1 is made higher with separation from the electrode short-circuited part of the first (n) layer 2 is also advisable. A built-in potential difference in the part wherein the impurity concentration is high is large and the current density distribution at the time of the thyristor 13 being continuous is uniform.
    • 5. 发明专利
    • VERTICAL TYPE MOSFET
    • JPS63128757A
    • 1988-06-01
    • JP27564386
    • 1986-11-19
    • FUJI ELECTRIC CO LTD
    • TAGAMI SABURO
    • H01L29/10H01L29/78
    • PURPOSE:To enhance the L-load resisting capacity by a method wherein a first region of high impurity-concentration, a second region of low impurity- concentration, of a first conductivity type, a third region of a second conductivity type and a fourth region, of the first conductivity type, formed selectively on the surface of the third region are piled up while a drain electrode comes into contact with the first region, a source electrode comes into contact with the third region and the fourth region and a gate electrode is formed on the surface of the third region via an insulating film with a view to specifying the thickness of the third region. CONSTITUTION:The thickness of a p-layer 3 is to be 3-8mum. If the thickness of a third region is made thick, its sheet resistance is reduced, and an L-load circuit is connected between a source and a drain of a vertical type MOSFET; it is possible to reduce a voltage drop in the third region by an electric current based on an electron-hole pair generated at the time when a reverse-bias junction between a p-layer and an n layer causes an avalanche; as a result, the breakdown of a device can be prevented.
    • 7. 发明专利
    • BIDIRECTIONAL SWITCHING ELEMENT
    • JPH01183849A
    • 1989-07-21
    • JP894688
    • 1988-01-19
    • FUJI ELECTRIC CO LTD
    • TAGAMI SABURO
    • H01L29/74H01L29/747H01L29/861
    • PURPOSE:To obtain an element having small electrostatic capacitance without changing voltage for bringing to a conductive state by making the trigger of a thyristor com posed of some four layer of a bi-directional switching element depend upon the punch- through currents of the central three layers without depending upon avalanche break down. CONSTITUTION:When fixed voltage is applied between main electrodes 61, 62, a punch- through is generated, and second-fourth layers 2-4 forming a transistor section introducing a thyristor consisting of a first - or fifth layer 1, 5 to a conductive state are shaped. When impurity concentration in the third layer 3 in the five layers lowers, a depletion layer is easy to spread, the depletion layer reaches the next junction, punch-through currents begins to flow, and a thyristor made up of the four layers is triggered when the currents reach latching currents or more. Since the magnitude of applied voltage at that time is determined by impurity concentration in the third layer 3 and the width of the third layer 3, impurity concentration can be altered by varying the width of the third layer 3 even when the thyristor is conducted by the same applied voltage, thus adjusting electrostatic capacitance. Accordingly, the relationship of a trade-off between electrostatic capacitance and operating voltage is released, thus acquiring an element having small electrostatic capacitance.
    • 8. 发明专利
    • BIDIRECTIONAL SEMICONDUCTOR SWITCHING ELEMENT
    • JPH01171273A
    • 1989-07-06
    • JP32914387
    • 1987-12-25
    • FUJI ELECTRIC CO LTD
    • TAGAMI SABURO
    • H01L29/74H01L29/747H01L29/861H01L29/87
    • PURPOSE:To set a holding current to an arbitrary value by dividing second and fourth layers in contact with a common electrode into a plurality of regions which penetrate first and fifth layers, and dividing second and fourth layers in contact with the common electrode of a switching element having five adjacent layers of alternately different conductivity types into a plurality of regions which penetrate first and fifth layers. CONSTITUTION:A plurality of regions of first and second base layers 2, 3 are respectively brought into contact with electrodes 61, 61 in short holes which penetrates first and second emitter layers 4, 5. Since an electron current 18 is divided to both sides right under the P-type emitter layer 4 to arrive at the contact region 9, a potential drop of resistance rho/1 of the half of the whole sheet resistance rho right under the layer 4 merely occurs. Accordingly, a holding current IM can be set to a predetermined value or more without reducing the total area of the electrode 61 or 62, i.e., without reducing the capacitance.
    • 9. 发明专利
    • INSULATED-GATE BIPOLAR TRANSISTOR
    • JPS6381862A
    • 1988-04-12
    • JP22687186
    • 1986-09-25
    • FUJI ELECTRIC CO LTD
    • TAGAMI SABURO
    • H01L29/68H01L29/10H01L29/739H01L29/78
    • PURPOSE:To prevent ratching without increasing gate threshold voltage by providing a high impurity concentration region which is the same conductivity type to a collector region in the collector region directly under a source region. CONSTITUTION:The low impurity concentration and a conductivity type, n type, second region (drain or source region) (base region) 2 is provided on the first region (emitter region) 1 made of a p -type substrate and the p-type third region (collector region) 3 is selectively formed on the surface of the second region 2. Further, the high impurity concentration n -type fourth region (source region) 4 is selectively formed on the surface of the third region 3. A gate electrode 6 is provided on the fourth region 4 by interposing an insulating film 5 (gate insulating film). A collector electrode 7, an emitter electrode 8 and a p-type high impurity concentration layer 9 are also provided. A high impurity concentration region 10 which is the same conductivity type to the third region 3 is formed directly under the fourth region 4 in the third region 3 by such a method as to implant a high energy p-type ion by using the insulating film 5 which is used for forming the fourth region 4 as a mask before the gate electrode 6 and the collector electrode 7 are provided.
    • 10. 发明专利
    • SEMICONDUCTOR DEVICE
    • JPS6262557A
    • 1987-03-19
    • JP20205485
    • 1985-09-12
    • FUJI ELECTRIC CO LTD
    • HASHIMOTO OSAMUKIRIHATA FUMIAKITAGAMI SABURO
    • H01L29/744H01L29/167H01L29/74
    • PURPOSE:To readily electrically insulate between an n-type emitter and a p-type base by selectively implanting life time killer such as gold or platinum directly under the center of a segment to shorten the carrier lifetime directly under the center of the segment, and alleviating the current concentration at turning OFF time. CONSTITUTION:A window 12 of an oxide film is opened by photoetching an oxide film at the center of a rectangular n-type emitter 4, and life time killer such as gold or platinum is thermally diffused in high density through the window 12. In order to implant tthe killer from a p-type emitter 7 side, the oxide film of the emitter 7 is removed, and the gold or platinum is again implanted to optimize the turning OFF time or tail current of a GTO thyristor. The second implanting amount is sufficiently reduced as compared with the first implanting amount from the emitter 4 side. The lives of carriers are largely differentiated between the region 12 directly under the center of a rectangular cathode electrode and a region except the region 12 by differentiating the first and second killer implanting amounts.