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1. 发明专利

JPS5636734A ACTUATION PROCESSING CONTROL SYSTEM OF COMMUNICATION CONTROLLER 失效
公开(公告)号：JPS5636734A
公开(公告)日：1981-04-10
申请号：JP11214779
申请日：1979-08-31
申请人： FUJITSU LTD , PANA FACOM KK
发明人： DOI YASUO , MASUDA TOMIO , ODAKAWA TOSHIYUKI
IPC分类号： H04L29/04 , G06F13/00 , H04L13/00
摘要： PURPOSE:To evade the occurrence of a word omission, etc., by freely stopping and restarting the counting of a scanning counter, which scans interrupting actuation information, by a program. CONSTITUTION:Scanning counter 7 counts up with the output of AND circuit 13 and subchannels 6-0-6-n are accessed sequentially to set the contents in register 10. Actuation information A0, when residing in register 10, is detected by detecting circuit 11 and program control part 3 is informed of that. Subsequently, flip-flop 12 is set and AND circuits 13 and 14 turn off, inhibiting scanning counter 7 from counting up. Further, the scanning stop display signal of program control part 3 also turns off AND circuits 13 and 14. During this period, the program performs processing such as actuation that corresponds to circuit #0 and data transfer of a random circuit.

2. 发明专利

JPS63314663A SWITCH CONTROL SYSTEM FOR INPUT/OUTPUT DEVICE 失效
公开(公告)号：JPS63314663A
公开(公告)日：1988-12-22
申请号：JP15074987
申请日：1987-06-17
申请人： FUJITSU LTD
发明人： HOSHI FUMIO , DOI YASUO , MOTOMURA NOBUFUMI , TAKENO TADAYUKI , TAKAHATA SHOJI , HORI YOICHI
IPC分类号： G06F13/12
摘要： PURPOSE:To simply perform a switching job of input/output devices at a high speed by applying the switch control to the connecting state between a channel device and a channel connecting part based on the switch information and the non-communication state information regardless of the presence or absence of the data or a status to be transferred. CONSTITUTION:A switch informing part 4 delivers the switch information to indicate a valid or invalid state of a path between a channel connecting part 2 and a channel device 1. A channel interface control part 5 delivers the non- communication state information showing that the data or a status is not under a transfer state regardless of the presence or absence of the data or the status to be transferred. Then a switch control part 6 switches a path between the part 2 and the device 1 to an invalid state from a valid state and vice versa based on the switch information and the non-communication state information. Thus the switching action is carried out quickly. At the same time, it is possible to perform a switching action between an input/output device and a host computer an also to load a program to the input/output device from the host computer with high efficiency.

3. 发明专利

JPS61296842A LINE CONTROL SYSTEM 失效
公开(公告)号：JPS61296842A
公开(公告)日：1986-12-27
申请号：JP13831885
申请日：1985-06-25
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： GOHARA MASAO , DOI YASUO , SHOJI TOSHIO
IPC分类号： H04L29/10 , G06F13/00 , H04L13/00
摘要： PURPOSE:To eliminate the need for address replacement and to attain flexible accommodation of a line by applying split processing to a character processing of the line of a control means which requires the time for processing due to a low communication speed over plural numbers of line scannings. CONSTITUTION:Plural lines having different communication speeds and control means are connected, the character is assembled disassembled and a character processing request is generated. In a line controller having a common control circuit section 4 performing various control operations such as character read/ write, when the 1st means 16 detects a request that it is a character processing request from the line of communication speed and control procedure, based on the content of the 2nd means 14, after a part of processing among required processings of characters is executed, the state of character processing is updated and stored in the 2nd means. In the scanning of the line, one character processing is subjected to split processing over plural numbers of scanning periods by executing one by one partial processing split at each each scanning.

4. 发明专利

JPS61260743A COMMUNICATION CONTROL EQUIPMENT 失效
公开(公告)号：JPS61260743A
公开(公告)日：1986-11-18
申请号：JP10201285
申请日：1985-05-14
申请人： FUJITSU LTD
发明人： NAKAJIMA TOSHIKI , DOI YASUO , OGASAWARA SHIGERU , GOHARA MASAO
IPC分类号： H04L29/02 , G06F13/00 , H04L13/00
摘要： PURPOSE:To improve the utilizing efficiency of a communication line by providing a transmission queue between a line control section and a line adaptor and using transmission operation indication information stored in the transmission queue and the information representing the state of the transmission queue so as to control the transmission operation by the transmission queue. CONSTITUTION:The transmission queue SQ is provided between the line control section 4 and a line adaptor 5 and the transmission operation indication information is stored in the transmission queue together with a transmission data information. The transmission operation is subject to execute control when the data of a prescribed number or over exists in the transmission queue by using the transmission operation indication information and the information representing the state of the transmission queue. Thus, the generation of under run error due to the temporary processing delay of the line control section is prevented and the transmission stop period between texts is reduced so as to improve the utilizing efficiency of the communication line.

5. 发明专利

JPS6169239A Circuit control system 失效
标题翻译：电路控制系统
公开(公告)号：JPS6169239A
公开(公告)日：1986-04-09
申请号：JP19082884
申请日：1984-09-12
申请人： Fujitsu Ltd
发明人： DOI YASUO
IPC分类号： H04L29/04 , H04L13/00
CPC分类号： H04L13/00
摘要： PURPOSE:To omit a circuit scan mechanism and to store successively the circuit adaptor parts regardless of the communication speed, by using a means which informs the processing request given from the circuit adaptor side and the packing circuit number storing an adaptor to a circuit processing part. CONSTITUTION:A circuit adaptor 2 stores a data transmission circuit 1 and processes the bit or character level through a processing part 9. These adaptors are loaded to a device for each stored circuit and in the order of #1-@{/32}n. A circuit processing part 4 processes the character or block level and usually recognizes the adaptor 2 of a communication circuit by the circuit number information 6 in case either one of processing request signals 7A-7N (speed increased in the order of A-N) set for each communication speed. Then the data are transferred between the part 4 and the adaptor 2 via an information bus 5.
摘要翻译：目的：省略电路扫描机制，并连续存储电路适配器部件，无论通信速度如何，通过使用通知电路适配器侧给出的处理请求的装置和将适配器存储到电路处理部分的打包电路号。构成：电路适配器2存储数据传输电路1，并通过处理部分9处理位或字符电平。这些适配器被加载到每个存储的电路的装置中，并按照＃1〜@ {/ 32} n 。电路处理部分4处理字符或块级别，并且通过电路号码信息6来识别通信电路的适配器2，以处理请求信号7A-7N（以AN的顺序增加的速度）为每个处理请求信号设置通讯速度然后，数据通过信息总线5在部分4和适配器2之间传送。

6. 发明专利

JPS6061852A COLLATION SYSTEM FOR WRITE DATA 失效
公开(公告)号：JPS6061852A
公开(公告)日：1985-04-09
申请号：JP16858483
申请日：1983-09-13
申请人： FUJITSU LTD
发明人： DOI YASUO
IPC分类号： G06F13/14 , G06F12/16 , G06F13/16
摘要： PURPOSE:To perform simultaneous parallel writing and reading to and from all selected decentralized control parts and perform comparative collation by providing a means which selects optionally decentralized control parts which is an object where data is to be written in common. CONSTITUTION:Microprogram writing and reading, and collation are performed simultaneously through a data bus 3a, address bus 3b, and control bus 3c from a main controller CC1a as to bit-corresponding decentralized processing part CS set in a register 11 among decentralized controllers CSs 4a-4m. The controller CC1a reads a corresponding microprogram out of a main storage device MM2a, and sends it out to the data bus 3a, word by word, to send an address signal to the address bus 3b and a write command to the control bus 3c. Memory control circuits 42 of CSs 4a-4m selected by the register 11 are enabled and select addresses of storage circuits 43 to write the microprogram.

7. 发明专利

JPS56110169A MULTIPROCESSOR PROCESSING SYSTEM 失效
公开(公告)号：JPS56110169A
公开(公告)日：1981-09-01
申请号：JP1328180
申请日：1980-02-06
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD
发明人： NAKAMURA TAKASHI , DOI YASUO , SHIMOMURA FUMIO , HIRAIDE TOSHIHIKO , NAGAFUKU KATSUTERU
IPC分类号： H03M9/00 , G06F5/06 , G06F13/00 , G06F13/38 , G06F15/16 , G06F15/167
摘要： PURPOSE:To improve processing capacity by providing first-in first-out register groups storing data of predefined fixed lengths between respectively independent processors, and accumulating the processing requests between the processors into the register groups. CONSTITUTION:Plural processors PA, PB and storages MEM-A, MEM-B are connected to system buses BUS-A, BUS-B, whereby the multiprocessor processing system is constituted. First-in first-out register groups FIFO-1, FIFO-2 are connected via an interrupt control circuit INTC between these processors PA and PB, and the respective register groups FIFO-1, FIFO-2 are connected to the BUS-A, BUS-B. The processing requests from the respective processor PA or PB are written in the register group FIFO-1 or FIFO-2, and the respective processing requests are detected through the control circuit INTC, thereafter the contents of the processing requests are read into the processor PB or PA on the other side, whereby the processing capacity is improved.

8. 发明专利

JPS5557947A REGISTER CONTROL SYSTEM 失效
公开(公告)号：JPS5557947A
公开(公告)日：1980-04-30
申请号：JP7817678
申请日：1978-06-28
申请人： FUJITSU LTD
发明人： DOI YASUO , HIHARA SEIJI , TAKAHASHI HIROSHI , NAKAHARA YASUHIRO , NAKAMURA TAKASHI
IPC分类号： G06F7/00 , G06F9/34
摘要： PURPOSE:To make it possible to relieve a burden upon a program by storing several pieces of control information in external registers of a microprocessor, etc., by providing a control bits to every control information, and by assigning the availability of control information in accordance with its contents. CONSTITUTION:Pieces of control information A, B and C are stored in FFA1..., FFB1..., FFC1... constituting external register OREG, and one-bit control bits CNTA, CNTB and CNTC are provided to head parts of respective pieces of control information. Now, an instruction which changes information A among contents of resister OREG into A' and control information A' are inputted from CPU to microprocessor mupu. From mupu, ''1'' and ''0'' are supplied to signal lines CNTA, and CNTB and CNTC, and information A' is supplied to data lines DB1-DB6 in parallel. Only when the signal line is ''1'', a clock pulse is supplied to FF of an external register and FFA1 and FFA2 has CNTA of ''1'', so that while control information A is changed into A', the others will maintain their initial states. Consequently, a burden on a program and the number of addresses can both be reduced.

9. 发明专利

JPS6252335B2 失效
公开(公告)号：JPS6252335B2
公开(公告)日：1987-11-05
申请号：JP15910582
申请日：1982-09-13
申请人： FUJITSU LTD
发明人： DOI YASUO , NAKAJIMA TOSHIKI , SHIBATA HIROKI
IPC分类号： G06F11/28 , G06F11/22

10. 发明专利

JPS61294570A CHANNEL DEVICE 失效
公开(公告)号：JPS61294570A
公开(公告)日：1986-12-25
申请号：JP13739785
申请日：1985-06-24
申请人： FUJITSU LTD
发明人： SHIBATA HIROKI , DOI YASUO
IPC分类号： G06F13/38 , G06F13/12
摘要： PURPOSE:To obtain a highly efficient channel device which is free from an overrun (underrun) produced between an input/output controller IOC and a channel CH, by deciding the suppress conditions of data according to the contents of a data transfer mode table for IOC. CONSTITUTION:An IOC data transfer mode table 10 contains the proper transfer mode information on all IOC. This mode information includes a constant which is set small with an IOC of a responseconfirmation system and large with an IOC of a non-response confirmation system respectively. In a data transfer mode the CH reads out the constant from the table 10 corresponding to the IOC which is under execution. A comparator 11 compares said constant with the buffer idle space received from a buffer control part. Then a data suppress indication is given to an input/output interface control part if the buffer idle space is equal to or smaller than the constant.

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