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1. 发明专利

JPS60257489A DISPLAY CONTROLLER 失效
公开(公告)号：JPS60257489A
公开(公告)日：1985-12-19
申请号：JP11342084
申请日：1984-06-01
申请人： PANA FACOM KK
发明人： MAEDA SHIN , ISOGAWA TAKAO , ICHIKAWA TOSHIKI
IPC分类号： G09G5/377 , G06F3/048 , G06F3/14 , G09G1/06 , G09G5/14 , G09G5/36

2. 发明专利

JPS60254081A DISPLAY CONTROLLER 失效
公开(公告)号：JPS60254081A
公开(公告)日：1985-12-14
申请号：JP10982584
申请日：1984-05-30
申请人： PANA FACOM KK
发明人： ISOGAWA TAKAO , HASHIMOTO YOUJI , MATSUNUMA NAOKI
IPC分类号： G09G5/36 , G09G1/02 , G09G1/06 , G09G5/18

3. 发明专利

JPS60207945A DATA TRANSFER CONTROL SYSTEM 失效
公开(公告)号：JPS60207945A
公开(公告)日：1985-10-19
申请号：JP6487084
申请日：1984-03-30
申请人： PANA FACOM KK
发明人： YOSHIYA YUKIHIRO
IPC分类号： G11C7/00 , G06F13/28 , G06F13/38 , G06F15/167
摘要： PURPOSE:To decide the final output data at a high speed with the small number of hardwares by deciding the end of data transfer on the basis of a flag in case of using a first in first out type buffer. CONSTITUTION:When data transfer for the prescribed volume of transfer data from a data transmission device 1 is ended, a decoder circuit 22 detects that the contents of an input number counter 5 is ''0'' and sends information ''1'' to a flag holding area 21 in a data buffer 3 and a read/write control circuit 4 writes the flag information ''1'' in the data buffer 3 together with the final transfer data. The output side of the data buffer 3 decides the data read out together with the flag information as the final data when the flag information 1 is read out from the flag holding area 21 in the reading process of the data, and a data end signal line 8 is turned to ''1''.

4. 发明专利

JPS6066392A REFRESH SYSTEM OF DYNAMIC STORAGE DEVICE 失效
公开(公告)号：JPS6066392A
公开(公告)日：1985-04-16
申请号：JP17354083
申请日：1983-09-20
申请人： PANA FACOM KK
发明人： MASUDA TSUGIO , GOTOU TOSHIO
IPC分类号： G11C11/406 , G11C11/34
摘要： PURPOSE:To reduce current required for refresh by refreshing a selected storage area successively. CONSTITUTION:Prescribed high order bits of an address outputted from a refresh address counter 2 are decoded by a decoder 4 and divided storage areas ARY1-ARY4 in a dynamic RAM3 are successively selected through corresponding NAND gates 5-8 and refreshed in each storage area each storage areas ARY1-ARY4. Said constitution makes it possible to reduce current required for refresh, stabilize a power supply system, reduce and prevent a noise margin, and make its design easy.

5. 发明专利

JPS6045972A DISC CONTROL SYSTEM 失效
公开(公告)号：JPS6045972A
公开(公告)日：1985-03-12
申请号：JP15362683
申请日：1983-08-23
申请人： PANA FACOM KK
发明人： NAKA KENICHI , WADA SEIJI
IPC分类号： G11B19/00 , G11B19/12 , G11B27/00
摘要： PURPOSE:To control disc devices having different discs by writing device identification data in a specific record of a disc storing medium. CONSTITUTION:The device identification data (He, Cy, Seek) are previously written in a cylinder (Cy)0, a head (He)0, a record (Sec)0 of each unit 2 and its diagonal line. When an electric power supply is turned on in a system, the units 2 are automatically seeked to tracks ''0''. The unit 2 having no automatic seeking is seeked by a disc controller 1. The seeking speed of respective units 2 is uniform. The controller 1 reads identification data of the basis of a sense command from a CPU, stores the data in a register 11 in each unit 2 and reports the data to the CPU. The identification data stored in the controller 1 is referred every transmission of a command to control each unit 2 in accordance with an operation sequence.

6. 发明专利

JPS59206878A Access control system for graphic memory 失效
标题翻译：图形存储器的访问控制系统
公开(公告)号：JPS59206878A
公开(公告)日：1984-11-22
申请号：JP8134183
申请日：1983-05-10
申请人： Pana Facom Kk
发明人： OGAWA SHINJI , YAMAMOTO YOUJI
IPC分类号： G09G5/00 , G06F12/00 , G06F12/06 , G06F13/00 , G06T11/00 , G09G1/02 , G09G5/32 , G09G5/39

7. 发明专利

JPS59124376A Data transducer 失效
标题翻译：数据传输器
公开(公告)号：JPS59124376A
公开(公告)日：1984-07-18
申请号：JP23417782
申请日：1982-12-30
申请人： Pana Facom Kk
发明人： YAMAGUCHI TAHEI
IPC分类号： G06F3/153 , G06F3/14 , G09G1/02 , G09G1/06 , G09G5/36

8. 发明专利

JPS58169660A FORMING METHOD OF MULTI-PROCESSOR SYSTEM 失效
公开(公告)号：JPS58169660A
公开(公告)日：1983-10-06
申请号：JP5290282
申请日：1982-03-31
申请人： PANA FACOM KK
发明人： SATOU AKIRA , ASAJI YOSHIO , MARUOKA HIROSHI
IPC分类号： G06F13/36 , G06F9/38 , G06F15/16 , G06F15/173 , G06F15/177
摘要： PURPOSE:To improve the processing capability of a multi-processor system while saving the quantity of both hardware and software, by providing the function of interruption of many differences, the IOC control and the bus control respectively only to a main processor when different types of microprocessors are combined. CONSTITUTION:Plural microprocessors 11, 11a..., memories 13, 13a... and input/ output controllers (IOC) 12, 12a... are connected to common buses 20a-20c. A main processor 11 has the functions of the interruption control, the IOC control and the bus control respectively and controls option processors 11a..., memories 11a... and IOC12, 12a... respectively. The option processors 11a... control the memories 13a... with a command of the processor 11 and at the same time gives the interruption control to the processor 11 to give a request of control to the processor 11 for the IOC12a....

9. 发明专利

JPS57113147A COMPILING SYSTEM FOR INCORPORATED INSTRUCTION 失效
公开(公告)号：JPS57113147A
公开(公告)日：1982-07-14
申请号：JP18575080
申请日：1980-12-31
申请人： FUJITSU LTD , PANA FACOM KK
发明人： MATSUBAYASHI JIROU , TAKEYAMA SATORU , YAKABE KAZUYUKI
IPC分类号： G06F9/45 , G06F9/44
摘要： PURPOSE:To support incorporated macro instructions which are abstracted and characteristic independently to a machine, by generating a source program by expressing the incorporated instructions with incorporated macro statements in high level language and by giving each incorporated macro instruction an incorporated macro definition for the recognition of a machine name and incorporated-instruction processing. CONSTITUTION:The source statement of a source program is inputted to a compiler 1 and when it is a macro statement, processing is passed to a pre- compiler 2, which recognizes the macro instruction to process macro expansion in accordance with a macro definition fetched from a macro library 3. This system generates the source program by expressing incorporated instructions with incorporated macro statements in high level language, and generates and registers an incorporated macro definition, which is used to recognize a machine name and to process an incorporated instruction corresponding to the machine, for every incorporated instruction in the library 3, so that the incorporated macro instructions which are abstracted and characteristic independently to the machine are supported.

10. 发明专利

JPS57111733A BUS CONVERSION SYSTEM 失效
公开(公告)号：JPS57111733A
公开(公告)日：1982-07-12
申请号：JP18540780
申请日：1980-12-29
申请人： PANA FACOM KK
发明人： YAMAGUCHI TAHEI , HAIDA HIROTOSHI , MASUDA TOMIO , SATOU NOBUAKI , OKUNO ITARU
IPC分类号： G06F13/36 , G06F5/00 , G06F13/40
摘要： PURPOSE:To raise the throughput of a CPU, by providing a low-speed bus for transferring data of unit quantity, a high-speed bus for transferring data of (n) unit qantity, and a corresponding address information storing buffer, and converting the data between both the buses by a control means. CONSTITUTION:This system is provided with a low-speed bus 1 for transferring data of unit quantity, a high-speed bus 2 for transferring data of (n) unit quantity, and a buffer 3 for storing the data of (n) unit and an address information corresponding to said data, and the data between both the buses is converted by a control means 4. In case when data is transferred to the bus 2 side from the bus 1 side, the means 4 writes the data in order in the buffer 3, and when it is written, a timer is reset, and after that, the timer is restarted, and when the buffer becomes full and the timer becomes time-over, said means controls so that the data is sent out to the bus 2. In case when data is transferred to the bus 1 from the bus 2, the means sends out the data to the bus if request data is in the buffer, requests it to the CPU and inputs it to the buffer if not any, and after that, sends it out to the bus 1, and controls so that the buffer is released in case of time-over.

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