专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JPS6158067A Maintenance system of communication control device 失效
标题翻译：通信控制设备维护系统
公开(公告)号：JPS6158067A
公开(公告)日：1986-03-25
申请号：JP17955584
申请日：1984-08-29
申请人： Fujitsu Ltd
发明人： OGASAWARA SHIGERU
IPC分类号： H04L29/04 , G06F11/30 , G06F11/34 , G06F13/00 , H04L13/00
摘要： PURPOSE: To retrieve a trouble easily by sampling a hardware condition of a designated circuit after the designated time from the designated microstep in a request processing condition.
CONSTITUTION: A register SLNR is installed so that a trace of a hardware condition can be obtained when a designated circuit is scanned, and a circuit number of a checking object is set to this register. When a microprogram step is successively read from a memory MPM, a trigger effective bit TEB is read, this is inputted through a register OP to only one AND gate G2. A non-scanning circuit number is coincident with a circuit number set to the register SLNR, and then, a comparing circuit COMP generates an coincident output, and when the trigger effective bit TEB is outputted, the AND gate G2 generates a H level output and sets a flip-flop FF. When a counter CTR overflows, a hardware trace momentum signal TC is outputted.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过在请求处理条件下从指定的微步指定的时间之后，对指定电路的硬件条件进行采样，轻松获取故障。构成：安装寄存器SLNR，以便在指定的电路被扫描时，可以获得硬件条件的跟踪，并且将检查对象的电路号设置为该寄存器。当从存储器MPM连续读取微程序步骤时，读取触发有效位TEB，通过寄存器OP将其输入到仅一个与门G2。非扫描电路号与设置到寄存器SLNR的电路号一致，然后，比较电路COMP产生一致的输出，当输出触发有效位TEB时，与门G2产生H电平输出，设置一个触发器FF。当计数器CTR溢出时，输出硬件轨迹动量信号TC。

2. 发明专利

JPS6077253A CONTROL SYSTEM OF INPUT/OUTPUT INSTRUCTION 失效
公开(公告)号：JPS6077253A
公开(公告)日：1985-05-01
申请号：JP18555583
申请日：1983-10-04
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD
发明人： SHIBATA HIROKI , OGASAWARA SHIGERU , SAWAI TOSHIO , AOYAMA MASAO , IDE DAISAKU , YAMAGA MITSUHIRO
IPC分类号： G06F13/36 , G06F13/10 , G06F13/12
摘要： PURPOSE:To attain I/O instruction control preventing overrun or underrun by providing an instruction retry requesting signal and an instruction suppressing signal between a processing part and a peripheral part and opening a common bus temporally or quickly on the basis of the state of peripheral parts. CONSTITUTION:A processing part PU of an information processor reads out an instruction stored in a memory part MM and executes the instruction successively. If the read-out instruction is an I/O instruction to/from the peripheral parts (ADP0-ADPn), the I/O instruction operation is specified by using the common bus. Each peripheral part discriminates the I/O instruction operating information on the common bus and an external register address, and if the address is the self-address, the I/O instruction operation is executed. An I/O instruction retry requesting signal RETRY is a signal informing the busy status of the peripheral parts and an instruction suppressing signal WAIT is a signal displaying the execution status at the operation of the output instruction of the peripheral part and is used for the suppression of advancement of the instruction in the processing part.

3. 发明专利

JPS6072358A PARITY CHECK SYSTEM 失效
公开(公告)号：JPS6072358A
公开(公告)日：1985-04-24
申请号：JP17971883
申请日：1983-09-28
申请人： FUJITSU LTD
发明人： OGASAWARA SHIGERU
IPC分类号： H03M13/00 , H04L13/00 , H04L29/02
摘要： PURPOSE:To reduce signal lines of interface between a controlling section and a connecting common section by comparing each parity bit held by an address line and a data line in a circuit controlling section and the parity bit from a circuit connecting common section. CONSTITUTION:A communication controlling and processing devide is made up of a communication controlling and processing section PC, circuit controlling section LC, circuit connecting common section LAB, rotary adapter LA and an interface bus B. The parity generate bit of an address line at the time of data transfer just before, the parity generate bit of a data line or the held parity bit is placed from the LAB on the data line after completion of data transfer of read or write and before starting next data transfer under control of a service processor SVP and CPU. Then, the parity bit or generate bit held by the address line is compared with each parity bit sent from the LAB in the LC.

4. 发明专利

JPS59127153A Program loading system 失效
标题翻译：程序加载系统
公开(公告)号：JPS59127153A
公开(公告)日：1984-07-21
申请号：JP22863182
申请日：1982-12-28
申请人： Fujitsu Ltd
发明人： OGASAWARA SHIGERU
IPC分类号： G06F15/177 , G06F9/445 , G06F15/16
CPC分类号： G06F9/445
摘要： PURPOSE:To load simultaneously programs of same contents by connecting these programs to a common bus via plural data processors which sets a memory in a writable state after deciding whether an address is for a program storing memory or not. CONSTITUTION:The signals ai indicating each device through a repeating device are turned on at a time when the programs are loaded to memories MAi which serve as program storing circuits of each device from a service processor. When a comparator 2 detects that the address signal designating a memory MAi1 is on an address signal line, the output of an AND circuit 3 is turned on. Then the write control signal is sent to the memory MAi1 via an OR circuit 4. The data on a write data signal line 6 is written at the address position of the memory MAi1 that is indicated by an address signal line 5. Then the programs can be simultaneously loaded when the signals ai (a1-an) are turned on at a time.
摘要翻译：目的：通过在决定是否存储存储程序的地址之后，将存储器设置为可写状态的多个数据处理器将这些程序连接到公共总线来同时加载相同内容的程序。构成：当将程序从服务处理器加载到作为每个设备的程序存储电路的存储器MAi时，通过重复设备指示每个设备的信号ai被接通。当比较器2检测到指定存储器MAi1的地址信号在地址信号线上时，AND电路3的输出导通。然后，写入控制信号通过OR电路4发送到存储器MAi1。写入数据信号线6上的数据被写入由地址信号线5指示的存储器MAi1的地址位置。然后程序可以当信号ai（a1-a）一次接通时同时加载。

5. 发明专利

JPS5958548A Diagnostic processing system by microprogram 失效
标题翻译：通过微波炉诊断加工系统
公开(公告)号：JPS5958548A
公开(公告)日：1984-04-04
申请号：JP16892082
申请日：1982-09-28
申请人： Fujitsu Ltd
发明人： OGASAWARA SHIGERU
IPC分类号： G06F9/22 , G06F11/22
CPC分类号： G06F11/22
摘要： PURPOSE:To perform microprogram control according to the content of a read register which holds read data from a control memory, by providing a memory stored with a microprogram and the read register. CONSTITUTION:A maintenance testing person when stopping microprogram instruction operation at some address of a memory CS1 uses the service processor SVP, maintenance panel, etc., of a maintenance diagnosis part 9 to rewrite the bit of a CS address stop control memory CSAHM2 in an address where the operation is to be stopped into logic ''1''. When plural addresses are used for stop conditions, said operations are repeated to write logic ''1'' in plural addresses of the CSAHM2. Further, when the microprogram is stopped after the execution, a switching circuit 10 is controlled so that the contents of the CSAHM read data holding part 5 in the memory read register 3 are selected.
摘要翻译：目的：通过提供存储有微程序和读取寄存器的存储器，根据读取寄存器的内容执行微程序控制，该读取寄存器保存来自控制存储器的读取数据。构成：在存储器CS1的某个地址停止微程序指令操作时的维护测试人员使用维护诊断部件9的服务处理器SVP，维护面板等来重写CS地址停止控制存储器CSAHM2的位地址，其中操作将被停止为逻辑“1”。当多个地址用于停止条件时，重复所述操作以在CSAHM2的多个地址中写入逻辑“1”。此外，当执行之后微程序停止时，控制切换电路10，使得选择存储器读取寄存器3中的CSAHM读取数据保持部分5的内容。

6. 发明专利

JPS5764842A Data transfer system 失效
标题翻译：数据传输系统
公开(公告)号：JPS5764842A
公开(公告)日：1982-04-20
申请号：JP14052380
申请日：1980-10-09
申请人： Fujitsu Ltd
发明人： TAKAHASHI HIROSHI , OGASAWARA SHIGERU
IPC分类号： H04L23/00 , G06F5/00 , G06F13/00
CPC分类号： G06F5/00
摘要： PURPOSE:To increase the efficiency of data transfer, by converting the data of unit number M into that of unit number N smaller than M at the transmitter side and transmitting the converted data along with a command of conversion. CONSTITUTION:At the transmitter side, the data of unit number M, e.g. 8 is converted 2 into the unit number N e.g. 4 smaller than M. This converted data is transmitted along with a command of conversion comprising a synchronous pattern and its following information of conversion. At the receiver side, the synchronous pattern is detected through a transmitting register 5 to give the synchronism to a data transfer control circuit 4. In such a way, the conventional 8 bits are turned into 4 bits when only figures are transmitted. Furthermore the bits can be converted into an optional number. Thus the efficiency is increased for the transfer of data.
摘要翻译：目的：为了提高数据传输的效率，通过将单元号M的数据转换为小于发送机侧的M的单元数N的数据，并传送转换的数据以及转换命令。构成：在发射机侧，单元号M的数据，例如 8被转换为单元号N，例如小于M.该转换的数据与包括同步模式的转换命令及其以下转换信息一起发送。在接收机侧，通过发送寄存器5检测同步模式，以给予数据传送控制电路4的同步。以这种方式，当仅发送数字时，传统的8位被转换成4位。此外，这些位可以转换成可选数字。因此，提高数据传输的效率。

7. 发明专利

JPS61274452A LINE SCANNING SYSTEM 失效
公开(公告)号：JPS61274452A
公开(公告)日：1986-12-04
申请号：JP11580485
申请日：1985-05-29
申请人： FUJITSU LTD
发明人： OGASAWARA SHIGERU
IPC分类号： H04L29/04 , G06F13/00 , H04L13/00
摘要： PURPOSE:To make it possible to accommodate a high speed line at an optional address position by providing a code area where a code value corresponded with a communication speed is stored and a counting area where a prescribed value at every scanning of a line memory is added at the line memory. CONSTITUTION:A line memory 1 that is a corresponded line is read out with a value represented by a scanning counter (CNT) 2 and communication speed code value storing areas C0-Cn indicated by a communication control process part (PC) are set at a read out code value register (CR) 5. At the same time, an add value storing areas P0-Pn on which one is added are set at an add value register (PR) 6. Next, the content of the CR5 is compared with that of the PR6 and a CNT2 is terminated when they are equal and a line process is performed according to the contents of line memories LSW0-LSWn that are corresponded lines. On the other hand, when the result at a comparison circuit 7 is not equal, after the contents of the PR6 are stored at the P0-Pn, the CNT2 is advanced and the next line memory is scanned.

8. 发明专利

JPS58195961A Microprogram controlling system 失效
标题翻译：微控制系统
公开(公告)号：JPS58195961A
公开(公告)日：1983-11-15
申请号：JP7857982
申请日：1982-05-11
申请人： Fujitsu Ltd
发明人： OGASAWARA SHIGERU
IPC分类号： G06F9/22 , G06F11/22 , G06F11/28
CPC分类号： G06F11/22
摘要： PURPOSE:To reduce a hardware quantity, by using a result of comparison of a specified code in an operand corresponding to a detected non-operation instructing operation code, and a given input code, as a start signal of a maintenance operation. CONSTITUTION:In case when a maintenance operation is executed after a microprogram instruction is stored in a control memory 1, a person in charge of maintenance inputs the same code as a discriminating code of a no-operation (NOP) instruction at the point of time of processing, in which it is desired to execute the maintenance operation, onto an operand discrimination corresponding code signal line 9. As a result, when the NOP instruction is read out while the microprogram instruction processing is being executed, a comparing circuit 5 outputs a comparison coincidence signal. In this case, a signal from an NOP code detecting signal line 7 from a decoding circuit is inputted to an AND gate 6, therefore, a trigger signal line 10 of an output of the AND gate 6 becomes on, and a maintenance circuit part is started.
摘要翻译：目的：通过使用与检测到的非操作指示操作代码相对应的操作数中的指定代码的比较结果和给定的输入代码来减少硬件量作为维护操作的开始信号。构成：如果在微程序指令存储在控制存储器1中之后执行维护操作的情况下，负责维护的人员在时间点输入与无操作（NOP）指令的识别码相同的代码在操作数辨别对应代码信号线9上执行维护操作的处理。结果，当在执行微程序指令处理时读出NOP指令时，比较电路5输出比较符号信号。在这种情况下，来自解码电路的NOP码检测信号线7的信号被输入到与门6，因此与门6的输出的触发信号线10变为导通，维护电路部分开始了

9. 发明专利

JPS5750152A Communication control processor 失效
标题翻译：通信控制处理器
公开(公告)号：JPS5750152A
公开(公告)日：1982-03-24
申请号：JP12548880
申请日：1980-09-10
申请人： Fujitsu Ltd , Hitachi Ltd , Nec Corp , Nippon Telegr & Teleph Corp
发明人： MIURA TETSUO , HIRAIDE TOSHIHIKO , AOYAMA MASAO , FURUYA KUNIO , OGASAWARA SHIGERU
IPC分类号： H04L29/04 , G06F13/00 , G06F13/22
CPC分类号： G06F13/22
摘要： PURPOSE:To achieve start control saving the hardware, by minimizing the effect on other line control adaptor. CONSTITUTION:A line common control section 1 consists of a control circuit 2, a start flag 3 storing the indication of start, an address register storing the line address indicated of starting, a scanning counter 5, a switching circuit 6 and a data buffer 7, and it is connected to a data bus 8 and a control bus 9. A line control adaptor 10 consists of an adaptor control circuit 11, a start-enable-flag 12 which displays the start reception enable being logic ''1'' when the preparation of reception of start information is finished, processing request flag 13 displaying the processing request, data buffer 14 in an adaptor, common bus 15 in the adaptor and a plurality of line interface circuits 16.
摘要翻译：目的：通过最小化对其他线路控制适配器的影响，实现启动控制，节省硬件。线路公共控制部分1包括控制电路2，存储开始指示的开始标志3，存储起始线路地址的地址寄存器，扫描计数器5，切换电路6和数据缓冲器7 ，并且连接到数据总线8和控制总线9.线路控制适配器10包括适配器控制电路11，启动使能标志12，其将起始接收使能显示为逻辑“1” 开始信息的接收准备完成，显示处理请求的处理请求标志13，适配器中的数据缓冲器14，适配器中的公共总线15以及多个线路接口电路16。

10. 发明专利

JPS6220052A STAND-BY SWITCHING CONTROL SYSTEM 失效
公开(公告)号：JPS6220052A
公开(公告)日：1987-01-28
申请号：JP15981485
申请日：1985-07-19
申请人： FUJITSU LTD
发明人： OGASAWARA SHIGERU
IPC分类号： H04L29/14 , G06F13/00 , H04L13/00
摘要： PURPOSE:To prevent a parity error from being detected in spite of a fact that no fault exists, in a switching period, by constituting the titled system so that a parity check of a data bus is not executed in the switching period, in case of stand-by switching between a CCU and an LUT. CONSTITUTION:When a data transfer is being executed between one CCU and one LUT, if a fault is generated in the CCU, a system monitor device detects it and instructs a switching to the LUT. When the LUT receives the switching instruction, a timer 1 is started, and simultaneously, a switching advance notice signal is sent to the CCU. When reaching the time which has been set to the timer 1, switching destination information which has been set to a register 3 is set to a register 4, and simultaneously, a timer 2 is started. In this way, by information which has been set to the register 4, switching of an interface is executed. When reaching the time which has been set to the timer 2, a switching completing signal is sent out to a CCU of a switching destination, and from this time point, the CCU of the switching destination executes a parity check.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式