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1. 发明专利

JPH1195936A DISK CONTROL CHANNEL DEVICE 失效
公开(公告)号：JPH1195936A
公开(公告)日：1999-04-09
申请号：JP25946697
申请日：1997-09-25
申请人： NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD
发明人： MASUDA ETSUO , OHASHI KOJI , TAKAHASHI MASAHIRO
IPC分类号： G06F13/10 , G06F3/06
摘要： PROBLEM TO BE SOLVED: To provide a disk control channel device by which a standardized high-reliability DK mount board can efficiently be exchanged, the maintenance of an information processing system using such a DK mount board can be improved and the design of a high-reliability information processing system is facilitated. SOLUTION: In this disk control channel device 1 (DKCH), respective disk devices 6A and 6B mounted on one DK mount board 6 are operated as one virtual DK (#00) having the total storage capacitance of the respective disk devices 6A and 6B, concerning a command from a CPU 3, it is received corresponding to the virtual DK and concerning a notice at the time of processing end, it is performed as the command executed result corresponding to the virtual DK. Then, the executed result of diagnostic processing or attribute read processing to the respective disk devices 6A and 6B when the active line of the DK mount board is mounted is reported also to the virtual DK.

2. 发明专利

JPH03296159A MEMORY ACCESS SYSTEM FOR DMA DEVICE 失效
公开(公告)号：JPH03296159A
公开(公告)日：1991-12-26
申请号：JP9840490
申请日：1990-04-13
申请人： NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD
发明人： MASUDA ETSUO , KOMACHIYA TADAYOSHI , SHIBATA YUJI , ISHIKAWA YASUHIRO
IPC分类号： G06F15/17 , G06F13/28 , G06F15/16 , G06F15/177
摘要： PURPOSE:To improve the direct memory access DMA transfer performance and to prevent the generation of a logic conflict by holding previously the ID information and a CM-IM boundary address in a common bus interface control part. CONSTITUTION:A DMA control part 43 designates a DMA via a control line 110 and suddenly gives a DMA address and the DMA data of a certain port to a common bus interface control part 42 via an address line 111 and a data line 112. The part 42 sends the DMA address, i.e., the output of a demultiplexer 113 and the DMA data, i.e., the output of a demultiplexer 114 to a common bus. At the same time, a comparator 118 compares the DMA address with the IM-CM boundary address of a register 117. Based on the result of this comparison, a selector 119 selects the CPU-ID or the CM-ID previously held in the registers 115 and 116. Then the ID information is sent to the common bus. Thus the DMA transfer performance is improved and at the same time a logic conflict is eliminated.

3. 发明专利

JPH1165879A BUS INTERFACE TESTING METHOD AND STORAGE MEDIUM RECORDING PROCESSING PROGRAM THEREFOR 失效
公开(公告)号：JPH1165879A
公开(公告)日：1999-03-09
申请号：JP22245897
申请日：1997-08-19
申请人： NIPPON TELEGRAPH & TELEPHONE , NEC CORP , HITACHI LTD , FUJITSU LTD , OKI ELECTRIC IND CO LTD
发明人： MASUDA ETSUO , SHIMIZU KOICHI , MURAKAMI TAKAO , NISHII HIROSHI , HIRANO YUICHI , TAWARA TAMOTSU
IPC分类号： G06F3/00 , G06F11/22
摘要： PROBLEM TO BE SOLVED: To provide a bus interface testing method and a storage medium recording processing program therefor by which the fault detection accuracy of an interface test can be improved. SOLUTION: When the number of signal lines as a bus interface test object is an odd number, 'write' (101) and 'read' (103) used for a conventional test are performed while switching respective opposite patterns like all '1' and all '0', for example, (100 and 200) and a parity check is performed (102 and 104) so that the one-bit stack fault of driver and receiver elements at a bus interface part can be detected. When the number of signal lines as the test object is an even number, a 3rd pattern to be the opposite party value to two other patterns is used (300). Further, the pattern when written and the pattern when read are collated in the respective patterns (105 and 106) and failure except for a parity error is detected as well.

4. 发明专利

JPH03127158A COMMON DATA CHANNEL DEVICE ACTUATING SYSTEM IN MULTIPROCESSOR SYSTEM 失效
公开(公告)号：JPH03127158A
公开(公告)日：1991-05-30
申请号：JP26569189
申请日：1989-10-12
申请人： NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD
发明人： MASUDA ETSUO , UEMORI AKIRA , FUKUSHIMA TOMOYOSHI , KANAZAWA NOBUHARU
IPC分类号： G06F13/12 , G06F15/16 , G06F15/17
摘要： PURPOSE:To reduce the processing burden of a program by using an actuation origin central processor equipment number received from a common bus and a head command address of a channel program and reading out a channel device control word on a separate storage device of the central processor equipment. CONSTITUTION:When a software of a central processor equipment issues an instruction for writing a head command address (CMA) of a channel program prepared on a separate storage device 102 of the central processor equipment in the corresponding register in a common data channel device 101 at the time of actuating the common data channel device, a common bus control circuit provided on the central processor equipment adds an actuating origin central processor equipment number of the central processor equipment of an actuating origin to the head command address of the channel program and sends it out to a common bus. The common data channel device 101 reads out a channel device control word on the separate storage device by using the received actuating origin central processor equipment number and the head command address of the channel program. In such a way, the CMA setting processing is simplified.

5. 发明专利

JP2000035897A DEVICE DETACHING SYSTEM 失效
公开(公告)号：JP2000035897A
公开(公告)日：2000-02-02
申请号：JP20202098
申请日：1998-07-16
申请人： NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD , HITACHI LTD , NEC CORP , OKI ELECTRIC IND CO LTD
发明人： MASUDA ETSUO , SHINPO HIDEO , MURAKAMI TAKAO , HATAE KENICHIRO , HIRANO YUICHI , TAWARA TAMOTSU
IPC分类号： G06F11/20 , G06F13/00
摘要： PROBLEM TO BE SOLVED: To flexibly cope with the change of the number of devices and to securely detach them without a manual operation by installing a complete suppression-type detaching means by way of a maintenance bus and a restrictive communication possible-type detaching means by way of a system bus. SOLUTION: MPU 12 in CPU 10 sets a detaching command in a register in CNC 14 and starts it. Then, μP 15 receiving an interruption from CNC 14 reads the command which is set in CNC 14, checks normality and sets the detaching command in MBC 17. MBC 17 designates a device i20 in accordance with a prescribed protocol and sends the detaching command to the maintenance bus MB. Then, MBC 28 of the device i20 receiving the command sets DV/RV 31 in an electrically cut state via a detaching signal 32 and transmits an answer. The, μP 15 reads the answer from MBC 17 which receives the answer writes the answer against CNC 14 and makes an interruption for the termination of command execution on MPU 12 then, the detachment of the device completes.

6. 发明专利

JPH11212898A PERIPHERAL STORAGE CONTROLLER AND ITS DATA TRANSFER METHOD 失效
公开(公告)号：JPH11212898A
公开(公告)日：1999-08-06
申请号：JP918798
申请日：1998-01-21
申请人： NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD
发明人： MASUDA ETSUO , SUGIYAMA RYUICHI , TAKAHASHI MASAHIRO
IPC分类号： G06F13/10 , G06F13/12
摘要： PROBLEM TO BE SOLVED: To cut a writing processing to a medium in a peripheral storage controller at the time of writing a data group which is diffusively arranged in a main storage device into continuous address areas to a peripheral storage device. SOLUTION: The peripheral storage controller (disk control channel device 4) which controls the transfer of data between the main storage device 2 and the peripheral storage device (hard magnetic disk device 6) based on a channel control word(CCW) which a central processing unit(CPU) 1 issues is provided with a write processing part 8 constituted of GWRT detection processing part 9, a command compilation processing part 10, a CCW fetch processing part 11 and an execution termination report processing part 12. Respective pieces of data transferred to the hard magnetic disk device 6 from the main storage device 2 are collectively transferred at the time of transferring data to the hard magnetic disk device 6 based on first CCW among a plurality of CCW made into a chain.

7. 发明专利

JPH05113953A START CONFIRMING SYSTEM 失效
公开(公告)号：JPH05113953A
公开(公告)日：1993-05-07
申请号：JP27586391
申请日：1991-10-24
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： ISHIKAWA YASUHIRO , TAKAHASHI MASAHIRO , WAKIMURA YOSHIAKI , MASUDA ETSUO
IPC分类号： G06F13/42
摘要： PURPOSE:To confirm the starting state of an input/output control part without lowering the throughput of a processor system in the start confirming system for the processor system connecting a central control part and the input/output control part through a bus interface control part equipped with a delayed response function. CONSTITUTION:A delay responding means 100 is provided to complete a start processing and to return information reporting the starting state to a central control part 4 after the information is completely prepared when an inquiry signal concerning the starting state of an input/output control part 6 is transmitted based on the delay response function after a start request signal is transmitted from the central control part 4 through bus interface control parts 2 and 3 and a system bus 1 to the input/output control part 6. Further, a delayed response waiting means 200 is provided at the central control part 4 so as to set the central control part 4 on standby until the information reporting the starting state is returned when the inquiry signal of the starting state is transmitted to the input/output control part 6.

8. 发明专利

JPS56121138A BUFFER MEMORY CONTROLLING SYSTEM 失效
公开(公告)号：JPS56121138A
公开(公告)日：1981-09-22
申请号：JP2436980
申请日：1980-02-28
申请人： NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： MASUDA ETSUO , NAKAMURA YUKIO , DOI AKIHIKO , FUJITA HIROSHI , HOSOKAWA CHIKAYOSHI
IPC分类号： H04L29/02 , G06F5/06 , G06F7/78 , G06F12/02 , G06F13/00
摘要： PURPOSE:To make it possible to efficiently accomodate and process all kinds of and a lot of different speed circuit terminals, by supervising idle data cells in the buffer area in common and in the lump as to all the circuit terminals, and dynamically controlling the assignment of the idle data cells. CONSTITUTION:After initializing, the data units I37-III39 are inputted from the circuit terminal #i. Data 37-39 are connected with a chain to the idle data cells which have been taken out in order from the idle data cell queue by the input controlling part, and are stored. The data cells 40-42, 43-46, 47-48 correspond to the units I-III, respectively. In this way, a data which has been stored in the buffer area is output to the outside of the memory, after processing. As a result, the data cell becomes idle, is released from the chain connected by the input/output controlling part, and if is added after the end cell of the queue of the idle cell. And, the pointer of the control area is updated by being accompanied by release of the data cell and addition to its idle data cell queue.

9. 发明专利

JPS56108157A DATA PROCESSOR 失效
公开(公告)号：JPS56108157A
公开(公告)日：1981-08-27
申请号：JP881480
申请日：1980-01-30
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： IKUTA AKIRA , MASUDA ETSUO , FUTAGAWA TAKESHI , DOI AKIHIKO , KIMURA AKIO
IPC分类号： G06F12/06 , G06F13/16 , G06F13/28
摘要： PURPOSE:To use an address bus of 8 bits with a CC in common, by isolating successively a 16-bit address given from the DMAC-LSI into a 8-bit row address and a 8-bit line address each for access. CONSTITUTION:The CC, DMAC-LSI and MM have the common memory address bus AB of 8 bits; and the CC, MM and IOC have the common data bus DB. The 16-bit address information given from the DMAC-LSI is first isolated into a row address of 8 bits by the MUX, and a row access is given to the MM through the AB. Then the address information is isolated into a line address of 8 bits, and an access is given to the MM via the AB. The CC sends the address of 8 bits to the MM via the AB to give the row access and then the line access. Thus the address given from the DAMC-LSI is performed by the address bus common to the CC, and accordingly the hardwares is reduced conveniently.

10. 发明专利

JPH11143817A INFORMATION PROCESSING SYSTEM, SYSTEM BUS TESTING METHOD AND STORAGE MEDIUM RECORDING ITS PROCESSING PROGRAM 失效
公开(公告)号：JPH11143817A
公开(公告)日：1999-05-28
申请号：JP31207697
申请日：1997-11-13
申请人： NIPPON TELEGRAPH & TELEPHONE , NEC CORP , FUJITSU LTD , OKI ELECTRIC IND CO LTD , HITACHI LTD
发明人： MASUDA ETSUO , SHINPO HIDEO , ISHIKAWA YASUHIRO , IKEDA KOJI , KOBAYASHI HIROSHI , HASHIMOTO HIROSHI
IPC分类号： G06F11/22 , G06F13/28
摘要： PROBLEM TO BE SOLVED: To efficiently execute the performance test of a system bus at an information processing system. SOLUTION: DMAC 8 provided in an input/output controller 4 is started from CPU(central processing unit) 1 and pseudo DMA transfer (DMA transfer without operating a subordinate input/output device) is executed between the controller 4 and a main memory 2 through the DMAC(direct memory access controlling circuit) 8 to give a load to a system bus by this pseudo DMA transfer to test durability and stability of the system bus in the configuration of the information processing system.

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