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1. 发明专利

JPH06202963A MEMORY FAULT DETECTING CIRCUIT 失效
公开(公告)号：JPH06202963A
公开(公告)日：1994-07-22
申请号：JP34738792
申请日：1992-12-28
申请人： FUJITSU LTD
发明人： SHIMIZU NOBORU , HAYASHI AKIHIRO , IKUTA KOJI
IPC分类号： G06F11/10 , G06F12/16
摘要： PURPOSE:To decrease the number of terminals of the memory fault detecting circuit which has plural memory check circuits and to detect such a fixed fault that data and parity degenerate into 1 or 0. CONSTITUTION:The memory fault detecting circuit has plural memory check circuits which each finds a parity bit matching an indication signal indicating odd or even parity by a parity bit generating circuit 10 from inputted data and writes it in a memory 11 together with the inputted data, and also finds the parity bit of its read data matching an indication signal indicating odd or even parity and compares it with the read parity bit to decide memory abnormality unless those parity bits match each other; and indication signals for odd or even parity supplied to the memory check circuits 1, 2, and 3 are converted by a parity indicating circuit 20 as to convert the odd parity and even parity in series at a certain period and supplied to a series-parallel converting circuit 13, which converts them into parallel signals and supplies them to the memory check circuits 1, 2, and 3.

2. 发明专利

JPH0637732A CASCADE CONNECTION TYPE TIME SWITCH CIRCUIT 失效
公开(公告)号：JPH0637732A
公开(公告)日：1994-02-10
申请号：JP18558492
申请日：1992-07-14
申请人： FUJITSU LTD
发明人： SUZUKI MASAYUKI , IKUTA KOJI , MORITAKA TETSUO , TAKAHASHI YUJI , YOSHINO TOYOHIKO
IPC分类号： H04J3/16 , H04Q3/52 , H04Q11/08
摘要： PURPOSE:To realize a cascade connection type time switch circuit consisting of small scale circuits and coping simply with extension of a highway with respect to the cascade connection type time switch circuit replacing time slots. CONSTITUTION:Each of time slot replacement sections 1-m of a time switch circuit 100 replacing time slots of data inputted from an mN-lines of highway HW is provided with a time switch replacing time slots of mN-lines of highway HW, a phase adjustment circuit 20 adjusting the phase so that an output signal as a result of the replacement by the time switch 10 is in cascade connection to an output signal of a prestage time slot replacement section (i-1), and a selection circuit 30 selecting any of output signals so that the output signal of the prestage time slot replacement section (i-1) and an output of the phase adjustment circuit 20 of a concerned time slot replacement section (i) are connected in cascade and outputting the selected result.

3. 发明专利

JPH04357726A MASK PATTERN INSERTING SYSTEM AT FORMAT CONVERSION 失效
公开(公告)号：JPH04357726A
公开(公告)日：1992-12-10
申请号：JP13252491
申请日：1991-06-04
申请人： FUJITSU LTD
发明人： ASAMA MOTOKAZU , SHIROTA KATSUYA , IKUTA KOJI , TAKAHASHI YUJI
IPC分类号： H04J3/17
摘要： PURPOSE:To realize a mask pattern inserting system in which a mask pattern is inserted with a simple control and a small scale circuit with respect to the system in which only a valid channel is extracted from a data format with plural channels multiplexed thereon and a mask pattern is inserted to an idle channel. CONSTITUTION:The system is provided with a random access memory 10, a mask control circuit 20, a write address generating circuit 30, a mask address generating circuit 40, a multiplexer circuit 50, a selector 60 and a read address generating circuit 70. Data is written at an address generated from the write address generating circuit 30 at the entry of a valid channel and a mask pattern is written at an address generated from a mask address generating circuit 40 at the entry of an invalid channel, and the format conversion and the insertion of the mask pattern are implemented simultaneously by reading the data sequentially.

4. 发明专利

JPH04183132A ERRONEOUS OPERATION PROTECTING CIRCUIT FOR COUNTER CIRCUIT 失效
公开(公告)号：JPH04183132A
公开(公告)日：1992-06-30
申请号：JP31320690
申请日：1990-11-19
申请人： FUJITSU LTD
发明人： SUGAWARA AKIRA , IKUTA KOJI , OGATA HIROKI , MIYAMA KENICHI
IPC分类号： H04L7/04
摘要： PURPOSE:To protect erroneous operation of a counter circuit by providing the counter circuit with the function that when a reset signal is released, if a data receiving busy signal is being input, sending a clear signal is stopped when inputting the data receiving signal is completed. CONSTITUTION:When a reset signal is released during counting received data and the potential of a reset signal input section 3' turns to '1', the potential of R of FF4 turns to '1'. Then, the output from NAND4 remains at '1', while the input to FF4 changes R at '1' and S at '1'. However, in this state, since the output holds the preceding state, output 11' from FF4 still remains at '0', and CNT2 holds a clear state. When terminating the reception of data 2' in this state, output 10' from data receiving on detecting circuit 3 turns to '1', and the input to FF4 changes R to '1' and S to '0'. In this state, since the output 11 from FF4 turns to '1', CNT2 is released from a clear state.

5. 发明专利

JPH0345948B2 失效
公开(公告)号：JPH0345948B2
公开(公告)日：1991-07-12
申请号：JP24611383
申请日：1983-12-29
申请人： FUJITSU LTD
发明人： HAYASHI AKIHIRO , TAKEDA SATOSHI , IKUTA KOJI , TAKAHASHI KAKUJI
IPC分类号： H04L25/49

6. 发明专利

JPH0263234A AUTOMATIC PHASE SYNCHRONIZING CIRCUIT 失效
公开(公告)号：JPH0263234A
公开(公告)日：1990-03-02
申请号：JP21611188
申请日：1988-08-29
申请人： FUJITSU LTD
发明人： HARIGAYA KOICHI , IKUTA KOJI
IPC分类号： H03L7/00 , H04L7/00
摘要： PURPOSE:To simplify the test by inputting a data generated from one simulation test panel to other panel to be tested and taking phase synchronization with reset. CONSTITUTION:A phase of a data from a simulation test panel 3 and a phase of a data from a panel 6 to be tested are compared by a phase matching circuit 4 to match the phase thereby generating a reset pulse coincident with the phase of the panel 6 to be tested. Thus, the test making the phase of the data from the simulation test panel 3 and the panel 6 to be tested is attained by using the reset pulse. Thus, a signal generated from the simulation test panel is inputted to the other panel 6 to be tested and phase synchronization is taken by applying reset so as to simplify the test.

7. 发明专利

JPH0220937A SYNCHRONOUS DETECTING CIRCUIT 失效
公开(公告)号：JPH0220937A
公开(公告)日：1990-01-24
申请号：JP17140988
申请日：1988-07-08
申请人： FUJITSU LTD
发明人： HARIGAYA KOICHI , IKUTA KOJI
IPC分类号： H04J3/06 , H04L7/08
摘要： PURPOSE:To shorten the synchronous state reset time by providing an all '0' generating means for sending out all '0' data by an access of an alarm display signal, and a frame synchronizing pattern detecting means. CONSTITUTION:The number of pieces of '0' in one frame or plural frames is always monitored, and when it is detected that said number is below a prescribed value, when an alarm signal to be displayed is ON, an input of received data is obstructed by an all '0' generating means 10 until the alarm display signal becomes OFF completely, and also, by ON of this alarm display signal, all '0' data is sent out of the all '0' generating means 10, and written in a frame synchronizing pattern detecting means 20a. Subsequently, at the time point when the number of pieces of '0' exceeds the prescribed value, and the alarm display signal has become OFF, a frame synchronizing pattern is detected by the frame synchronizing pattern detecting means 20a from in the received data which has been received through the all '0' generating means 10. In such a way, the probability for detecting artificially the frame synchronizing pattern is lowered remarkably and the synchronous reset time is shortened.

8. 发明专利

JPS62172274A APPARATUS FOR TESTING INTEGRATED CIRCUIT 失效
公开(公告)号：JPS62172274A
公开(公告)日：1987-07-29
申请号：JP1497386
申请日：1986-01-27
申请人： FUJITSU LTD
发明人： IKUTA KOJI , KODACHI HIRONORI , SUWA SUSUMU
IPC分类号： G01R31/28
摘要： PURPOSE:To contrive to reduce the number of testing processes necessary for the operation test of a processing block, by establishing synchronism by selecting a frame synchronous pattern to add the same to a detection circuit. CONSTITUTION:At time of use in normal state, a selection circuit 3 selects data inputted from an external pin IN-1 and supplies the same to a frame synchronous pattern detection circuit 1. After frame synchronism is established, a timing signal is sent to a processing block from a generation circuit 16 through an AND circuit 17. At the time of an operation test, a test signal is added to the external pin IN-1 to drive the selection circuit 3 and the output of a frame synchronous pattern generating circuit 2 is sent to the detection circuit 1. The circuit 1 quickly establishes frame synchronism. A timing signal is rapidly sent out to the processing block.

9. 发明专利

JPH07219857A MEMORY FAULT DETECTION/ERROR CORRECTION SYSTEM 失效
公开(公告)号：JPH07219857A
公开(公告)日：1995-08-18
申请号：JP1143994
申请日：1994-02-03
申请人： FUJITSU LTD
发明人： KAMIOKA SHINJI , IKUTA KOJI , HAYASHI AKIHIRO
IPC分类号： G06F12/16 , G06F11/10
摘要： PURPOSE:To provide a memory fault detection/error correction system which can reduce the power consumed for detection of the memory faults and also can improve the correction efficiency of the memory writing errors. CONSTITUTION:An S/P converter means 1 converts the serial write data into the parallel ones, and a parity calculator means 2 calculates a parity of the parallel data. A memory means 3 stores the parallel data in a 1st RAM and stores the parity calculating result in a 2nd RAM. Furthermore a parity check means 4 calculates the parity of the data stored in the 1st RAM and also compares this parity calculating result with the data stored in the 2nd RAM to generate the output to show the presence or absence of errors of the data written in the 1st RAM. If an error of the written data is confirmed, an enable control means 5 writes the data again in the means 5 and operates the 2nd RAM only for a period needed for detection of errors of the written data.

10. 发明专利

JPH05341958A 失效
公开(公告)号：JPH05341958A
公开(公告)日：1993-12-24
申请号：JP15102192
申请日：1992-06-11
申请人： FUJITSU LTD
发明人： OGATA HIROKI , IKUTA KOJI , SUGAWARA AKIRA
IPC分类号： G06F5/06 , H04L7/027 , H04L13/08
摘要： PURPOSE:To provide the data switching circuit for which change of circuits is unnecessitated even the frequency of a clock is changed, delay is reduced and a circuit scale is small for taking out data from signals for which n-bit parallel data are synchronized with a fast clock and transmitted at a slow clock. CONSTITUTION:The n-bit parallel data are latched and taken out at a fast data latch circuit 1 and inputted to an FF 3 for reinputting the data at the asynchronous slow clock and the FF 2 for shifting the data by the one cycle of the fast clock. The output is inputted to the FF 4 for reinputting the data at the asynchoronous slow clock, the output is inputted to the FF 5 for shifting the data for the one cycle of the slow clock and the output is inputted to a slow data latch circuit 8 and inputted to an EX-OR 6 along with the output of the FF 5. The output is inputted to a rise detection circuit 7 for outputting a latch pulse synchronized with the slow clock when rise is detected and the n-bit parallel data inputted to the slow data latch circuit 8 is latched and outputted by the latch pulse.

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