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1. 发明专利

JP2007273624A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007273624A
公开(公告)日：2007-10-18
申请号：JP2006095737
申请日：2006-03-30
申请人： Fujitsu Ltd , 富士通株式会社
发明人： SAITO NOBUKATSU , UNO TADASHI , KANO MASASHI , MATSUOKA YOSHIHIRO
IPC分类号： H01L21/3205 , H01L21/60 , H01L23/52
CPC分类号： H01L24/05 , H01L23/293 , H01L23/3192 , H01L24/03 , H01L24/13 , H01L2224/02166 , H01L2224/0345 , H01L2224/03912 , H01L2224/0401 , H01L2224/05012 , H01L2224/05086 , H01L2224/05095 , H01L2224/05124 , H01L2224/05571 , H01L2224/05573 , H01L2224/05666 , H01L2224/1146 , H01L2224/1147 , H01L2224/11849 , H01L2224/131 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/15787 , H01L2924/3025 , H01L2924/351 , H01L2924/00014 , H01L2924/01014 , H01L2224/05552 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device inhibiting the peeling of a wiring layer and a conductive layer due to a thermal stress at a time when a semiconductor substrate is mounted, preventing an electrical disconnection and having a high performance and a high reliability and an efficient manufacturing method for the semiconductor device. SOLUTION: The semiconductor device has the semiconductor substrate (such as a silicon wafer 10), the wiring layer 14 formed on the semiconductor substrate 10 and a first conductive layer 15 formed on the wiring layer. The semiconductor device further has an inter-layer insulating film 16 formed on the first conductive layer and a second conductive layer 17 formed on the inter-layer insulating film 16 in a conductible manner with the first conductive layer 15. A bump is formed on the second conductive layer. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：为了提供一种半导体器件，其在安装半导体衬底时由于热应力而抑制布线层和导电层的剥离，防止电断开并具有高性能和高可靠性和半导体器件的高效制造方法。解决方案：半导体器件具有半导体衬底（例如硅晶片10），形成在半导体衬底10上的布线层14和形成在布线层上的第一导电层15。半导体器件还具有形成在第一导电层上的层间绝缘膜16和与第一导电层15以可导电的方式形成在层间绝缘膜16上的第二导电层17。第二导电层。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2007013063A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2007013063A
公开(公告)日：2007-01-18
申请号：JP2005195432
申请日：2005-07-04
申请人： Fujitsu Ltd , 富士通株式会社
发明人： MATSUOKA YOSHIHIRO , IMAMURA KAZUYUKI , OSHIMA MASAO , SUZUKI TAKASHI , SAWADA TOYOJI
IPC分类号： H01L21/60 , H01L21/3205 , H01L23/52
CPC分类号： H01L23/49816 , H01L24/11 , H01L24/12 , H01L2224/05001 , H01L2224/05011 , H01L2224/05022 , H01L2224/05027 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05184 , H01L2224/05572 , H01L2224/05655 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/3025 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide a bump wiring structure capable of preventing current concentration in the joint of a bump and uniformizing a current density. SOLUTION: A wiring layer 41 is provided separately from a connection pad 32 to which the bump 37 is joined. A plurality of columnar conductors 43 are arranged for electrically connecting the connection pad 32 and the wiring layer 41. By arranging the columnar conductors 43 over the entire joint region corresponding to the joint of the bump 37, the current density is uniformized in the joint. Also, by changing the arrangement density of the columnar conductors 43 corresponding to the direction of an electron flow, the current density is further uniformized in the bump joint. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够防止凸起接头中的电流集中并使电流密度均匀化的凸块布线结构。解决方案：布线层41与连接凸块37连接的连接焊盘32分开设置。布置多个柱状导体43，用于电连接连接焊盘32和布线层41.通过将柱状导体43布置在对应于凸块37的接头的整个接合区域上，电流密度在接头中均匀化。此外，通过改变与电子流的方向对应的柱状导体43的排列密度，电流密度在凸块接合部中进一步均匀化。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2005260163A Capacitance element and its manufacturing method, semiconductor device and its manufacturing method 审中-公开
标题翻译：电容元件及其制造方法，半导体器件及其制造方法
公开(公告)号：JP2005260163A
公开(公告)日：2005-09-22
申请号：JP2004073018
申请日：2004-03-15
申请人： Fujitsu Ltd , 富士通株式会社
发明人： YASUDA MAKOTO , WATANABE AKIYOSHI , MATSUOKA YOSHIHIRO
IPC分类号： H01L21/76 , H01L21/822 , H01L21/8234 , H01L27/04 , H01L27/06 , H01L29/06
CPC分类号： H01L27/0629 , H01L27/0805 , H01L29/66181 , H01L29/94
摘要： PROBLEM TO BE SOLVED: To provide a capacitance element having high reliability and its manufacturing method, and a semiconductor device using its capacitance element and its manufacturing method.
SOLUTION: The capacitance element includes a element separating area 14 formed on a semiconductor substrate 10, a lower electrode 16 which is formed in an element area 12 defined by the element separating area and is composed of an impurity diffusion layer, a dielectric film 18 composed of a thermally oxidized film formed on the lower electrode, an upper electrode 20 formed on the dielectric film, an insulating layer 26 formed on the semiconductor substrate to cover the upper electrode, a first conductor plug 30a buried into a first contact hole 28b reaching the lower electrode, and a second conductor plug 30b buried into a second contact hole 28b reaching the upper electrode. The upper electrode is not formed on the element separating area.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供具有高可靠性的电容元件及其制造方法，以及使用其电容元件的半导体器件及其制造方法。解决方案：电容元件包括形成在半导体衬底10上的元件分离区域14，下电极16，其形成在由元件分离区限定的元件区域12中，并由杂质扩散层，电介质由下部电极上形成的热氧化膜构成的膜18，形成在电介质膜上的上部电极20，形成在半导体基板上的覆盖上部电极的绝缘层26，埋入第一接触孔 28b到达下电极，第二导体插塞30b埋入到到达上电极的第二接触孔28b中。上部电极未形成在元件分离区域上。版权所有（C）2005，JPO＆NCIPI

4. 发明专利

JP2007266061A E fuse and method of manufacturing the same 有权
标题翻译： E保险丝及其制造方法
公开(公告)号：JP2007266061A
公开(公告)日：2007-10-11
申请号：JP2006085469
申请日：2006-03-27
申请人： Fujitsu Ltd , 富士通株式会社
发明人： MATSUOKA YOSHIHIRO , MATSUYAMA HIDEYA , SAWADA TOYOJI , NAGAYAMA JUN , SUZUKI TAKASHI , SUEDA MASAHIRO
IPC分类号： H01L21/82 , H01L21/3205 , H01L23/52
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide an e fuse (electrical-fuse) which can avoid back-flow effect and is superior in accuracy, and to provide a method of manufacturing the same. SOLUTION: A silicide (area) 1 is a shaded part, and it is comprised of a first contact area 7, a fuse area 8 of which width in lengthwise direction is smaller than that of the first contact area 7, and a second contact area 9 which is formed opposite to the first contact area 7 with the fuse area 8 in between. In this case, a non-silicide area 2 is provided at an adjacent position (non-fuse connection side) to the opposite side to the side being in contact with the fuse area 8 in the second contact area 9. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够避免逆流效应并且精度优异的e熔丝（电熔丝），并提供其制造方法。解决方案：硅化物（区域）1是阴影部分，它包括第一接触区域7，长度方向上宽度小于第一接触区域7的熔丝区域8，以及第二接触区域9，其形成为与第一接触区域7相对，熔丝区域8在其间。在这种情况下，非硅化物区域2设置在与第二接触区域9中的保险丝区域8接触的相对侧的相邻位置（非熔断体连接侧）。版权所有：（C）2008，JPO＆INPIT

5. 发明专利

JP2004282000A Semiconductor device 有权
公开(公告)号：JP2004282000A
公开(公告)日：2004-10-07
申请号：JP2003280004
申请日：2003-07-25
申请人： Fujitsu Ltd , 富士通株式会社
发明人： SUGIURA IWAO , NAMIKI TAKAHISA , MATSUOKA YOSHIHIRO
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532
CPC分类号： H01L23/53295 , H01L23/522 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To prevent a stress at wire bonding, etc. to be applied to a minute wiring pattern in a first multilayer wiring structure, in a semiconductor integrated circuit device comprising a first multilayer wiring structure using a low dielectric constant inter-layer insulating film and a second multilayer wiring structure using an inter-layer insulating film of larger dielectric constant formed thereon. SOLUTION: A support rod is so formed as to be extended while penetrating through the multilayer wiring structure, at least in the first multilayer wiring structure. COPYRIGHT: (C)2005,JPO&NCIPI

6. 发明专利

JPH07245357A SEMICONDUCTOR DEVICE AND ITS INSPECTION METHOD 失效
公开(公告)号：JPH07245357A
公开(公告)日：1995-09-19
申请号：JP3338294
申请日：1994-03-03
申请人： FUJITSU LTD , FUJITSU VLSI LTD
发明人： KATAGIRI TOMOKO , NIWA YOSHITAKA , MATSUOKA YOSHIHIRO , ITO SATORU
IPC分类号： H01L21/66 , H01L23/02 , H01L23/04
摘要： PURPOSE:To provide a semiconductor device wherein the pattern surface of a semiconductor chip in the mounted state especially on a base substrate can be easily inspected by an optical means, in relative to a semiconductor device constituted by mounting a semiconductor chip, in the face down state, on the base substrate. CONSTITUTION:An observation hole A tightly closed with a closing-up lid 21e which can be detached by heating is formed in the region of a base substrate 31 which region corresponds with the pattern surface 22a of a semiconductor chip 22.

7. 发明专利

JPH0384929A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0384929A
公开(公告)日：1991-04-10
申请号：JP22215589
申请日：1989-08-28
申请人： FUJITSU LTD , FUJITSU VLSI LTD
发明人： YAMAUCHI KAZUO , MATSUOKA YOSHIHIRO
IPC分类号： H01L21/60 , H01L21/321
摘要： PURPOSE:To enhance a close contact property between a lead and a bump by a method wherein a bump whose area is relatively large is divided into small bumps, its plating growth speed is approached to that of a bump whose area is relatively small and a height of the bumps is made uniform. CONSTITUTION:Regarding at least a bump whose area is largest, the bump is divided, and a growth operation is executed by making an area of bumps nearly equal; then, a plating growth speed becomes nearly uniform inside a chip, and an irregularity in a plating height can be reduced. For example, since an area of a pad 6a for power-supply line use is about three times that of a pad 6b for signal line use, a bump 5a is divided into three so that the same size as that of a bump 5b for signal line use can be used. Concretely, a bump (bump for power-supply line use) whose Al pad size is large is divided in a designing stage; a mask is made in such a way that a size of a bump is as large as that of a bump (bump for signal use) whose size is small. After that, a tab bonding operation is executed by using an ordinary heating tool. Thereby, a close contact property between a lead and the bump becomes good.

8. 发明专利

JPH09246344A SEMICONDUCTOR SUBSTRATE 失效
公开(公告)号：JPH09246344A
公开(公告)日：1997-09-19
申请号：JP4600996
申请日：1996-03-04
申请人： FUJITSU LTD , FUJITSU VLSI LTD
发明人： MATSUOKA YOSHIHIRO , NIWA YOSHITAKA , ITO SATORU , KATAGIRI TOMOKO
IPC分类号： H01L21/66 , H01L21/301 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To prevent the contact of a metal piece for constituting a pad electrode with a semiconductor element by constituting the electrode by a square pattern having one side along a scribing direction and a plurality of patterns extended substantially perpendicular to the scribing direction from the square pattern. SOLUTION: A monitoring element 2 for inspecting the characteristics of a semiconductor element 4 formed on a semiconductor substrate is formed in a scribing region 3, and a pad electrode 1 is led from the element 2. The electrode 1 is formed of a patterned metal thin film, and has a square pattern 11 having a long side in the scribing direction and a plurality of bar-like patterns 12 extended perpendicularly to the long side of the pattern 11. In the case of cutting the region 3 by a dicing saw, the pattern 11 for forming the pad 2 is finely cut along the scribing line, the metal thin film for constituting the electrode 1 all becomes short metal thin pieces, and is not brought into contact with the semiconductor element.

9. 发明专利

JPH07122609A METHOD FOR ANALYZING DETECTIVE BUMP 失效
公开(公告)号：JPH07122609A
公开(公告)日：1995-05-12
申请号：JP26766893
申请日：1993-10-27
申请人： FUJITSU LTD , FUJITSU VLSI LTD
发明人： ITO SATORU , MATSUOKA YOSHIHIRO , NIWA YOSHITAKA , KATAGIRI TOMOKO
IPC分类号： H01L21/66
摘要： PURPOSE:To detect insufficient connection at a bump positively while protecting the bump against damage when it is exfoliated from a substrate. CONSTITUTION:In a semiconductor device where a semiconductor chip 1 is connected with a substrate 3 through a bump 2, a resin 8 is cured around the bump. The substrate is then heated to exfoliate the semiconductor chip therefrom and the surface state of the bump is observed. An insufficiently connected bump is then specified based on the adhesion of resin or the abnormal surface state.

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