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1. 发明专利

JPS6342100A TERNARY LEVEL ROM 失效
公开(公告)号：JPS6342100A
公开(公告)日：1988-02-23
申请号：JP18524686
申请日：1986-08-08
申请人： FUJITSU LTD
发明人： SUZUKI YASUO , SUZUKI YASUAKI , HIRAO HIROSHI
IPC分类号： G11C16/04 , G11C11/56
摘要： PURPOSE:To reduce the number of reference cells, to simplify a circuit constitution and to improve the degree of integration by deciding the state of a cell at a ternary level from the logical combinations of the potentials of two switching elements. CONSTITUTION:The gm of a cell transistor Q can select gm1, gm2 and gm3, whereas the gm of a reference cell transistor QR is gm2. A cell level generating circuit 3 converts the output of the cell transistor Q into a voltage V, while a reference cell level generating circuit 4 converts the output of the reference transistor QR into a reference voltage VR. The switching element Q3 is connected between a load Q1 and the cell level generating circuit 3, while the switching element Q4 is connected between a load Q2 and the reference cell level generating circuit 4. From the logical combinations of the potentials of nodes N1 and N2 in the switching elements Q3 and Q4, the state of the cell transistor Q, that is, gm can be discriminated.

2. 发明专利

JPS6146065B2 失效
公开(公告)号：JPS6146065B2
公开(公告)日：1986-10-11
申请号：JP2227183
申请日：1983-02-14
申请人： FUJITSU LTD
发明人： NAGASAWA MASANORI , SUZUKI YASUO , HIRAO HIROSHI
IPC分类号： G11C17/00 , G11C11/56 , G11C17/08 , G11C17/12 , H01L21/8246 , H01L27/10 , H01L27/112 , H01L29/78

3. 发明专利

JPS5948567B2 JPS5948567B2 - 失效
公开(公告)号：JPS5948567B2
公开(公告)日：1984-11-27
申请号：JP17118479
申请日：1979-12-29
申请人： Fujitsu Ltd
发明人： HIRAO HIROSHI
IPC分类号： H03K3/353 , H03K3/3565
CPC分类号： H03K3/3565

4. 发明专利

JPS5696525A SCHMITT TRIGGER CIRCUIT 失效
公开(公告)号：JPS5696525A
公开(公告)日：1981-08-04
申请号：JP17118479
申请日：1979-12-29
申请人： FUJITSU LTD
发明人： HIRAO HIROSHI
IPC分类号： H03K3/353 , H03K3/3565
摘要： PURPOSE:To avoid the production of improper operation even with the power supply level in variance, by lowering the potential of connecting point of transistors in series connection correspondingly, when the power supply level is decreased. CONSTITUTION:A transistor TRQX is inserted between the power supply line and the node N1, the drain is connected to the power supply line, and the gate and source are connected to the node N1 respectively. When the power supply level VCC is lowered and the level difference with the node N1 is greater than the threshold voltage of TRQX, the charge of the node N1 is discharged to the power supply line via TRQX to lower the level of the node N1. Thus, the improper operation due to a delay in the level decrease in the node N1 can be avoided.

5. 发明专利

JPS5525840A DECODER CIRCUIT 失效
公开(公告)号：JPS5525840A
公开(公告)日：1980-02-23
申请号：JP9792378
申请日：1978-08-11
申请人： FUJITSU LTD
发明人： HIRAO HIROSHI , ORIKABE YASUO
IPC分类号： H03M5/20 , G11C8/12 , G11C11/413
摘要： PURPOSE:To decrease considerably the number of the memory elements with a simple circuit constitution. CONSTITUTION:The 1st circuits E1-E4 decode the optional k(2) bits of the address signal composed of n(8) bits, and 2nd circuit E5 of 2 (64) sets decode the rest n-k(6) bits of the address signal. In addition, 3rd circuit E7 is provided which receives the output of circuit E5 and comprises four units of circuit elements using output PW1-PW4 of four units (2 units) of circuits E1-E4 as the power source each. Now 2 (4) units are selected among addresses 2 (256) through circuits E5, E6 and E9, and 2 (4) units are selected through circuits E1-E4. As a result, all addresses of 2 (256) units can be selected, thus decreasing a considerable amount of the element number as well as reducing the occupied area.

6. 发明专利

JPS6141078B2 失效
公开(公告)号：JPS6141078B2
公开(公告)日：1986-09-12
申请号：JP17079483
申请日：1983-09-16
申请人： FUJITSU LTD
发明人： SUZUKI YASUO , HIRAO HIROSHI , SUZUKI YASUAKI
IPC分类号： G11C16/04 , G11C11/56 , G11C29/00 , H01L27/10

7. 发明专利

JPS6010495A SENSE AMPLIFIER 失效
公开(公告)号：JPS6010495A
公开(公告)日：1985-01-19
申请号：JP11861883
申请日：1983-06-30
申请人： FUJITSU LTD
发明人： SUZUKI YASUO , HIRAO HIROSHI , SUZUKI YASUAKI
IPC分类号： G11C7/06 , G11C11/409 , G11C11/419 , G11C11/56 , G11C11/34
摘要： PURPOSE:To furnish a circuit suitable for multi-value level memory that can perform accurate operation even when input power varies remarkably and accordingly reference voltage becomes low by making a power source to a flip flop circuit off until just before starting sense operation. CONSTITUTION:Clocks CLKn, CLKp applied to switching circuits Q5, Q6 and Q11, Q12 are so designed that CLKn rises first and then CLKp falls. At first CLKn is L level, and CLKp is H level and a flip flop circuit FF does not operate. When a memory cell is read out and the output D is applied to a transistor Q7, CLKn rises, and Q6 becomes on and Q5 becomes off. However, as Q12 is in and Q11 is off, the current of passage Vcc, Q3, P1, Q8, ground and Vcc, Q4, P2, Q12, ground does not flow. Then, CLKp falls, Q11 becomes on, Q12 becomes off, and the voltage of a power source Vcc is applied to the flip flop circuit FF. One of transistors Q1, Q2 becomes on, and another becomes off.

8. 发明专利

JPS582039A TEST METHOD FOR SEMICONDUCTOR SUBSTRATE 失效
公开(公告)号：JPS582039A
公开(公告)日：1983-01-07
申请号：JP9943981
申请日：1981-06-25
申请人： FUJITSU LTD
发明人： TANAKA IZUMI , HIRAO HIROSHI
IPC分类号： G01R31/26 , H01L21/02 , H01L21/66
摘要： PURPOSE:To automatically examine a plurality of a variety of elements, by arranging decision elements corresponding to each kind at the top position of each area to detect the kind of an element continuous to the decision element for the selection of the test program corresponding thereto. CONSTITUTION:A sbustrate to be measured is placed on a movable table and when positioning is finished, the measuring probe of a prober contacts with each pad of element on the starting position. Before test starts, firstly this element is identified to be a decision element or not. When the element is recognized as a decision element, the test program corresponding to the decision element is called out according to the program, then to execute the element test based on this program. If the element is a normal ROM, it is judged to be not a decision element, and immediate test is executed according to an already selected program for the decision whether good or not.

9. 发明专利

JPS5531374A INVERTER CIRCUIT 失效
公开(公告)号：JPS5531374A
公开(公告)日：1980-03-05
申请号：JP10521078
申请日：1978-08-29
申请人： FUJITSU LTD
发明人： HIRAO HIROSHI , ORIKABE YASUO
IPC分类号： H03K19/0944 , H03K17/16 , H03K19/00 , H03K19/0948
摘要： PURPOSE:To check generation of the transient short-circuit current by mounting the auxiliary transistor in the front stage of the output stage transistor, and preventing the output stage transistors from becoming ON state at the same time. CONSTITUTION:This inverter circuit has the first and second circuits in which an inversion output and a non-inversion output of the static type MOS memory are connected in series to MOSFET Q5, Q6 supplied to the gates, and their load elements Q1, Q2, respectively, and their connection points N1, N2 are made their output terminals; and the output stage by which MOSFET Q7, Q8 receiving outputs of the points N1, N2 to their gates are connected in series. And the auxiliary MOSFET Q9, Q10 by which rise of the gate voltage of MOSFET Q7, Q8 is suppressed by receiving output of the respective opposite points N1, N2 to their gates are connected to the gates of MOSFET Q7, Q8. Thus it is possible to prevent the output stage transistors from becoming ON state, and to check generation of the transient short- circuit current.

10. 发明专利

JPH0451918B2 失效
公开(公告)号：JPH0451918B2
公开(公告)日：1992-08-20
申请号：JP18201283
申请日：1983-09-30
申请人： FUJITSU LTD
发明人： SUZUKI YASUO , HIRAO HIROSHI , SUZUKI YASUAKI
IPC分类号： G11C17/18 , G11C11/417 , G11C11/56 , G11C16/04 , H01L27/10

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