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1. 发明专利

JP2009174936A Crack growth evaluation apparatus and method 有权
标题翻译：裂纹生长评估装置和方法
公开(公告)号：JP2009174936A
公开(公告)日：2009-08-06
申请号：JP2008012272
申请日：2008-01-23
申请人： Fujitsu Ltd , Fujitsu Ten Ltd , 富士通テン株式会社 , 富士通株式会社
发明人： SAKAI HIDEHISA , MORIMUNE KATSUFUMI , MOGI MASANORI , IIKAWA TSUTOMU
IPC分类号： G01N3/32
CPC分类号： G01N3/32 , G01N2203/0016 , G01N2203/006 , G01N2203/0066 , G01N2203/0224
摘要： PROBLEM TO BE SOLVED: To provide a crack growth evaluation apparatus for accurately evaluating a growth of a crack occurring in a continuum. SOLUTION: An element damage determination unit 13 calculates a cumulative value of a damage value using a Coffin-Manson rule for a plurality of finite elements of a continuum based on a result of a stress/distortion analyzing process, and determines whether or not the cumulative value of the damage value is equal to or exceeds a threshold. A calculation unit 15 obtains first correspondence information indicating the correspondence between the number of cycles of a load and a growth rate of a crack occurring in the continuum based on the determination result. A Coffin-Manson rule change unit 17 changes a Coffin-Manson rule based on the first correspondence information and second correspondence information indicating the correspondence between an actual measurement value of the number of cycles of a load applied to the continuum and an actual measurement value of the growth rate of a crack occurring in the continuum at that time. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于精确评估连续体中发生的裂纹的生长的裂纹扩展评估装置。解决方案：元件损坏确定单元13基于应力/失真分析处理的结果，针对连续体的多个有限元使用棺木 - 曼森规则来计算损伤值的累积值，并且确定是否损伤值的累积值不等于或超过阈值。计算单元15基于确定结果，获得指示负载循环次数和连续体中发生的裂纹的生长速度之间的对应关系的第一对应信息。棺木规则改变单元17基于第一对应信息和表示施加到连续体的负载的循环次数的实际测量值与实际测量值之间的对应关系的第二对应信息来改变棺木曼森规则当时连续体发生裂缝的增长速度。版权所有（C）2009，JPO＆INPIT

2. 发明专利

JP2006053747A Substrate deformation prediction device, substrate deformation prediction method and substrate deformation prediction program 有权
标题翻译：基板变形预测装置，基板变形预测方法和基板变形预测程序
公开(公告)号：JP2006053747A
公开(公告)日：2006-02-23
申请号：JP2004234717
申请日：2004-08-11
申请人： Fujitsu Ltd , 富士通株式会社
发明人： TOYABE YOKO , SAKAI HIDEHISA
IPC分类号： G06F17/50
CPC分类号： H05K3/00 , G06F17/5018 , G06F2217/80 , H05K1/0271 , H05K2201/068 , H05K2203/162
摘要： PROBLEM TO BE SOLVED: To provide a substrate deformation prediction device capable of efficiently predicting warping of a printed wiring board.
SOLUTION: In this substrate deformation prediction device 100, an area division processing part 110 divides a substrate to areas of a size according to a wiring pattern density based on Garbor data inputted from an input device 200, an equivalent physical property value calculation processing part 120 calculates an anisotropic physical property value for every wiring direction of each area, and calculates an equivalent physical property value of each divided area based on the calculated anisotropic physical property values. A warping simulation execution processing part 130 predicts the warping of a substrate based on the equivalent physical property values.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：提供能够有效地预测印刷电路板翘曲的基板变形预测装置。解决方案：在该基板变形预测装置100中，区域分割处理部110基于从输入装置200输入的加法数据，将基板划分为与布线图案密度相对应的尺寸的区域，等效物理值计算处理部分120计算每个区域的每个布线方向的各向异性物理特性值，并且基于所计算的各向异性物理性质值来计算每个分割区域的等效物理特性值。翘曲模拟执行处理部130基于等效物理特性值来预测基板的翘曲。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2004354291A Physical property value measuring device and method 有权
公开(公告)号：JP2004354291A
公开(公告)日：2004-12-16
申请号：JP2003154146
申请日：2003-05-30
申请人： Fujitsu Ltd , 富士通株式会社
发明人： SAKAI HIDEHISA , FUKUDA TAKASHI
IPC分类号： G01N25/16
摘要： PROBLEM TO BE SOLVED: To identify an unknown property value of a material accurately, efficiently, and at a low cost. SOLUTION: Concerning a sample 10 including a material whose property value is to be measured, in a camber measuring part 2 of this property value measuring device 1, the temperature of the sample 10 arranged in a sealed container 2a is adjusted by a temperature control part 2b, and the camber at each temperature is measured by a noncontact type laser displacement meter 2c. In a property value identification part 3 of the property value measuring device 1, a predicted value of the camber generated in the sample 10 at each temperature is calculated, and the unknown property value of the material included in the sample 10 is identified by using the predicted value of the camber and a measured value of the camber measured by the camber measuring part 2. Hereby, various unknown property values of an electronic part component such as a printed wiring board can be identified accurately without processing it into a specific shape, and the unknown property values can be identified efficiently at low cost. COPYRIGHT: (C)2005,JPO&NCIPI

4. 发明专利

JPH04219966A SEMICONDUCTOR ELEMENT 失效
公开(公告)号：JPH04219966A
公开(公告)日：1992-08-11
申请号：JP41245790
申请日：1990-12-20
申请人： FUJITSU LTD
发明人： KUWAHARA KIYOSHI , SEYAMA KIYOTAKA , SUMIYOSHI MAKOTO , SAKAI HIDEHISA
IPC分类号： H01L25/18 , H01L25/065 , H01L25/07
摘要： PURPOSE:To enhance the mounting efficiency of a semiconductor element. CONSTITUTION:A plurality of chip holding seats 3 are formed at the inside of a package main body 2 where external terminals 1 are formed on its one face. A semiconductor chip 4 is fixed and bonded to each chip holding seat 3. Said semiconductor chip 4 is connected to the external terminals 1 by using proper means. Said semiconductor chip 4 is sealed with a sealing cap 5.

5. 发明专利

JP2014006908A Meshing method and meshing device 有权
标题翻译：打磨方法和打磨装置
公开(公告)号：JP2014006908A
公开(公告)日：2014-01-16
申请号：JP2013133157
申请日：2013-06-25
申请人： Fujitsu Ltd , 富士通株式会社
发明人： SELVAN GEORGESCU , CHOW PETER , SAKAIRI SHIN , SAKAI HIDEHISA
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F9/4881 , G06F17/5018 , G06F17/5095 , G06T17/005 , G06T17/20 , G06T19/20 , G06T2219/2008
摘要： PROBLEM TO BE SOLVED: To provide a high speed extendable tool capable of meshing a complicated CAD model without any user's interposition.SOLUTION: There is provided a meshing device which is configured in such a manner that one or more serial meshing units 1-8 are used to execute a decoupled parallel meshing processes on all parts of a CAD assembly model, and which is used for a CAD or CAE system. The meshing device includes a meshing parameter setting unit 2 which is configured to automatically set an input parameter of the meshing process for each of parts to be processed, and which operates so as to use live execution time information associated with meshing processes on related parts for determining one or more input parameters.
摘要翻译：要解决的问题：提供能够在没有任何用户插入的情况下啮合复杂CAD模型的高速可伸缩工具。解决方案：提供了一种啮合装置，其被配置成使得一个或多个串联网格单元1-8 用于在CAD装配模型的所有部件上执行解耦平行啮合过程，并用于CAD或CAE系统。啮合装置包括啮合参数设定单元2，其被配置为自动设置每个要处理的部件的啮合处理的输入参数，并且其操作以使用与相关部件的啮合处理相关联的实时执行时间信息确定一个或多个输入参数。

6. 发明专利

JP2010087082A Semiconductor device, substrate design method, and substrate design apparatus 有权
标题翻译：半导体器件，衬底设计方法和衬底设计设备
公开(公告)号：JP2010087082A
公开(公告)日：2010-04-15
申请号：JP2008252348
申请日：2008-09-30
申请人： Fujitsu Ltd , 富士通株式会社
发明人： MATSUI NORIYUKI , SAKAI HIDEHISA
IPC分类号： H01L23/12
CPC分类号： H01L23/49816 , H01L23/3677 , H01L23/49827 , H01L23/49838 , H01L2924/0002 , H01L2924/15311 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device, and a method and apparatus for designing a substrate, reducing stress and distortion of electrodes provided in chip peripheral parts of a substrate.
SOLUTION: The semiconductor device includes a substrate, and a semiconductor chip mounted on the substrate. The substrate is provided with a plurality of holes. On the surface of substrate, the density of holes provided in the first region of the substrate which faces the periphery of the semiconductor chip, is higher than that of the holes provided in a region of the substrate other than the first region.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件，以及用于设计衬底的方法和设备，减少了设置在衬底的芯片周边部分中的电极的应力和变形。解决方案：半导体器件包括衬底和安装在衬底上的半导体芯片。基板设置有多个孔。在基板的表面上，设置在基板的面向半导体芯片的周边的第一区域中的孔的密度高于设置在除了第一区域之外的基板的区域中的孔的密度。版权所有（C）2010，JPO＆INPIT

7. 发明专利

JP2010056162A Semiconductor device and circuit board assembly 审中-公开
标题翻译：半导体器件和电路板组件
公开(公告)号：JP2010056162A
公开(公告)日：2010-03-11
申请号：JP2008217150
申请日：2008-08-26
申请人： Fujitsu Ltd , 富士通株式会社
发明人： MATSUI NORIYUKI , SAKAI HIDEHISA
IPC分类号： H01L23/12
CPC分类号： H05K3/3436 , H01L23/3128 , H01L23/49816 , H01L23/49838 , H01L2224/16225 , H01L2224/48227 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/3511 , H05K1/0271 , H05K2201/10734 , Y02P70/613
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device or the like whose connecting reliability with a circuit board is improved, while allowing the formation of multiple terminals without using any special material.
SOLUTION: The semiconductor device 3 is equipped with: semiconductor elements 31; an element fixing board 32 having a front surface F and a rear face B, in which the semiconductor elements 31 are fixed on the front surface F; and a plurality of coupling members 33 arranged on the rear face B of the element fixing board 32 in a two-dimensional shape for coupling a circuit board 2 and the element fixing board 32. The semiconductor device is also characterized in that the coupling members 33 are arranged inside and outside a coupling prohibited area 321 on the rear face B while avoiding the coupling prohibited area 321 which overlaps a contour of the semiconductor elements 31 in a plane view and makes a round and is wider than a width in which the coupling members 33 can be arranged.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种改善了与电路板的连接可靠性的半导体器件等，同时允许形成多个端子而不使用任何特殊材料。解决方案：半导体器件3配备有：半导体元件31; 具有前表面F和后表面B的元件固定板32，其中半导体元件31固定在前表面F上; 以及在元件固定板32的后表面B上以用于连接电路板2和元件固定板32的二维形状布置的多个连接件33.其特征还在于连接件33 布置在背面B上的联接禁止区域321的内部和外部，同时避免与平面图中的半导体元件31的轮廓重叠的联接禁止区域321，并且形成圆形并且宽度大于连接构件 33可以安排。版权所有（C）2010，JPO＆INPIT

8. 发明专利

JP2007011601A Multiscale analyzer 有权
标题翻译：多尺度分析仪
公开(公告)号：JP2007011601A
公开(公告)日：2007-01-18
申请号：JP2005190157
申请日：2005-06-29
申请人： Fujitsu Ltd , 富士通株式会社
发明人： SAKAI HIDEHISA
IPC分类号： G06F17/50
CPC分类号： G06F17/5018
摘要： PROBLEM TO BE SOLVED: To improve the accuracy of analysis results to be obtained without significantly changing a program for a zooming analysis using a finite element method.
SOLUTION: The analyzer executes a global analysis of a structure (step 401) and calculates strain at each nodal point from the strain of each element of a global model (step 402). Next, a secondary coefficient of a quadratic function showing the displacement in each nodal point of a micro model is calculated from the strain of each nodal point (step 403). A constant term and a primary coefficient are calculated from the displacement of each nodal point of the global model (step 404). The displacement at each boundary nodal point of the micro model is calculated by using the quadratic function (step 405). Then, a micro analysis is executed (step 406).
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提高分析结果的准确性，而不用显着地改变使用有限元法的变焦分析的程序。解决方案：分析器执行结构的全局分析（步骤401），并从全局模型的每个元素的应变计算每个节点处的应变（步骤402）。接下来，从每个节点的应变计算显示微模型的每个节点中的位移的二次函数的二次系数（步骤403）。从全局模型的每个节点的位移计算常数项和主要系数（步骤404）。通过使用二次函数计算微型模型的每个边界节点处的位移（步骤405）。然后，执行微分析（步骤406）。版权所有（C）2007，JPO＆INPIT

9. 发明专利

JPH07245131A PRESS FIT PIN 失效
公开(公告)号：JPH07245131A
公开(公告)日：1995-09-19
申请号：JP3507894
申请日：1994-03-04
申请人： FUJITSU LTD
发明人： SAKURAOKA MASAHIKO , OKUYAMA TAKESHI , SAKAI HIDEHISA , NISHIYAMA TAKESHI
IPC分类号： H01R9/16 , H01R12/58 , H01R13/04 , H01R13/40 , H01R13/42 , H01R9/09
摘要： PURPOSE:To provide a press fit pin which can work well with through hole designed in a smaller diameter. CONSTITUTION:A fit pin has a right beam part 41, left beam part 42, and cross part 43 to tie them together in their part near the bottoms. The can deflect in the direction of arrow A resiliently with a spring constant K1. The beam parts 41, 42 on both sides are arranged as forming a V and have major beam parts 41a, 42a extending upward the cross part 43 and minor beam parts 41b, 42b extending down from the cross part 43. The major beam parts 41a, 42a can deflect in the direction shown by arrows B, C resiliently with a spring constant K2. The minor beam parts 41b, 42b can deflect in the directions shown by arrows D, E with a spring constant K3. The three spring constants should be related as K2

10. 发明专利

JP2014106774A Analysis method, analysis device, and analysis program 有权
标题翻译：分析方法，分析装置和分析程序
公开(公告)号：JP2014106774A
公开(公告)日：2014-06-09
申请号：JP2012259774
申请日：2012-11-28
申请人： Fujitsu Ltd , 富士通株式会社
发明人： URAKI YASUSHI , ISHIKAWA SHIGEO , KUBOTA TETSUYUKI , FURUYA SACHIKO , NAKATATE MASAMI , INAGAKI KAZUHISA , IMAI KANAKO , SAKAI HIDEHISA , YAMAOKA NOBUYOSHI , NIIDE TAKAMASA , MEGURO MASAKAZU
IPC分类号： G06F17/50
摘要： PROBLEM TO BE SOLVED: To legibly display a peak value included in an analysis output of a parallelized analysis processing.SOLUTION: An analysis device 1 includes: a management part 10 that divides an analysis object into a plurality of analysis regions; a plurality of calculation part 20 that respectively calculates an analysis value of the analysis regions, divides the successively arranged analysis value into a plurality of sections, extracts a maximum value of the analysis value of the respective region, and extracts the maximum value of a boundary section where the maximum value changes from increase to decrease, as a peak value of the analysis region; and the management part 10 displays a marker showing the peak value on the extracted analysis region.
摘要翻译：要解决的问题：清楚地显示并行化分析处理的分析输出中包括的峰值。解析：分析装置1包括：管理部分10，其将分析对象分割成多个分析区域; 分别计算分析区域的分析值的多个计算部20将连续排列的分析值分割为多个区间，提取各区域的分析值的最大值，提取边界的最大值最大值从增加到减少的部分，作为分析区域的峰值; 并且管理部分10显示在提取的分析区域上显示峰值的标记。

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