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    • 1. 发明专利
    • Light receiving circuit having avalanche photodiode protection circuit
    • 具有AVALANCHE光电保护电路的光接收电路
    • JPH11275755A
    • 1999-10-08
    • JP7075098
    • 1998-03-19
    • Fujitsu Ltd富士通株式会社
    • OKUMA YOSHINORIMIYAKI YUJI
    • H02H3/20H02H9/04H03F3/08H04B10/079H04B10/40H04B10/50H04B10/60H04B10/67H04B10/69H04B10/80H04B10/04H04B10/06H04B10/14H04B10/26H04B10/28
    • PROBLEM TO BE SOLVED: To prevent destruction owing to the overvoltage of a photodiode in the supply process of power voltage, by installing an avalanche photodiode for a bias control circuit, and detecting that applied voltage is overvoltage.
      SOLUTION: A Zener diode D1 is connected to an avalanche photodiode APD in parallel. Namely, the cathode of the Zener diode D1 is connected to the cathode of the avalanche photodiode APD and the anode of the Zener diode D1 is connected. The Zener diode D1 which is thus connected in parallel constitutes an avalanche photodiode protection circuit PR1. Thus, current flows from a power source to ground through resistors R1 and R2 and the Zener diode D1. Since the voltage of a connection point V1 drops as a result, the destruction of the avalanche photodiode APD owing to overvoltage is prevented.
      COPYRIGHT: (C)1999,JPO
    • 要解决的问题:为了防止在电源电压供给过程中由于光电二极管的过电压而造成的破坏,通过安装用于偏置控制电路的雪崩光电二极管,并且检测施加的电压是过电压。 解决方案:齐纳二极管D1并联连接到雪崩光电二极管APD。 也就是说,齐纳二极管D1的阴极连接到雪崩光电二极管APD的阴极,并且齐纳二极管D1的阳极被连接。 并联连接的齐纳二极管D1构成雪崩光电二极管保护电路PR1。 因此,电流从电源通过电阻器R1和R2以及齐纳二极管D1流到地。 由于连接点V1的电压因此下降,所以防止了由过电压引起的雪崩光电二极管APD的破坏。
    • 2. 发明专利
    • OPTICAL VARIATION RESISTANCE TESTING EQUIPMENT
    • JPH06160238A
    • 1994-06-07
    • JP31176992
    • 1992-11-20
    • FUJITSU LTD
    • NAGAKUBO YASUNARIOKUMA YOSHINORI
    • G01M11/00H04B10/07H04B10/079H04B10/2507H04B10/54H04B10/556H04B10/08
    • PURPOSE:To provide an optical variation resistance testing equipment for assisting measurement of optical variation resistance, representing stability at receiving terminal in terms of bit error, against variation of transmission characteristics caused by mechanical impact applied on an operating optical transmission line in which mechanical impact being applied on an optical fiber can be simulated positively and accurately. CONSTITUTION:The optical variation resistance testing equipment comprises means 11 for generating a signal corresponding to variation of transmission characteristics of an optical transmission line caused by mechanical impact applied thereon, and an indirect modulating means 13 for modulating a reference optical signal, corresponding to an optical signal put on the optical transmission line at a transmission terminal while being modulated according to transmission information, with a signal generated from the signal generating means 11 according to the transmission system for that optical transmission system thus simulating variation of optical transmission characteristics and then assisting measurement of optical variation resistance which represents stability of bit error rate at receiving terminal.
    • 3. 发明专利
    • OPTICAL OUTPUT CONTROL CIRCUIT
    • JPH02292882A
    • 1990-12-04
    • JP11216389
    • 1989-05-02
    • FUJITSU LTD
    • OKUMA YOSHINORIYAMANE KAZUOWADA TETSUO
    • H04B10/293H01S5/068H04B10/07H04B10/564H04B10/572
    • PURPOSE:To prevent output light from varying in level due to the change of a bias current caused by temperature change by a method wherein a variable offset voltage generating section which enables an offset voltage to change directly proportional to the temperature change is provided. CONSTITUTION:A variable offset voltage generating section 21 is composed of two diodes d and two potential dividing resistors R and R' (adjustable), where the characteristic inclinations of a reference voltage Vr(=Vm+Vo) at temperature of, for instance, 5 deg.C, 25 deg.C, and 55 deg.C are made different from each other. Concretely, an offset voltage Vo as one of factors which determine the reference voltage Vr is changed corresponding to the temperature change. The property of the diode d that its forward voltage drop is temperature-dependent is used for this purpose, for instance, it has a temperature characteristic of -2mV/ deg.C. A comparator 11 is a comparator formed of an operational amplifier, a bias control section 12 is composed of transistors, a pulse current control section 13 is formed of a pair of differential transistors, and a transistor Q is connected to the emitters of these transistors to serve as a common current source. The output of the comparator 11 is inputted into the base of the transistor Q through the intermediary of an amplifier A.
    • 7. 发明专利
    • SEMICONDUCTOR LASER DEVICE
    • JPS63204778A
    • 1988-08-24
    • JP3583787
    • 1987-02-20
    • FUJITSU LTD
    • MORI MASAKAZUOKUMA YOSHINORISUZUKI KAZUHIROYAMANE KAZUO
    • H01S5/06H01S3/23H01S5/068
    • PURPOSE:To suppress the amount of dispersion of an emission delay time in the case of superspeed modulation of a semiconductor laser by mounting separately a light source for injecting a direct current light consisting of a light emission diode and the like in a semiconductor emission region and by driving its light source for injecting the direct current light that is independent of a semiconductor laser, thereby using a direct current. CONSTITUTION:In addition to a semiconductor laser 11, a light source 13 for injecting a direct current light corresponding to a direct current bias emission source is mounted and a direct current light 14 out of the light source 13 is injected in an emission region 12 of the laser 11 as a seed for generating a laser beam 15 and then the direct light 14 out of the light source 13 is independently suppressed. In this way, the light source 13 is so less dependent to a temperature in comparison with the semiconductor laser's dependency to the temperature that its light source 13 is not affected by temperature changes or characteristic deterioration of the element itself and stablly controls the amount of dispersion of an emission delay time in the semiconductor laser.
    • 8. 发明专利
    • PULSE AMPLIFIER
    • JPS62217712A
    • 1987-09-25
    • JP5946486
    • 1986-03-19
    • FUJITSU LTD
    • YAMANE KAZUOMORI MASAKAZUTSUDA TAKASHIOKUMA YOSHINORISUZUKI KAZUHIRO
    • H03K5/02H03G3/10
    • PURPOSE:To control variably the pulse amplitude without changing the pulse width by impressing negative logic input pulse to a gate electrode of a FET so as to vary a gate-source voltage in a voltage range higher than the pinch-off voltage. CONSTITUTION:In selecting the gate-source voltage impressed to the FET 3 to a voltage V(GS11) higher than the pinch-off voltage VP0, one portion of an input pulse Pi3 is cut off and the pulse amplitude of an output pulse P03 is A3 and the pulse width is W3. On the other hand, in impressing a voltage V(GS12) higher than the voltage V(GS11) to the FET 3, the amplitude A4 of an output pulse P04 and the pulse width W4 have the relation of A3 W4. In inputting an output of the FET 3 to a FET 7, the '0' level of the input pulse is arranged to a constant value V(GSC) by a clamp diode 6. Thus, the same portion of the pulses P04, P03 is cut off by the pinch off voltage VP0 of the FET, the pulse widths W31, W41 of the pulses P003, P004 are nearly equal and the pulse amplitudes are A31, A41.