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1. 发明专利

JPS6325372B2 失效
公开(公告)号：JPS6325372B2
公开(公告)日：1988-05-25
申请号：JP4827781
申请日：1981-03-31
申请人： FUJITSU LTD
发明人： SAKAI KENJI , AOKI TAKASHI , NAKAO SADAO
IPC分类号： G06F9/22 , G06F9/26 , G06F9/42

2. 发明专利

JPS59133656A Data processing system 失效
标题翻译：数据处理系统
公开(公告)号：JPS59133656A
公开(公告)日：1984-08-01
申请号：JP765083
申请日：1983-01-20
申请人： Fujitsu Ltd
发明人： NAKAO SADAO
IPC分类号： G06F3/06 , G06F13/00 , G06F13/38
CPC分类号： G06F13/00
摘要： PURPOSE:To improve the throughput proper to a device, by recording data of a transfer destination temporarily in a buffer area of a control part and reading out it to transfer it to another auxiliary recording device. CONSTITUTION:A buffer memory 6m is provided as a disk cache memory in a magnetic disk controller 6. A magnetic disk device 4 and a magnetic tape device 7 are connected through the controller 6, and data is transferred between devices 4 and 7 through the controller. In this case, data is transferred from the device and is read into the buffer 6m of the controller 6, and data in the buffer 6m is transferred and written in the device 7. Thus, data is transferred from the device 4 to the device 7 through the controller 6 within the capacity where the buffer 6m of the controller 6 can store data, and data is copied. Thus, data is transferred without passing a main storage device 2 to make it possible that the device performs essential processings.
摘要翻译：目的：通过将传送目的地的数据暂时记录在控制部分的缓冲区中，并将其读出并传送到另一个辅助记录装置，来提高设备的吞吐量。构成：在磁盘控制器6中作为磁盘高速缓冲存储器提供缓冲存储器6m。磁盘装置4和磁带装置7通过控制器6连接，数据通过控制器在装置4和7之间传送。在这种情况下，数据从设备传送并被读入控制器6的缓冲器6m中，缓冲器6m中的数据被传送并写入设备7.因此，数据从设备4传送到设备7 在控制器6的缓冲器6m可以存储数据的容量内通过控制器6，并复制数据。因此，在不通过主存储装置2的情况下传送数据，使得设备可以执行必要的处理。

3. 发明专利

JPS57209541A DATA PROCESSOR HAVING INSTRUCTION ROM 失效
公开(公告)号：JPS57209541A
公开(公告)日：1982-12-22
申请号：JP9491281
申请日：1981-06-19
申请人： FUJITSU LTD
发明人： NAKAO SADAO
IPC分类号： G06F9/06 , G06F11/00
摘要： PURPOSE:To add a plurality of instructions to correct a signal instruction on an instruction ROM, by providing a correction processing block to correct the contents of the instruction ROM. CONSTITUTION:Address information corresponding to an address area of an ROM1 read out from a memory 6 and the content of the address register 2 are compared at a comparison circuit 7. When they are coincident, gate circuits 11, 12, 14 and 15 are set and a gate circuit 13 is reset. When control information is provided, the readout of instructions after a plurality of times of correction is instructed. In this case, a branch address B is set to an address register 9 at correction via the gate 15. Accessing is made to a memory 8 with the contents of the address register 9 at correction.

4. 发明专利

JPS5165847A Warikomiseigyohoshiki 失效
公开(公告)号：JPS5165847A
公开(公告)日：1976-06-07
申请号：JP13989774
申请日：1974-12-04
申请人： Fujitsu Ltd
发明人： KIKUCHI JOJI , NAKAO SADAO
IPC分类号： G06F9/22 , G03G21/00 , G06F9/46 , G06F9/48

5. 发明专利

JPS5848152A SELF-DIAGNOSING METHOD 失效
公开(公告)号：JPS5848152A
公开(公告)日：1983-03-22
申请号：JP14657581
申请日：1981-09-17
申请人： FUJITSU LTD
发明人： NAKAO SADAO , SUGIYAMA ITSUMI
IPC分类号： G06F11/22 , G01R31/3185 , G06F11/267
摘要： PURPOSE:To allow an exclusive arithmetic circuit which is used only for the execution of specific instructions to self-diagnose all the time, by inputting the counted value of a counter for diagnostic data generation as diagnostic data to the arithmetic circuit, and performing arithmetic and collation. CONSTITUTION:Before using an exclusive arithmetic device HSA, a central processing unit sets a control bit CB to 1 and when the CB is set to 0, the central processing unit enters into a diagnostic mode and a counter for diagnostic data goes by one successively to perform counting from an all-0 value to an all-1 value. While the CB is 0, a multiplexer MPX is switched to input the data of the CTR to arithmetic units ALU1 and ALU2, so three-divided data A, B, and DF of the counter CTR are inputted to the ALU1 and ALU2 together. A comparator COMP compares them mutually and when they do not coincide with each other, an error signal ER is generated. The capacity of the counter CTR is equal to data width and it adds by one successively, so a diagnosis is performed by combinations of all input patterns.

6. 发明专利

JPS57162031A ADDRESS STACK CONTROL SYSTEM 失效
公开(公告)号：JPS57162031A
公开(公告)日：1982-10-05
申请号：JP4827781
申请日：1981-03-31
申请人： FUJITSU LTD
发明人： SAKAI KENJI , AOKI TAKASHI , NAKAO SADAO
IPC分类号： G06F9/22 , G06F9/26 , G06F9/42
摘要： PURPOSE:To lighten the burden of a program generating person, and to easily change a return instruction or a routine of the return instruction, by automatically storing the control information in a stack, and making it unnecessary that the generating person gives the return instruction over again. CONSTITUTION:A data for generating an address data of a main routine and subroutines 2, 3 stored in a microprogram storage device (CS) 6 from a computer is supplied to a CS red address generating circuit 5. In this circuit 5, an address of the CS 6 is generated, and a stack point being a write and read-out address is stored in a stack 4. Also, the address control information is provided to the stack 4 and the circuit 5, and an address of the control information generated by the circuit 5 is stored in address control information storage areas 7-0-7-n. In this state, the routine 1 is executed, and after that, when the control is shifted to the subroutines 2, 3, a return address to the routines 2, 3 and the address control information informing that the control is shifted after the return instruction has been issued are stored in the stack 4.

7. 发明专利

JPS58114113A AUTOMATIC SAVE CONTROLLING SYSTEM FOR ABNORMAL TEMPERATURE OF COMPUTER 失效
公开(公告)号：JPS58114113A
公开(公告)日：1983-07-07
申请号：JP21400781
申请日：1981-12-26
申请人： FUJITSU LTD
发明人： SUGIYAMA ITSUMI , NAKAO SADAO
IPC分类号： G06F11/00 , G06F1/20 , G06F1/30
摘要： PURPOSE:To prevent the system breakdown, by not only saving information required for restoration into a non-volatile memory but also increasing the cooling capability of a capability variable cooling means when a temperature detector detects a temperature higher than a prescribed value and restoring the processing when the temperature is lowered to a value lower than the prescribed value. CONSTITUTION:Plural temperature sensors S and cooling fans 3 where the cooling capability is variable are arranged in a CPU having a print aggregate of an electronic circuit of a computer 1. A disc device 6 is provided on the outside of the computer 1, and the print aggregate 2 is connected to the disc device 6, and electric power is supplied to the print aggregate 2 by a power supply device 4. When each sensor S detects a temperature higher than a prescribed value, a power supply controller 5 interrupts the print aggregate 2 and saves data required for restoration onto the disc device 6 and controls the device 4 to increase the capability of each fan 3, and the processing is restored when the temperature is lowered to a value lower than the prescribed value; and thus, the system breakdown is prevented.

8. 发明专利

JPS586970B2 失效
公开(公告)号：JPS586970B2
公开(公告)日：1983-02-07
申请号：JP16502979
申请日：1979-12-19
申请人： FUJITSU LTD
发明人： NAKAO SADAO , HANADA TADASHI , MARUO AKIHIRO
IPC分类号： G06F9/32

9. 发明专利

JPS5687142A SEQUENCE CONTROL SYSTEM FOR ROM ADDRESS 失效
公开(公告)号：JPS5687142A
公开(公告)日：1981-07-15
申请号：JP16502979
申请日：1979-12-19
申请人： FUJITSU LTD
发明人： NAKAO SADAO , HANADA TADASHI , MARUO AKIHIRO
IPC分类号： G06F9/32
摘要： PURPOSE:To ensure a highly efficient execution for the data process to the address information with multiplex branch when the multiplex branch address is read out, by giving a control so as to secure an access for the address of the instruction which is directly required. CONSTITUTION:Both the address information and the branch address selection information which designates the multiplex branch address are stored in the ROM1, and the function to select the destination of the multiplex branch address is given to the branch address selection information. The address information for access is written into the ROM1 after partitioned into several devices. At the same time, the address register 2 containing the written address destination is provided along with the decoder 5 which decodes the branch address selection information of the ROM1. Then the output of the decoder 5 is applied to the next ROM address control circuit 4, and the address to be written into the register 2 is turned into the address relating the address written into the register 2 in accordance with the output of the decoder 5 or into the address obtained by combining the divided address information through a selection. Thus a direct access is possible for the address of the required instruction.

10. 发明专利

JPS5343444A PARITY CHECK ADDER 失效
公开(公告)号：JPS5343444A
公开(公告)日：1978-04-19
申请号：JP11838576
申请日：1976-10-01
申请人： FUJITSU LTD
发明人： NAKAO SADAO
IPC分类号： G06F7/38 , G06F7/00 , G06F7/499 , G06F7/508 , G06F11/10
摘要： PURPOSE:To decrease the number of the parts as well as to simplify the assembling processes by constituting an adder with an arithmetic logical circuit consisting of MSI and a look-ahead carry generator comprising MSI with addition of a carry growing circuit.

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