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1. 发明专利

JPS63306639A MASTER SLICE TYPE SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPS63306639A
公开(公告)日：1988-12-14
申请号：JP14249387
申请日：1987-06-08
申请人： FUJITSU LTD
发明人： MIURA DAISUKE
IPC分类号： H01L27/118 , H01L21/82 , H01L21/8238 , H01L27/08 , H01L27/092 , H01L27/10 , H03K19/177
摘要： PURPOSE:To improve the utilization factor of basic cells when a logic unit cell, a RAM and a ROM are constituted respectively by a method wherein the basic cell is composed of a CMOS forming part and an NMOS forming part. CONSTITUTION:A basic cell is composed of a CMOS forming part 10a and an NMOS forming part 10b. The CMOS forming part 10a is composed of gate electrodes 11 and 12 shown by frosted parts in the figure, a PMOS part 13 and an NMOS part 14. The PMOS part 13 is composed of P-type parts 13a and 13b and a P-type part 13c. The NMOS part 14 is composed of N-type part 14a and 14b and an N-type part 14c. The NMOS forming part 10b is composed of gate electrodes 15 and 16 shown by frosted parts in the figure and NMOS parts 17 and 18. With this constitution, when a logic unit is constituted by the CMOS forming parts 10a, the NMOS forming parts 10b can be utilized as wiring channels. Therefore, the utilization factor of the basic cells when the logic unit cell, a RAM and a ROM are formed respectively can be improved.

2. 发明专利

JP2003058591A Method and device for automatically designing wiring between circuit blocks of integrated circuit, and program for performing the method 有权
标题翻译：用于自动设计集成电路的电路块之间的接线的方法和设备，以及用于执行该方法的程序
公开(公告)号：JP2003058591A
公开(公告)日：2003-02-28
申请号：JP2001250924
申请日：2001-08-22
申请人： Fujitsu Ltd , 富士通株式会社
发明人： ARAKAWA TOSHIO , MIURA DAISUKE , OKAMOTO MASAYUKI , NAGASAKA MITSUAKI , HONDA HIROYUKI , YOSHIDA SHUJI , KOBAYASHI KENJI , YOSHIDA KENJI
IPC分类号： G06F17/50 , H01L21/82
CPC分类号： G06F17/5077
摘要： PROBLEM TO BE SOLVED: To reduce a wiring area necessary for wiring between blocks of an integrated circuit.
SOLUTION: In the automatic wiring designing method for automatically connecting inter-block wiring arranged between a first circuit block and a second circuit block with terminals formed along the opposite sides of the first and second circuit blocks, the terminals are sorted with a terminal width (S2), a terminal is selected in the order of a large terminal width, and the terminal is connected to inter-block wiring of a network being the same as that of the terminal (S3 to S11). In other performance examples, terminals to be connected to power supply wiring among the terminals are sorted with the value of current caused to flow to the terminals, and the terminal is selected in the order of the current value with a large value, and is connected to inter- block wiring being the same net as that of the terminal.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：减少集成电路块之间布线所需的布线面积。解决方案：在用于自动连接布置在第一电路块和第二电路块之间的块间布线的自动布线设计方法中，具有沿着第一和第二电路块的相对侧形成的端子，端子以端子宽度 S2），以大端子宽度的顺序选择端子，并且将端子连接到与端子相同的网络的块间布线（S3至S11）。在其他性能示例中，要连接到端子之间的电源布线的端子按照流向端子的电流值进行分类，并且以大值的当前值的顺序选择端子，并且连接来阻断与终端相同网络的接线。

3. 发明专利

JP2002312160A BINARY CARRY ARITHMETIC CIRCUIT, HALF ADDITION CIRCUIT AND INCREMENTER USING THE SAME, BINARY BORROW ARITHMETIC CIRCUIT, HALF SUBTRACTION CIRCUIT AND DECREMENTER USING THE SAME 失效
公开(公告)号：JP2002312160A
公开(公告)日：2002-10-25
申请号：JP2001116174
申请日：2001-04-13
申请人： FUJITSU LTD
发明人： YOSHIDA SHUJI , MIURA DAISUKE , ARAKAWA TOSHIO , NAGASAKA MITSUAKI , YOSHIDA KENJI , HONDA HIROYUKI , KOBAYASHI KENJI , OKAMOTO MASAYUKI
IPC分类号： G06F7/50 , G06F7/505 , G06F7/506
摘要： PROBLEM TO BE SOLVED: To achieve higher speed, while maintaining the advantage of a ripple carry type, having a small-scale circuit. SOLUTION: In this incrementer, binary carry arithmetic circuits 20 of half addition circuits, other than one for the lowest digit, each having a transfer gate 212 turned on when an input bit A2 is active and supplied at its data input end with a carry *C2 from a lower digit, and a transistor 23 turned on, when the input bit A2 is inactive and connected between a power potential VDD having a logical value equal to that of the inactive potential of the carry *C2 and a data output end of the transfer gate 212. The signal of the output end is a carry *C3 to a higher column. Since transfer gates 212 to 214 of the binary carry arithmetic circuits, other than that for the lowest column, are connected in series and the respective transfer gates are on-off controlled simultaneously by input bits, a carry from the lowest column can be propagated through the sequence of transfer gates at a high speed.

4. 发明专利

JP2000150781A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JP2000150781A
公开(公告)日：2000-05-30
申请号：JP32504398
申请日：1998-11-16
申请人： FUJITSU LTD
发明人： MIURA DAISUKE , INADA YASUHIKO , KIHARA FUKUJI , HONDA HIROYUKI , KOIKE TORU , YOSHIDA SHUJI , ARAKAWA TOSHIO
IPC分类号： H01L27/04 , H01L21/822
摘要： PROBLEM TO BE SOLVED: To appropriately interface to other diversified integrated circuits to be connected by performing specific wiring in a transistor region and composing an interface circuit that is required for an I/O terminal part. SOLUTION: In a microprocessor 1, a CPU 21, a control circuit 22, a RAM 23, and an EPROM 24 are provided on a chip 2, and at the same time an annular I/O terminal part 3 is provided around the chip 2. Then, the I/O terminal part 3 is provided with a transistor region 31 and a bonding pad 32, the transistor region 31 is arranged inside the chip 2, and the bonding pad 32 is arranged outside the chip 2. In this manner, cell structure with a specific transistor is wired at the transistor region 31, thus composing an interface circuit requiring for each I/O terminal part 3.

5. 发明专利

JPH0265157A MASTER SLICE TYPE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0265157A
公开(公告)日：1990-03-05
申请号：JP21670688
申请日：1988-08-30
申请人： FUJITSU LTD
发明人： MIURA DAISUKE
IPC分类号： H01L21/822 , H01L21/82 , H01L27/04 , H01L27/118
摘要： PURPOSE:To increase bus driving capacity without extension of a driver by wiring a drive transistor to a transistor within an unused I/O cell in an I/O cell region as to form it. CONSTITUTION:As a necessary logic system can be constituted within one chip in case of high integration in a master slice type LSI, unused ones arise in I/O cell regions for interface with the outside. Now, in a master slice type IC device with a master chip 1, where a basic cell 2 region, a wiring channel 3, and an I/O cell 4 region are formed in unwired conditions, logical blocks 5, 7, and 9, where an optional variable wiring pattern is provided in each region on the master chip 1, an internal bus 11, and a bus driver 13 having a drive transistor, a drive master is formed by wiring it to elements 22 and 23 within unused cells 24 inside the I/O cell 4 region. According to this constitution, by utilizing a vacant I/O cell effectively a bus driver of large driving capacity can be obtained.

6. 发明专利

JPH01112749A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH01112749A
公开(公告)日：1989-05-01
申请号：JP26930387
申请日：1987-10-27
申请人： FUJITSU LTD
发明人： MIURA DAISUKE
IPC分类号： H01L21/82 , H01L21/3205 , H01L23/52 , H01L27/118
摘要： PURPOSE:To prevent any crosstalk from being produced between first layer wirings and third layer wirings by forming the third layer wirings having a pitch specified obliquely with respect to the first layer wirings and second layer wirings, both latter wirings being formed longitudinally and transversely at predetermined pitches, said third layer wirings being further defined to pass over intersections between said first and second wirings. CONSTITUTION:For first and second layer wirings 11 and 21, the first ones 11 are arranged longitudinally with a pitch of (a), and the second ones 21 are arranged transversely with a pitch of (b). In addition, third layer wirings 31 are arranged so that they pass over intersections between the first and second layer wirings and extend obliquely. With such arrangement of the third layer wirings 31, their pitch is given as being 2ab/(a +b ) . Further, via holes 51, 52 are provided for connecting the third layer wirings 31, and the first and second layer wirings 11, 21. There is no parallel part between the first and third layer wirings 11 and 31, thus preventing any crosstalk from being produced.

7. 发明专利

JP2001332626A METHOD OF DESIGNING SEMICONDUCTOR IC 失效
公开(公告)号：JP2001332626A
公开(公告)日：2001-11-30
申请号：JP2000153695
申请日：2000-05-24
申请人： FUJITSU LTD
发明人： INADA YASUHIKO , MIURA DAISUKE , OKAMOTO MASAYUKI , NAGASAKA MITSUAKI , ARAKAWA TOSHIO
IPC分类号： G06F17/50 , H01L21/82 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To provide a method of designing a semiconductor IC, which can shorten the time for designing a circuit including a sequential circuit. SOLUTION: The method of designing a semiconductor IC comprises a step of preparing cells, each including flip-flop circuits and spare transistors, a step of designing the circuit using these cells, and a step of timing adjustment, if it is necessary in the flip-flop circuits, by connecting the spare transistors to the flip-flop circuits.

8. 发明专利

JPH05183407A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH05183407A
公开(公告)日：1993-07-23
申请号：JP73592
申请日：1992-01-07
申请人： FUJITSU LTD
发明人： MIURA DAISUKE
IPC分类号： H01L21/8234 , H01L27/088 , H03K5/13 , H03K5/133 , H03K5/134
摘要： PURPOSE:To easily attain the adjustment of the change in the delay time even after the layout by increasing/decreasing number of transistors(TRs) connected in series through the switch ON/OFF. CONSTITUTION:m-Sets of 1st transistors(TRs) Q11-Q1m and m-sets of 2nd TRs Q21-Q2m of the different conduction type are connected directly. Then m-sets of 2nd switches SW11-SW1m and m-sets of 2nd switches SW21-SW2m are provided to the device. Through the constitution above, number of the TRs Q11-Q1m connected in series is substantially reduced depending on number of switches selected to connect sources of the TRs Q11-Q1m to a high potential power supply among the switches SW21-SW2m. Similarly, number of the TRs Q21-Q2m connected in series is substantially reduced in response to number of the switches SW21- SW2m.

9. 发明专利

JPH05129435A SEMICONDUCTOR LOGIC CELL LIBRARY FORMING EQUIPMENT 失效
公开(公告)号：JPH05129435A
公开(公告)日：1993-05-25
申请号：JP28644791
申请日：1991-10-31
申请人： FUJITSU LTD
发明人： MIURA DAISUKE
IPC分类号： H01L21/82 , G06F17/50
摘要： PURPOSE:To update and form a cell library in a short time, eliminate the delay of logic design, and develop a new product, by sequentially operating and obtaining logic cell library information only by obtaining basic data of elements necessary for forming a circuit, and storing results in a library. CONSTITUTION:From a device simulator 1, three-dimensional part structure of an element for forming an LSI is inputted, and capacitance values per unit area of metal wiring and polysilicon wiring are obtained. As the parameter of a layout verification tool 2, values like actual capacitance extracted from a mask pattern 7 and actual length of transistor size are determined, the capacitance value of an input terminal and the transistor size of an output terminal are obtained, and these values are written in a storage device 3. A circuit simulator 4 performs operation by using the output of the storage device 3 and the output of test specification 8. A computer 5 calculates the delay time between an input and an output, on the basis of the output of the circuit simulator 4, devices the delay time into basic delay time and load capacity dependent coefficient, and writes them in a logic cell library.

10. 发明专利

JPH04216142A RECEIVED DATA INSPECTING DEVICE 失效
公开(公告)号：JPH04216142A
公开(公告)日：1992-08-06
申请号：JP40291990
申请日：1990-12-17
申请人： FUJITSU LTD
发明人： MIURA DAISUKE
IPC分类号： G06F11/10 , H03M13/00
摘要： PURPOSE:To realize a received data inspecting device which checks the parity of receive serial data and reads out data at a high speed without enlarging the circuit scale CONSTITUTION:An n-bit shift register 10 with a preset terminal is used for receiving serial data having variable bit lengths. All bits of the register 10 are preset to a prescribed logical value before parity computation. A parity checker 20 performs the parity computation based on the output data of the register 10 and bit length data of the serial data and generates a status indicating the presence/absence of a parity error. A status register 30 holds the status.

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