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1. 发明专利

JP2008165407A Electronic mail transmission method, communication device, computer program and recording medium 有权
标题翻译：电子邮件传输方法，通信设备，计算机程序和记录介质
公开(公告)号：JP2008165407A
公开(公告)日：2008-07-17
申请号：JP2006352884
申请日：2006-12-27
申请人： Fujitsu Ltd , 富士通株式会社
发明人： YOSHIDA KENJI
IPC分类号： G06F13/00
摘要： PROBLEM TO BE SOLVED: To provide an electronic mail transmission method, a communication device, a computer program and a recording medium, allowing transmission of only an electronic mail without attaching data to some of the addresses when performing broadcast transmission of the electronic mail attached with data.
SOLUTION: A CPU 17 of this communication device 1 generates the electronic mail attached with the data D (S101). The CPU 17 extracts a title or the like from the generated electronic mail (S102). The CPU 17 decides whether the extracted title or the like accords with a value stored in a table 140 or not (S106). When the CPU 17 decides that it accords with the value stored in the table 140 (YES at S106), the CPU 17 copies the electronic mail unattached with the data D (S108). The CPU 17 adds a transmission history of the attached data D transmitted in the past after a mail body of the copied electronic mail (S109). The CPU 17 transmits the electronic mail to each communication device 4 (S111).
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了提供电子邮件发送方法，通信设备，计算机程序和记录介质，仅在电子邮件的广播发送时才允许仅发送电子邮件而不附加数据到一些地址附有数据的邮件。解决方案：该通信设备1的CPU 17产生附有数据D的电子邮件（S101）。 CPU17从所生成的电子邮件中提取标题等（S102）。 CPU17判定提取的标题等是否符合存储在表140中的值（S106）。当CPU 17判断为与存储在表140中的值一致时（S106为“是”），CPU17复制未附加数据D的电子邮件（S108）。 CPU17在复制的电子邮件的邮件正文之后添加过去发送的附加数据D的发送历史（S109）。 CPU17将电子邮件发送到各通信装置4（S111）。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2006260190A Marginless determination circuit 审中-公开
标题翻译：无损检测电路
公开(公告)号：JP2006260190A
公开(公告)日：2006-09-28
申请号：JP2005076961
申请日：2005-03-17
申请人： Fujitsu Ltd , 富士通株式会社
发明人： YOSHIDA KENJI , KOIKE YOSHIHIKO , YOSHIDA TETSUYA
IPC分类号： G06F1/04 , G06F1/10 , H03K19/21
CPC分类号： G01R31/31727
摘要： PROBLEM TO BE SOLVED: To operate electronic equipment which monitors presence of margin regardless of circumferential conditions without changing the frequency of a clock signal up to marginal conditions. SOLUTION: This marginal determination circuit comprises: a means 1 for storing data to be determined, a means 2 for delaying the data; a means 3 for storing the output of the means 2; and a means 4 for comparing the stored contents of the means 1 and the stored contents of the means 3 and outputting a marginless detection signal when both differ. The marginless detection signal output by the means 4 is used as a switching control signal for a clock switch circuit. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：操作电子设备，无论周边情况如何，都可以监视边缘的存在，而不会将时钟信号的频率改变到边缘条件。该边缘确定电路包括：用于存储要确定的数据的装置1，用于延迟数据的装置2; 用于存储装置2的输出的装置3; 以及用于比较装置1的存储内容和装置3的存储内容并在两者不同时输出无边距检测信号的装置4。由装置4输出的无边缘检测信号用作时钟切换电路的切换控制信号。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2003058591A Method and device for automatically designing wiring between circuit blocks of integrated circuit, and program for performing the method 有权
标题翻译：用于自动设计集成电路的电路块之间的接线的方法和设备，以及用于执行该方法的程序
公开(公告)号：JP2003058591A
公开(公告)日：2003-02-28
申请号：JP2001250924
申请日：2001-08-22
申请人： Fujitsu Ltd , 富士通株式会社
发明人： ARAKAWA TOSHIO , MIURA DAISUKE , OKAMOTO MASAYUKI , NAGASAKA MITSUAKI , HONDA HIROYUKI , YOSHIDA SHUJI , KOBAYASHI KENJI , YOSHIDA KENJI
IPC分类号： G06F17/50 , H01L21/82
CPC分类号： G06F17/5077
摘要： PROBLEM TO BE SOLVED: To reduce a wiring area necessary for wiring between blocks of an integrated circuit.
SOLUTION: In the automatic wiring designing method for automatically connecting inter-block wiring arranged between a first circuit block and a second circuit block with terminals formed along the opposite sides of the first and second circuit blocks, the terminals are sorted with a terminal width (S2), a terminal is selected in the order of a large terminal width, and the terminal is connected to inter-block wiring of a network being the same as that of the terminal (S3 to S11). In other performance examples, terminals to be connected to power supply wiring among the terminals are sorted with the value of current caused to flow to the terminals, and the terminal is selected in the order of the current value with a large value, and is connected to inter- block wiring being the same net as that of the terminal.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：减少集成电路块之间布线所需的布线面积。解决方案：在用于自动连接布置在第一电路块和第二电路块之间的块间布线的自动布线设计方法中，具有沿着第一和第二电路块的相对侧形成的端子，端子以端子宽度 S2），以大端子宽度的顺序选择端子，并且将端子连接到与端子相同的网络的块间布线（S3至S11）。在其他性能示例中，要连接到端子之间的电源布线的端子按照流向端子的电流值进行分类，并且以大值的当前值的顺序选择端子，并且连接来阻断与终端相同网络的接线。

4. 发明专利

JP2017091117A 電子機器及び表示制御プログラム审中-公开
公开(公告)号：JP2017091117A
公开(公告)日：2017-05-25
申请号：JP2015218966
申请日：2015-11-06
申请人：富士通株式会社 , Fujitsu Ltd
发明人： YOSHIDA KENJI
IPC分类号： G06F3/0484 , G06F3/0488 , G09G5/00 , G09G5/14 , G09G5/38
摘要：【課題】タッチパネルの表示画面に複数のアプリケーションを表示した際のアプリケーションの利用のし易さを向上させる電子機器及び表示制御プログラムを提供する。【解決手段】電子機器100は、記憶部302と、決定部311とを含む。記憶部302は、タッチパネル101の表示画面に表示された第1のアプリケーションのウィンドウに入力されたタッチ操作の第1の回数と、第2のアプリケーションのウィンドウに入力されたタッチ操作の第2の回数とを記憶する。決定部311は、第1のアプリケーションと、第2のアプリケーションとを一の表示画面に表示する場合、第1の回数と、第2の回数とに基づいて、第1のアプリケーションのウィンドウと、第2のアプリケーションのウィンドウとの表示位置の関係を決定する。【選択図】図3

5. 发明专利

JP2006085868A Rewrite limiting method and semiconductor device 审中-公开
标题翻译： REWRITE限制方法和半导体器件
公开(公告)号：JP2006085868A
公开(公告)日：2006-03-30
申请号：JP2004271908
申请日：2004-09-17
申请人： Fujitsu Ltd , 富士通株式会社
发明人： YOSHIDA KENJI , KOIKE YOSHIHIKO , YOSHIDA TETSUYA , WATANABE NAOYA
IPC分类号： G11C16/02
摘要： PROBLEM TO BE SOLVED: To improve reliability of data by surely preventing rewriting in an area where the permissible number of rewriting times of a nonvolatile memory is exceeded, to effectively use the rewriting of the entire nonvolatile memory, and to make decision of an error in a writing process within a short period of time. SOLUTION: In the rewrite limiting method of the electrically erasable nonvolatile memory, signals inhibiting the rewriting in the area when the number of rewriting times reaches a predetermined value are outputted to the respective areas of the nonvolatile memory. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题为了通过可靠地防止在超出非易失性存储器的允许重写次数的区域中的重写来提高数据的可靠性，有效地使用整个非易失性存储器的重写，并且决定在短时间内写作过程中的错误。解决方案：在电可擦除非易失性存储器的重写限制方法中，当重写次数达到预定值时禁止重写区域的信号被输出到非易失性存储器的各个区域。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2004252850A Design method for semiconductor integrated circuit 审中-公开
公开(公告)号：JP2004252850A
公开(公告)日：2004-09-09
申请号：JP2003044379
申请日：2003-02-21
申请人： Fujitsu Ltd , 富士通株式会社
发明人： KAWABATA KENICHI , YOSHIDA KENJI , YOKOYAMA KAZUHIRO , NAGATOMI YOSHIAKI
IPC分类号： G06F17/50 , H01L21/82
摘要： PROBLEM TO BE SOLVED: To reduce man-hours and errors in test pattern creation for a semiconductor integrated circuit.
SOLUTION: This design method for a semiconductor integrated circuit is provided with a net list creation step (S121) for creating a net list, which includes connection information between and inside macros of the semiconductor integrated circuit and identification information about the used macro, and a test pattern creation step (S122) creating a test pattern for the semiconductor integrated circuit on the basis of the identification information about the used macro inside the net list.
COPYRIGHT: (C)2004,JPO&NCIPI

7. 发明专利

JP2007213188A Semiconductor integrated circuit device 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：JP2007213188A
公开(公告)日：2007-08-23
申请号：JP2006030653
申请日：2006-02-08
申请人： Fujitsu Ltd , 富士通株式会社
发明人： MINEMURA HIROAKI , YOSHIDA KENJI , YOKOYAMA KAZUHIRO , SHIBAYAMA YUICHI
IPC分类号： G06F12/06 , G06F12/02
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device for increasing a memory region to be used as a general-purpose memory region by a CPU by utilizing a memory region in a functional macro, and for minimizing the increase of a chip size without increasing the capacity of the general-purpose memory, and for coping with the increase request of the general-purpose memory capacity.
SOLUTION: The address of a memory region in an unused functional macro among functional macros 13 to 15 is changed by an in-functional macro memory region rearrangement control circuit 17, and the memory region in the unused functional macro is rearranged in a memory region accessible as an RAM region to be used in a general purpose manner by a CPU 11.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体集成电路器件，用于通过利用功能宏中的存储器区域来增加用作通用存储器区域的存储器区域，并且用于最小化芯片尺寸，而不增加通用存储器的容量，并且用于应对通用存储容量的增加请求。解决方案：功能宏13至15中的未使用的功能宏中的存储器区域的地址由功能内宏区存储区域重排控制电路17改变，并且将未使用的功能宏中的存储区重新排列成存储器区域作为RAM区域可访问，由CPU 11以通用方式使用。版权所有：（C）2007，JPO＆INPIT

8. 发明专利

JP2007058467A Register monitor circuit, device and register monitor method 审中-公开
标题翻译：寄存器监视器电路，器件和寄存器监视器方法
公开(公告)号：JP2007058467A
公开(公告)日：2007-03-08
申请号：JP2005241850
申请日：2005-08-23
申请人： Fujitsu Ltd , 富士通株式会社
发明人： MINEMURA HIROAKI , KOIKE YOSHIHIKO , SHIBAYAMA YUICHI , YOKOYAMA KAZUHIRO , YOSHIDA KENJI
IPC分类号： G06F12/16 , G06F11/00
摘要： PROBLEM TO BE SOLVED: To provide a register monitor circuit for preventing device malfunction when the content of a register changes due to bit change or abnormal writing. SOLUTION: A register 2 for monitor is installed in a target register 1 for duplicating a system. Also, clock signals CLK1 and CLK2 to be supplied to the register 2 for monitor with the same frequency and in different timings are used for the object register 1. Thus, it is possible to detect that the registers 1 and 2 are rewritten as an alarm signal(ALARM), and to provide a response even when the registers 1 and 2 are rewritten due to the superimposition of a noise on the clock signals. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种寄存器监视电路，用于当寄存器的内容由于位改变或异常写入而改变时防止设备故障。解决方案：用于监视器的寄存器2安装在目标寄存器1中，用于复制系统。此外，用于以相同频率和不同定时提供给用于监视的寄存器2的时钟信号CLK1和CLK2用于对象寄存器1.因此，可以检测到寄存器1和2被重写为报警信号（ALARM），并且即使当寄存器1和2由于时钟信号上的噪声叠加而被重写时也提供响应。版权所有（C）2007，JPO＆INPIT

9. 发明专利

JP2003044536A Layout method and apparatus for lsi arranging cell with timing priority 有权
标题翻译：用于具有时序优先权的LSI安排单元的布局方法和装置
公开(公告)号：JP2003044536A
公开(公告)日：2003-02-14
申请号：JP2001228373
申请日：2001-07-27
申请人： Fujitsu Ltd , 富士通株式会社
发明人： NAGASAKA MITSUAKI , MIURA DAISUKE , OKAMOTO MASAYUKI , HONDA HIROYUKI , ARAKAWA TOSHIO , YOSHIDA SHUJI , YOSHIDA KENJI , KOBAYASHI KENJI
IPC分类号： G06F17/50 , H01L21/82
CPC分类号： G06F17/5068
摘要： PROBLEM TO BE SOLVED: To provide a layout method and apparatus as much capable as possible of wiring automatically after a cell arrangement with timing priority.
SOLUTION: In a layout method for LSI with a plurality of cells, cells are arranged automatically based on the net list including data on cells and their connections and on the timing conditions, and global wiring processing is performed to analyze a degree of complexity of wiring after an optimizing processing for timing to arrange a plurality of cells in a chip then within a small area in which determined it is hard to perform detailed wiring processing because of a high degree of complexity of wiring, and the detailed wiring processing is performed to the rearranged cells. Since the re-arrangement processing of cells is performed only in the small areas, it is possible to reduce in the degree of complexity while keeping the optimized status of timing of cells, so that it is reduced in possibility to cause a wiring impossibility due to the detailed wiring processing in the future.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供一种在具有定时优先级的单元布置之后尽可能多地布线的布局方法和装置。解决方案：在具有多个单元的LSI的布局方法中，基于包括关于单元及其连接的数据的网表自动布置单元，并且在定时条件下，执行全局布线处理以分析布线的复杂程度在对芯片中的多个单元进行优化处理之后，在由于布线复杂度高而难以进行详细布线处理的小区域内进行详细布线处理，重排细胞。由于仅在小区域中进行单元的重新配置处理，所以可以在保持单元的定时优化状态的同时降低复杂度，从而可能导致由于未来的详细布线处理。

10. 发明专利

JP2002312160A BINARY CARRY ARITHMETIC CIRCUIT, HALF ADDITION CIRCUIT AND INCREMENTER USING THE SAME, BINARY BORROW ARITHMETIC CIRCUIT, HALF SUBTRACTION CIRCUIT AND DECREMENTER USING THE SAME 失效
公开(公告)号：JP2002312160A
公开(公告)日：2002-10-25
申请号：JP2001116174
申请日：2001-04-13
申请人： FUJITSU LTD
发明人： YOSHIDA SHUJI , MIURA DAISUKE , ARAKAWA TOSHIO , NAGASAKA MITSUAKI , YOSHIDA KENJI , HONDA HIROYUKI , KOBAYASHI KENJI , OKAMOTO MASAYUKI
IPC分类号： G06F7/50 , G06F7/505 , G06F7/506
摘要： PROBLEM TO BE SOLVED: To achieve higher speed, while maintaining the advantage of a ripple carry type, having a small-scale circuit. SOLUTION: In this incrementer, binary carry arithmetic circuits 20 of half addition circuits, other than one for the lowest digit, each having a transfer gate 212 turned on when an input bit A2 is active and supplied at its data input end with a carry *C2 from a lower digit, and a transistor 23 turned on, when the input bit A2 is inactive and connected between a power potential VDD having a logical value equal to that of the inactive potential of the carry *C2 and a data output end of the transfer gate 212. The signal of the output end is a carry *C3 to a higher column. Since transfer gates 212 to 214 of the binary carry arithmetic circuits, other than that for the lowest column, are connected in series and the respective transfer gates are on-off controlled simultaneously by input bits, a carry from the lowest column can be propagated through the sequence of transfer gates at a high speed.

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