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1. 发明专利

JP2014082361A Silicon carbide mos semiconductor device manufacturing method 有权
标题翻译：硅碳化镓半导体器件制造方法
公开(公告)号：JP2014082361A
公开(公告)日：2014-05-08
申请号：JP2012229785
申请日：2012-10-17
申请人： Fuji Electric Co Ltd , 富士電機株式会社
发明人： OGINO MASAAKI
IPC分类号： H01L21/02 , H01L21/336 , H01L29/12 , H01L29/739 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To inhibit the occurrence of wafer breakage or cracks even in a manufacturing method having a process of thinning a wafer by grinding a rear face on the side opposite to a surface on which a mark for identification is formed to a degree where a thickness is maintained at equal to or more than a thickness determined by at least a withstanding voltage.SOLUTION: A manufacturing method of a silicon carbide MOS semiconductor device comprises: an epitaxial layer formation process of growing an epitaxial layer on one principal surface of an n-type SiC semiconductor substrate; a formation process of a MOS gate structure on a surface layer of the epitaxial layer; a substrate thinning process of thinning the substrate by grinding the other principal surface of the substrate to a degree where a thickness equal to or more than a required substrate thickness determined depending on at least a withstanding voltage is maintained. The manufacturing method further comprises either before or after the epitaxial layer formation process, a process of forming a mark for identification on the one principal surface of the n-type SiC semiconductor substrate, in which a depth of the mark for identification is set at a depth shallower than a substrate thickness after the substrate thinning process.
摘要翻译：要解决的问题：即使在具有通过研磨在与形成有识别标记的表面相反的一侧的后表面来削薄晶片的方法的制造方法中，也可以抑制晶片断裂或裂纹的发生，将厚度保持在至少由耐压确定的厚度以上的厚度。解决方案：碳化硅MOS半导体器件的制造方法包括：外延层形成工艺，其在一个主表面上生长外延层 n型SiC半导体衬底; 在外延层的表面层上形成MOS栅极结构的工艺; 通过研磨基板的另一个主表面使其厚度等于或大于至少根据耐受电压确定的所需基板厚度的程度而使基板变薄的基板薄化工艺。该制造方法还包括在外延层形成工艺之前或之后，在n型SiC半导体衬底的一个主表面上形成用于识别的标记的处理，其中识别标记的深度设置为深度比基板薄化处理后的基板厚度浅。

2. 发明专利

JP2002094032A SEMICONDUCTOR SUBSTRATE AND ITS MANUFACTURING METHOD, AND SEMICONDUCTOR DEVICE USING THE SUBSTRATE AND ITS MANUFACTURING METHOD 失效
公开(公告)号：JP2002094032A
公开(公告)日：2002-03-29
申请号：JP2000276790
申请日：2000-09-12
申请人： FUJI ELECTRIC CO LTD
发明人： OGINO MASAAKI , SUGAHARA NORIYUKI , KURIBAYASHI HITOSHI
IPC分类号： H01L21/762 , H01L21/02 , H01L21/336 , H01L21/822 , H01L27/04 , H01L27/08 , H01L27/12 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device, having superior gate breakdown voltage and capable of being manufactured in a high non-defective rate and an SOI substrate capable of forming its semiconductor device. SOLUTION: The SOI substrate comprises a CZ base 1, and a semiconductor layer region 3 made of an FZ single-crystal which is laminated on the base 1 and laminated via an oxide film 2. A MOS device is formed on the SOI substrate to provide superior gate breakdown voltage and to enhance non-defective rate.

3. 发明专利

JP2013120883A Lateral diffusion width evaluation method of diffusion region formed in semiconductor device 审中-公开
标题翻译：在半导体器件中形成的扩散区域的横向扩散宽度评估方法
公开(公告)号：JP2013120883A
公开(公告)日：2013-06-17
申请号：JP2011268860
申请日：2011-12-08
申请人： Fuji Electric Co Ltd , 富士電機株式会社
发明人： OGINO MASAAKI , HIRUTA REIKO
IPC分类号： H01L21/66
摘要： PROBLEM TO BE SOLVED: To provide a lateral diffusion width evaluation method of a diffusion region formed in a semiconductor device, which can measure a lateral diffusion width at a predetermined depth from a surface of a diffusion region at a depth of approximately 100 μm with high accuracy, and which can measure an in-plane distribution of a lateral diffusion width on a wafer with high efficiency.SOLUTION: A lateral diffusion width evaluation method comprises grinding to a predetermined depth T1, a rear face 1a of a wafer 1 in which a deep diffusion region 2 is formed; polishing or etching the rear face 1a of the wafer 1 to expose the diffusion region 2; stain-etching the exposed diffusion region 2; and subsequently, measuring a lateral diffusion width W1 of the stain-etched diffusion region 2. In this way, the lateral diffusion width W1 at the predetermined depth T1 can be measured with high accuracy.
摘要翻译：要解决的问题：提供形成在半导体器件中的扩散区域的横向扩散宽度评估方法，该扩散区域可以从大约100°的深度处的扩散区域的表面测量在预定深度处的横向扩散宽度 μm，并且可以高效率地测量晶片上的横向扩散宽度的面内分布。解决方案：横向扩散宽度评估方法包括研磨到预定深度T1，形成深扩散区2的晶片1的背面1a; 抛光或蚀刻晶片1的背面1a以暴露扩散区域2; 污染蚀刻暴露的扩散区域2; 并且随后测量污迹蚀刻扩散区域2的横向扩散宽度W1。以这种方式，可以高精度地测量预定深度T1处的横向扩散宽度W1。版权所有（C）2013，JPO＆INPIT

4. 发明专利

JP2013012651A Method for manufacturing reverse blocking insulated gate type bipolar transistor 有权
标题翻译：用于制造反向阻塞绝缘门型双极晶体管的方法
公开(公告)号：JP2013012651A
公开(公告)日：2013-01-17
申请号：JP2011145492
申请日：2011-06-30
申请人： Fuji Electric Co Ltd , 富士電機株式会社
发明人： OGINO MASAAKI
IPC分类号： H01L21/336 , H01L29/06 , H01L29/12 , H01L29/739 , H01L29/78
CPC分类号： H01L29/7395 , H01L21/76237 , H01L29/0615 , H01L29/0661 , H01L29/402 , H01L29/66333
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a reverse blocking insulated gate type bipolar transistor in which a separation layer used for curving the terminal end of high breakdown voltage pn junction in the reverse direction and extending the curved terminal end onto the surface, and ensuring of the high breakdown voltage in the reverse direction and reduction in leakage current during reverse bias are possible.SOLUTION: A tapered groove is formed by anisotropic alkaline etching so that the semiconductor substrate thickness between bottoms of the tapered grooves formed of one main surface and the other main surface becomes 60 μm or more.
摘要翻译：要解决的问题：提供一种用于制造反向阻挡绝缘栅型双极晶体管的方法，其中用于使相对方向弯曲高击穿电压pn结的末端的分离层并将弯曲的终端延伸到表面，确保反向偏压时的高击穿电压和漏电流的降低是可能的。解决方案：通过各向异性碱蚀刻形成锥形槽，使得由一个主表面和另一个主表面形成的锥形槽的底部之间的半导体衬底厚度变为60μm以上。版权所有（C）2013，JPO＆INPIT

5. 发明专利

JP2011243670A Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2011243670A
公开(公告)日：2011-12-01
申请号：JP2010112829
申请日：2010-05-17
申请人： Fuji Electric Co Ltd , 富士電機株式会社
发明人： OGINO MASAAKI , WAKIMOTO HIROKI , MIYAZAKI MASAYUKI
IPC分类号： H01L21/336 , H01L21/301 , H01L29/12 , H01L29/739 , H01L29/78
CPC分类号： H01L29/66333 , H01L29/045 , H01L29/0657
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device capable of securing strength of a wafer, and improving element performance.SOLUTION: A heat diffusion layer 7 is formed from a surface 2 of a wafer 1, a tapered trench 12 reaching the heat diffusion layer 7 is formed from a back surface 3 by anisotropic etching with an alkali solution, and a diffusion layer 21 within a trench is formed on a sidewall surface 13 of the trench 12. A separation layer 3 of a reverse blocking IGBT consists of the heat diffusion layer 7 and the diffusion layer 21 within the trench, and the heat diffusion layer 7 can be shallowly formed by forming the diffusion layer 21 within the trench, allowing the thermal diffusion time to be considerably reduced. A reverse breakdown voltage for the reverse blocking IGBT can be secured while an optimal value in a trade-off of an ON-state voltage and a switching loss can be selected by performing an ion implantation for forming the diffusion layer 21 within the trench and an ion implantation for forming a collector layer 22, separately.
摘要翻译：要解决的问题：提供一种能够确保晶片强度并提高元件性能的半导体器件的制造方法。解决方案：从晶片1的表面2形成热扩散层7，到达热扩散层7的锥形沟槽12由背面3通过各向异性蚀刻用碱溶液形成，扩散层 21的沟槽形成在沟槽12的侧壁表面13上。反向阻断IGBT的分离层3由沟槽内的热扩散层7和扩散层21组成，并且热扩散层7可以是浅的通过在沟槽内形成扩散层21形成，允许热扩散时间大大降低。可以确保反向阻断IGBT的反向击穿电压，同时通过在沟槽内形成扩散层21的离子注入可以选择导通状态电压和开关损耗的权衡的最佳值，用于形成集电极层22的离子注入。版权所有（C）2012，JPO＆INPIT

6. 发明专利

JP2003037077A Chemical vapor phase epitaxial growth device 审中-公开
标题翻译：化学蒸气相外延生长装置
公开(公告)号：JP2003037077A
公开(公告)日：2003-02-07
申请号：JP2001240142
申请日：2001-08-08
申请人： Fuji Electric Co Ltd , 富士電機株式会社
发明人： SHIMIZU AKINORI , HEBINUMA TADASHI , OGINO MASAAKI
IPC分类号： C23C16/52 , H01L21/205
摘要： PROBLEM TO BE SOLVED: To provide a chemical vapor phase epitaxial growth device in which a thin film can be formed on the wafer surface with uniform thickness.
SOLUTION: The chemical vapor phase epitaxial growth device comprises an outer container tube 5 having one closed end (upper part), an inner container tube 4 disposed in the outer container tube 5 and serving as a reaction chamber 9, a supporting jig 2 contained in the inner container tube 4 and referred to a boat, and an electric furnace 7 containing the outer container tube 5 and having a heater 6 for heating a wafer 1 set in the supporting jig 2, wherein a plurality of ring-like adsorption jigs 3 are fixed to the inner wall of the inner container tube 4. Since the adsorption jigs 3 adsorb radical gas, a thin film can be formed uniformly on the wafer 1.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供一种化学气相外延生长装置，其中可以在具有均匀厚度的晶片表面上形成薄膜。解决方案：化学气相外延生长装置包括具有一个封闭端（上部）的外部容器管5，设置在外部容器管5中并用作反应室9的内部容器管4，内部容器管4和称为舟皿的电炉7和包含外部容器管5并具有用于加热设置在支撑夹具2中的晶片1的加热器6的电炉7，其中多个环状吸附夹具3为固定在内容器管4的内壁上。由于吸附夹具3吸附自由基气体，所以可以在晶片1上均匀地形成薄膜。

7. 发明专利

JP2002134504A SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 失效
公开(公告)号：JP2002134504A
公开(公告)日：2002-05-10
申请号：JP2000329929
申请日：2000-10-30
申请人： FUJI ELECTRIC CO LTD
发明人： OGINO MASAAKI
IPC分类号： C23C16/42 , H01L21/318 , H01L21/8238 , H01L27/092
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device of a high reliability by avoiding a deterioration of a quality of a gate dielectric film. SOLUTION: A silicon nitride film 22 of the first layer, as a surface-protecting film for a CMOS, is formed by using a plasma CVD method with a SiH4 gas having no ammonia gas and with N3 gas, and a silicon nitride film 23 of the second layer is formed on the silicon nitride film 22 of the first layer by using a plasma CVD method with a SiH4 containing an ammonia gas and with N3 gas. A great deal of hydrogen existing in the second silicon nitride film 23 which penetrates into gate film 4, 6 is reduced by the first silicon nitride film 22, thereby, the values of Qbd for the gate oxide films 4, 6 can be elevated. As a result, the semiconductor device of a high reliability which has a good TDDB characteristics and a gate oxide film of a high reliability by avoiding a deterioration of the quality of the gate film, can be manufactured in a high yield.

8. 发明专利

JP2001006904A VOLTAGE NONLINEAR RESISTOR 失效
公开(公告)号：JP2001006904A
公开(公告)日：2001-01-12
申请号：JP17552199
申请日：1999-06-22
申请人： FUJI ELECTRIC CO LTD
发明人： SAKAGUCHI TOYOSHIGE , OGINO MASAAKI , NAGATA NORIHISA , TANAKA AKINORI , KOE KAZUO
IPC分类号： H01C7/10
摘要： PROBLEM TO BE SOLVED: To provide a voltage nonlinear resistor wherein V1 mA/t is high and at least 400 V/mm, uniformity of voltage distribution in an element is excellent, and surge endurance is large. SOLUTION: In this resistor, ZnO is made as main component, and, as atomic percentage of each metal element, at least one kind of rare earth element of 0.08-5.0 atm.% as the total amount, Co of 0.1-10.0 atm.%, Ca of 0.01-1.0 atm.%, at least one kind out of K, Cs, Rb of 0.01-1.0 atm.% as the total amount, Cr of 0.01-1.0 atm.%, at least one kind out of Al, Ga, In of 1×10-4-5×10-2 atm.% as the total amount, Bi of 0.7-1.1 atm.%, and material wherein Sb is added in a range of Sb/Bi=0.8-1.2 as an adding ratio to Bi are added as subcomponent. For another way, Si and/or Mn of 0.1-1.0 atm.% are added further to material wherein B of 5×10-4-1×10-1 atm.% is added as atomic percentage of metal element to the above subcomponent. Then baking is performed. The figure shows relations of loadings of Si and Mn to surge endurance.

9. 发明专利

JP2011181770A Semiconductor device and method of manufacturing semiconductor device 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：JP2011181770A
公开(公告)日：2011-09-15
申请号：JP2010045740
申请日：2010-03-02
申请人： Fuji Electric Co Ltd , 富士電機株式会社
发明人： WAKIMOTO HIROKI , IGUCHI KENICHI , YOSHIKAWA ISAO , NAKAJIMA TSUNEHIRO , TANAKA SHUNSUKE , OGINO MASAAKI
IPC分类号： H01L29/739 , H01L29/06 , H01L29/78
CPC分类号： H01L21/308 , H01L21/302 , H01L21/78 , H01L29/06
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that is prevented from deteriorating in electric characteristics, and to provide a method of manufacturing the semiconductor device. SOLUTION: At a voltage blocking structure part of a reverse blocking type IGBT, a surface layer on a top side of an n-type drift region 1 is provided with a plurality of field limiting rings (FLR) 2 and a channel stopper 3. A surface layer on a reverse side of the n-type drift region 1 is provided with a p-type collector region 7. An element end part is provided with a p + -type isolation layer 11 for obtaining a voltage blocking capability. Further, a recess part 6 is provided which reaches the p + -type isolation layer 11 from the reverse side of the n-type drift region 1. A surface layer on a side wall and a bottom surface of the recess 6 is provided with a p-type region 8, and the p + -type isolation layer 11 and p-type collector region 7 are electrically connected. Further, the p + -type isolation layer 11 is in contact with the channel stopper 3. Furthermore, the p + -type isolation layer 11 is provided including a cleavage surface 21 having one side at a boundary 20 between the bottom surface and side wall of the recess part 6. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种防止电特性恶化的半导体器件，并提供一种半导体器件的制造方法。解决方案：在反向阻挡型IGBT的电压阻挡结构部分，n型漂移区1的上侧的表面层设置有多个场限制环（FLR）2和沟道阻塞在n型漂移区域1的背面上的表面层设置有p型集电区域7.元件端部设置有用于获得电压阻断能力。此外，设置从n型漂移区域1的反面到达p + SP>型隔离层11的凹部6。在侧壁和底面的表面层凹部6设置有p型区域8，并且p + SP型隔离层11和p型集电极区域7电连接。此外，p + 型隔离层11与通道阻挡件3接触。此外，提供了p

10. 发明专利

JP2001064019A Mn PERVOSKITE-TYPE OXIDE 失效
公开(公告)号：JP2001064019A
公开(公告)日：2001-03-13
申请号：JP24017199
申请日：1999-08-26
申请人： FUJI ELECTRIC CO LTD
发明人： KUNIHARA KENJI , OGINO MASAAKI
IPC分类号： H01F1/11 , C01G45/00 , H01F1/40
摘要： PROBLEM TO BE SOLVED: To obtain a recording material utilizing the change in physical properties, which is expressed by the formula La1-x-yEuySrxMnO3 wherein (x) and (y+x) are specified. SOLUTION: An Mn perovskite-type oxide is expressed by the formula La1-x-yEuySrxMnO3, wherein (x) is 0.15. When (x) is 0.08 and

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