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1. 发明专利

JP2010199548A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2010199548A
公开(公告)日：2010-09-09
申请号：JP2009270146
申请日：2009-11-27
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： HASEGAWA MASARU , KATAGIRI MITSUAKI , ISA SATOSHI , IWAKURA KEN , SASAKI MASARU
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L25/0657 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/48465 , H01L2224/48471 , H01L2224/48479 , H01L2224/48599 , H01L2224/4899 , H01L2224/49171 , H01L2224/73265 , H01L2224/85007 , H01L2224/85051 , H01L2225/0651 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01033 , H01L2924/01057 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12041 , H01L2924/15311 , H01L2924/181 , H01L2924/20755 , H01L2924/30105 , H01L2924/00 , H01L2224/48132 , H01L2924/00012 , H01L2924/20757 , H01L2924/2075 , H01L2924/20754 , H01L2224/4554
摘要： PROBLEM TO BE SOLVED: To reduce a parasitic capacitance of a bonding wire that extends from a lower-layer side semiconductor chip and passes through between lower-layer and upper layer semiconductor chips in a chip-stacked type semiconductor device. SOLUTION: In a chip-stacked type semiconductor device, a second semiconductor chip 30 is stacked on a first semiconductor chip 20 having a plurality of bonding pads 28 in its center area via a bonding layer 40. A plurality of wires respectively connected with the bonding pads 28 of the first semiconductor chip 20 pass through between the semiconductor chips 20 and 30 to be led outward beyond the periphery edge 55 of the first semiconductor chip 20. At least part of wires 80 among the plurality of wires is located almost at the center of interval of the first semiconductor chip 20 and the second semiconductor chip 30 in a area including at least an intermediate point 51 of the bonding pads 28 of the first semiconductor chip 20 and the periphery edge 55. Holders 50 holding those wires are provided that are made of a different material from the bonding layer 40 on the first semiconductor chip 20. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：为了降低从下层侧半导体芯片延伸并在芯片堆叠型半导体器件中的下层和上层半导体芯片之间通过的接合线的寄生电容。解决方案：在芯片堆叠型半导体器件中，第二半导体芯片30经由接合层40堆叠在其中心区域上具有多个接合焊盘28的第一半导体芯片20上。分别连接的多根线其中第一半导体芯片20的接合焊盘28穿过半导体芯片20和30之间，以被引导向外超出第一半导体芯片20的周边边缘55.多条电线中的至少一部分电线80几乎位于在第一半导体芯片20和第二半导体芯片30的间隔的中心处于包括第一半导体芯片20的接合焊盘28的至少中间点51和周边边缘55的区域中。保持这些线的支架50 提供由与第一半导体芯片20上的结合层40不同的材料制成。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2010177530A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2010177530A
公开(公告)日：2010-08-12
申请号：JP2009019931
申请日：2009-01-30
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： IWAKURA KEN , KATAGIRI MITSUAKI , ISA SATOSHI , SASAKI MASARU
IPC分类号： H01L23/12 , H01L23/52 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L23/49833 , H01L23/3128 , H01L24/06 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0657 , H01L2224/0401 , H01L2224/05554 , H01L2224/05599 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/49175 , H01L2224/73215 , H01L2224/73265 , H01L2224/85399 , H01L2225/0651 , H01L2225/06527 , H01L2225/06572 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01033 , H01L2924/014 , H01L2924/07802 , H01L2924/10161 , H01L2924/15311 , H01L2924/181 , H01L2924/19107 , H01L2924/30107 , H01L2924/3011 , H01L2224/45099 , H01L2924/00 , H01L2224/32145 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To make high-speed operation possible in a semiconductor device in which a laminated structure which laminates a printed wiring board on a semiconductor chip is mounted on a package base board via an insulating layer. SOLUTION: The semiconductor device 1 is formed by mounting a laminated structure 3 which laminates a printed wiring board 9 on a semiconductor chip 7 via an insulating layer 8 on a package base board 2, wherein in the laminated structure 3, the semiconductor chip 7 and the printed wiring board 9 are connected in flip-chip, a connection land 14a of a signal system in the center section of the printed wiring board 9 is connected with a connection land 6a of the signal system on package base board 2 by a comparatively long wire 18a, and a connection land 14b of a power supply system in the periphery of the printed wiring board 9 is connected with a connection land 6b of the power supply system on the package base board 2 by a comparatively short wire 18b. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：通过绝缘层将半导体芯片上的印刷线路板层叠的叠层结构的半导体器件中的高速操作成为可能。解决方案：半导体器件1通过安装层压结构3形成，层压结构3通过绝缘层8将半导体芯片7上的印刷线路板9层叠在封装基板2上，其中在层叠结构3中，半导体芯片7和印刷电路板9以倒装芯片连接，印刷电路板9的中心部分中的信号系统的连接台面14a通过包装基板2上的信号系统的连接平台6a与印刷电路板9周边的电源系统的较长的导线18a和连接台面14b通过比较短的导线18b与电源系统的连接台阶6b连接在封装基板2上。版权所有（C）2010，JPO＆INPIT

3. 发明专利

JP2013171361A Electric characteristics evaluation analysis system, equivalent circuit model extraction method, and program and recording medium for them 审中-公开
标题翻译：电特性评估分析系统，等效电路模型提取方法及其程序和记录介质
公开(公告)号：JP2013171361A
公开(公告)日：2013-09-02
申请号：JP2012033665
申请日：2012-02-20
申请人： Elpida Memory Inc , エルピーダメモリ株式会社 , Hitachi Ltd , 株式会社日立製作所
发明人： IWAKURA KEN , KATAGIRI MITSUAKI , HIROSE YUKITOSHI , MORIYA TAKUYA , UEMATSU YUTAKA
IPC分类号： G06F17/50
摘要： PROBLEM TO BE SOLVED: To provide an electric characteristics evaluation analysis system capable of easily obtaining an equivalent circuit model that can perform simulation of a circuit including crosstalk noise between high-accuracy signal wirings in a semiconductor package that includes a fixed potential wiring and a plurality of signal wirings each of which is connected to a corresponding semiconductor chip connection terminal and external connection terminal.SOLUTION: An electric characteristics evaluation analysis system includes: a division position setting section and an equivalent circuit model extraction section. The division position setting section sets division positions for dividing a fixed potential wiring into: a plurality of part wirings that are dividedly wired in such a manner that each signal wire is sandwiched from both sides so as to shield each of the plurality of signal wires; a part that connects each of the part wirings to a corresponding semiconductor chip connection terminal; and a part that connects each of the part wirings to a corresponding external connection terminal. The equivalent circuit model extraction section extracts a lumped-constant equivalent circuit model, in which the fixed potential wiring has been divided at each division positions, by electromagnetic field analysis.
摘要翻译：要解决的问题：提供一种电特性评估分析系统，其能够容易地获得能够执行包括固定电位布线和多个固定电位布线的半导体封装中的高精度信号布线之间的包括串扰噪声的电路的模拟的等效电路模型每个信号线连接到相应的半导体芯片连接端子和外部连接端子。解决方案：电气特性评估分析系统包括：分割位置设置部分和等效电路模型提取部分。分割位置设定部将将固定电位配线分割的分割位置设定为：分割地布线的多个部分配线，使得每个信号线被夹在两侧以便屏蔽多个信号线中的每一个; 将部分布线与相应的半导体芯片连接端子连接的部分; 以及将每个部分布线连接到相应的外部连接端子的部分。等效电路模型提取部分通过电磁场分析提取集中常数等效电路模型，其中固定电位线在每个分割位置被划分。

4. 发明专利

JP2012182784A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2012182784A
公开(公告)日：2012-09-20
申请号：JP2011241620
申请日：2011-11-02
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： KATAGIRI MITSUAKI , IWAKURA KEN , UEMATSU YUTAKA
IPC分类号： H03K5/01 , H03K19/0175 , H03K19/0944
CPC分类号： H03K19/00361 , G11C7/02 , G11C11/4074 , G11C11/4076 , G11C11/4096 , Y10T307/50
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can reduce vibration noise of SSN (Simultaneous Switching Noise) of an output circuit.SOLUTION: A semiconductor device comprises a first and second power source lines, an output circuit 12 arranged between the first power source line VDDQ and the second power source line VSSQ, and a noise cancellation circuit 13 arranged between the first power source line and the second power source line. The noise cancellation circuit 13 generates in a power source, against power source noise causing exponential attenuation in vibration with a predetermined period generated at the time of switching an output node of the output circuit to a logic level, power source noise delayed from the former vibration by a half cycle to cause inverse attenuation in vibration with respect to the former vibration to cause the both to cancel out each other.
摘要翻译：要解决的问题：提供可以降低输出电路的SSN（同时开关噪声）的振动噪声的半导体器件。解决方案：半导体器件包括第一和第二电源线，布置在第一电源线VDDQ和第二电源线VSSQ之间的输出电路12，以及布置在第一电源线和第二电源线。噪声消除电路13在电源中产生与在将输出电路的输出节点切换到逻辑电平时产生的预定周期的振动中引起指数衰减的电源噪声，从前一个振动延迟的电源噪声相对于前一个振动使振动产生相反的衰减，导致两者彼此抵消。版权所有（C）2012，JPO＆INPIT

5. 发明专利

JP2012104707A Semiconductor package 审中-公开
标题翻译：半导体封装
公开(公告)号：JP2012104707A
公开(公告)日：2012-05-31
申请号：JP2010252913
申请日：2010-11-11
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： KATAGIRI MITSUAKI , IWAKURA KEN , UEMATSU YUTAKA
IPC分类号： H01L23/12 , H01L21/60 , H01L21/822 , H01L21/8242 , H01L25/065 , H01L25/07 , H01L25/18 , H01L27/04 , H01L27/10 , H01L27/108
CPC分类号： H01L23/498 , G11C5/06 , H01L23/525 , H01L24/05 , H01L24/06 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L2223/6611 , H01L2224/04042 , H01L2224/05013 , H01L2224/05553 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48227 , H01L2224/48463 , H01L2224/49175 , H01L2224/49176 , H01L2224/49431 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/0102 , H01L2924/01023 , H01L2924/01033 , H01L2924/014 , H01L2924/15173 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor package capable of reducing loop inductance of bonding wires.SOLUTION: A semiconductor package has: a semiconductor device having a plurality pads for signal and a plurality of auxiliary pads arranged alternately in a predetermined direction; and a package substrate having a plurality of bond fingers for signal, a plurality of bond fingers for power-supply voltage, and a plurality of bond fingers for ground potential. Each of the plurality of pads for signal is connected to each of the plurality of bond fingers for signal via a first wire, and each of the plurality of bond fingers for power-supply voltage and each of the plurality of bond fingers for ground potential are connected to each of the plurality of auxiliary pads via a second wire. The first wire is arranged between the second wire connected to the bond finger for power-supply voltage and the second wire connected to the bond finger for ground potential.
摘要翻译：要解决的问题：提供能够降低接合线的环路电感的半导体封装。解决方案：半导体封装具有：具有用于信号的多个焊盘和沿预定方向交替布置的多个辅助焊盘的半导体器件; 以及具有多个用于信号的键合指状物的封装基板，用于供电电压的多个键合指状物和用于接地电位的多个键合指状物。多个用于信号的焊盘中的每一个通过第一线连接到多个接合指中的每一个用于信号，并且用于电源电压的多个键合键和用于接地电位的多个键合键中的每一个经由第二线连接到多个辅助垫中的每一个。第一线布置在连接到用于电源电压的接合指的第二线和连接到接合爪的接地电位的第二线之间。版权所有（C）2012，JPO＆INPIT

6. 发明专利

JP2011082451A Package substrate for semiconductor and semiconductor device equipped with the same 审中-公开
标题翻译：用于半导体的封装衬底和配备其的半导体器件
公开(公告)号：JP2011082451A
公开(公告)日：2011-04-21
申请号：JP2009235495
申请日：2009-10-09
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： TAKEDA HIROMASA , ISA SATOSHI , KATAGIRI MITSUAKI , IWAKURA KEN , HASEGAWA MASARU
IPC分类号： H01L23/12 , H01L21/60
CPC分类号： H01L24/50 , H01L23/13 , H01L23/49816 , H01L23/49838 , H01L23/50 , H01L2224/16145 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/01005 , H01L2924/01006 , H01L2924/0102 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To improve signal quantity by reducing stray capacitance between wiring and a chip on a package substrate.
SOLUTION: In a semiconductor device equipped with a semiconductor chip C and a package substrate P loaded with the chip, the package substrate P is provided with an internal terminal 30 connected to the semiconductor chip C, surface wiring 52 connected to the internal terminal 30, back face wiring 54 connected to an external terminal 40, and a contact 56 connected to the surface wiring 52 and the back face wiring 54. The contact 56 to which a signal is transmitted among the contacts 56 is arranged in the neighborhood of the internal terminal 30. Thus, the signal extracted from the semiconductor chip C is immediately isolated from the chip loading face of the package substrate P, so that it is possible to reduce stray capacitance between the wiring and the chip on the package substrate P and to improve signal quality as a result.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：通过减少布线和封装衬底上的芯片之间的杂散电容来提高信号量。解决方案：在装配有半导体芯片C的半导体器件和装载有芯片的封装衬底P的情况下，封装衬底P设置有连接到半导体芯片C的内部端子30，与内部连接的表面布线52 端子30，连接到外部端子40的背面布线54和连接到表面布线52和背面布线54的触点56.在触点56之间传输信号的触点56布置在内部端子30.因此，从半导体芯片C提取的信号立即与封装基板P的芯片负载面隔离，从而可以减少布线与封装基板P上的芯片之间的杂散电容，从而提高信号质量。版权所有（C）2011，JPO＆INPIT

7. 发明专利

JP2010122903A Circuit simulation method and device, and program, circuit simulation model and creation method therefor 审中-公开
标题翻译：电路仿真方法与装置及程序，电路仿真模型及其创建方法
公开(公告)号：JP2010122903A
公开(公告)日：2010-06-03
申请号：JP2008295956
申请日：2008-11-19
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： IWAKURA KEN , ISA SATOSHI , KATAGIRI MITSUAKI , SASAKI MASARU
IPC分类号： G06F17/50
摘要： PROBLEM TO BE SOLVED: To generate a partial circuit model obtained by substantially removing a specific circuit element from a standard circuit model without correcting the standard circuit model, to perform circuit simulation.
SOLUTION: The circuit simulation method using the standard circuit model having at least two external terminals, the standard circuit being supposed to include the specific circuit element connected in parallel with another circuit element between the two terminals in the standard circuit model. The circuit simulation method has steps of: performing circuit simulation for a circuit including the standard circuit model to obtain an inter-terminal voltage applied to between the two terminals; performing circuit simulation using the specific circuit element alone to obtain a specific current flowing through the specific circuit when the inter-terminal voltage is applied between the two terminals; generating a current source circuit model wherein a current whose absolute value is equal to the specific current flows in the direction opposite to the specific current, and generating the partial circuit model wherein the current source circuit model is connected between the two terminals in parallel with the standard circuit model; and performing the circuit simulation by use of the partial circuit model.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了产生通过在不校正标准电路模型的情况下从标准电路模型基本上去除特定电路元件而获得的部分电路模型，以进行电路仿真。解决方案：使用具有至少两个外部端子的标准电路模型的电路仿真方法，标准电路应该包括在标准电路模型中两个端子之间的另一个电路元件并联的特定电路元件。电路仿真方法有以下步骤：对包括标准电路模型的电路进行电路仿真，以获得施加在两个端子之间的端子间电压; 当在两个端子之间施加端子间电压时，使用单独的电路元件执行电路仿真以获得流过特定电路的比电流; 产生电流源电路模型，其中绝对值等于特定电流的电流沿与特定电流相反的方向流动，并产生部分电路模型，其中电流源电路模型连接在两个端子之间，与标准电路模型; 并使用部分电路模型进行电路仿真。版权所有（C）2010，JPO＆INPIT

8. 发明专利

JP2011196934A Testing method and interposer used for the same 审中-公开
标题翻译：测试方法和使用它的插入器
公开(公告)号：JP2011196934A
公开(公告)日：2011-10-06
申请号：JP2010066543
申请日：2010-03-23
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： UEMATSU YUTAKA , OSAKA HIDEKI , NAKAMURA SATOSHI , MURAOKA SATOSHI , KATAGIRI MITSUAKI , IWAKURA KEN , HIROSE YUKITOSHI
IPC分类号： G01R31/26
CPC分类号： G01R31/2889
摘要： PROBLEM TO BE SOLVED: To provide a test system 10 for finding an eliminable terminal in an IC of a BGA package.SOLUTION: The test system 10 includes: connecting an IC 11 of a BGA package with a test substrate 16 via an interposer 20 where a probe for detecting current and a switch are provided for each terminal of the BGA package; turning off the switch connected to at least one power terminal of the IC 11 to input a test pattern signal to the IC 11 via the test substrate 16; and specifying a power terminal connected to the switch that has been turned off as an eliminable terminal, when the IC 11 operates normally and current values of all the terminals of the IC 11 are within tolerance.
摘要翻译：要解决的问题：提供一种用于在BGA封装的IC中找到可消除端子的测试系统10.解决方案：测试系统10包括：通过插入器20将BGA封装的IC 11与测试衬底16连接，为BGA封装的每个端子提供用于检测电流和开关的探针; 关闭连接到IC 11的至少一个电源端子的开关，以经由测试基板16将测试图案信号输入到IC 11; 并且当IC 11正常工作并且IC 11的所有端子的当前值在公差内时，指定连接到已经被关闭的开关的电源端子作为可消除端子。

9. 发明专利

JP2013110314A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2013110314A
公开(公告)日：2013-06-06
申请号：JP2011255195
申请日：2011-11-22
申请人： Elpida Memory Inc , エルピーダメモリ株式会社 , Hitachi Ltd , 株式会社日立製作所
发明人： KATAGIRI MITSUAKI , FUJISAWA HIROKI , TAKEDA HIROMASA , IWAKURA KEN , UEMATSU YUTAKA , SHINKAI GO
IPC分类号： H01L21/822 , H01L27/04 , H03H11/04
CPC分类号： H03K19/017545 , H01L27/0805 , H01L28/40 , H03K19/00361
摘要： PROBLEM TO BE SOLVED: To inhibit noise from occurring between wiring for supplying power to a first circuit and wiring for supplying power to a second circuit when the power is supplied to the first circuit and the second circuit, which form an internal circuit, from different power supply terminals through different wiring.SOLUTION: A semiconductor device is provided with first power supply wiring for supplying power to a first circuit, a second power supply wiring for supplying power to a second circuit, and a capacitive element between the first power supply wiring and the second power supply wiring. The structure significantly reduces impedance between both terminals, thereby reducing noise between different kinds of power supplies.
摘要翻译：要解决的问题：为了防止在向第一电路供电的布线和当向第一电路和第二电路供电时向第二电路供电的布线之间发生噪声，形成内部电路，从不同的电源端子通过不同的接线。解决方案：半导体器件设置有用于向第一电路供电的第一电源布线，用于向第二电路供电的第二电源布线和第一电源布线与第二电力之间的电容元件供电接线。该结构显着降低了两个端子之间的阻抗，从而降低了不同种类电源之间的噪声。版权所有（C）2013，JPO＆INPIT

10. 发明专利

JP2010009179A Design method and design support system for semiconductor device or printed wiring board 审中-公开
标题翻译：半导体器件或印刷电路板的设计方法和设计支持系统
公开(公告)号：JP2010009179A
公开(公告)日：2010-01-14
申请号：JP2008165628
申请日：2008-06-25
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： NAKAMURA SATOSHI , HARA ATSUSHI , KATAGIRI MITSUAKI , HIROSE YUKITOSHI , ITAYA SATORU , IWAKURA KEN
IPC分类号： G06F17/50 , H05K3/00
CPC分类号： G06F17/5036 , G06F2217/78 , H05K1/181 , H05K3/0005
摘要： PROBLEM TO BE SOLVED: To provide a design method and a design support system for a semiconductor device or a printed wiring board, using a semiconductor device model properly expressing parasitic elements that occur when mounting a semiconductor chip or a semiconductor package on a printed wiring board or the like.
SOLUTION: The design method for a semiconductor device with the power source wiring, ground wiring and signal wiring of a semiconductor package and a printed circuit board as an adjustment-object system in a state that the semiconductor device is mounted on the printed wiring board or for a printed wiring board, includes: a step of extracting a correction circuit model 113 for correcting a parasitic element that occurs between the semiconductor device and the printed wiring board; a step of creating a semiconductor model 116 into which the correction circuit model 113 has been inserted; a step of calculating an adjustment-object value based on an adjustment-object system impedance model and the semiconductor device model 116; and a step of determining a design guide for the adjustment-object system by comparing the adjustment-object value with a constraint value.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种用于半导体器件或印刷线路板的设计方法和设计支持系统，使用适当地表示在将半导体芯片或半导体封装安装在基板上时发生的寄生元件的半导体器件模型印刷电路板等。解决方案：在半导体器件安装在印刷的状态下的半导体器件的设计方法，其具有作为调整对象系统的半导体封装的电源布线，接地布线和信号布线以及印刷电路板布线板或印刷布线板的步骤包括：提取用于校正在半导体器件和印刷线路板之间发生的寄生元件的校正电路模型113的步骤; 创建已经插入校正电路模型113的半导体模型116的步骤; 基于调整对象系统阻抗模型和半导体器件模型116计算调整对象值的步骤; 以及通过将调整对象值与约束值进行比较来确定调整对象系统的设计指南的步骤。版权所有（C）2010，JPO＆INPIT

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