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1. 发明专利

JP2013171361A Electric characteristics evaluation analysis system, equivalent circuit model extraction method, and program and recording medium for them 审中-公开
标题翻译：电特性评估分析系统，等效电路模型提取方法及其程序和记录介质
公开(公告)号：JP2013171361A
公开(公告)日：2013-09-02
申请号：JP2012033665
申请日：2012-02-20
申请人： Elpida Memory Inc , エルピーダメモリ株式会社 , Hitachi Ltd , 株式会社日立製作所
发明人： IWAKURA KEN , KATAGIRI MITSUAKI , HIROSE YUKITOSHI , MORIYA TAKUYA , UEMATSU YUTAKA
IPC分类号： G06F17/50
摘要： PROBLEM TO BE SOLVED: To provide an electric characteristics evaluation analysis system capable of easily obtaining an equivalent circuit model that can perform simulation of a circuit including crosstalk noise between high-accuracy signal wirings in a semiconductor package that includes a fixed potential wiring and a plurality of signal wirings each of which is connected to a corresponding semiconductor chip connection terminal and external connection terminal.SOLUTION: An electric characteristics evaluation analysis system includes: a division position setting section and an equivalent circuit model extraction section. The division position setting section sets division positions for dividing a fixed potential wiring into: a plurality of part wirings that are dividedly wired in such a manner that each signal wire is sandwiched from both sides so as to shield each of the plurality of signal wires; a part that connects each of the part wirings to a corresponding semiconductor chip connection terminal; and a part that connects each of the part wirings to a corresponding external connection terminal. The equivalent circuit model extraction section extracts a lumped-constant equivalent circuit model, in which the fixed potential wiring has been divided at each division positions, by electromagnetic field analysis.
摘要翻译：要解决的问题：提供一种电特性评估分析系统，其能够容易地获得能够执行包括固定电位布线和多个固定电位布线的半导体封装中的高精度信号布线之间的包括串扰噪声的电路的模拟的等效电路模型每个信号线连接到相应的半导体芯片连接端子和外部连接端子。解决方案：电气特性评估分析系统包括：分割位置设置部分和等效电路模型提取部分。分割位置设定部将将固定电位配线分割的分割位置设定为：分割地布线的多个部分配线，使得每个信号线被夹在两侧以便屏蔽多个信号线中的每一个; 将部分布线与相应的半导体芯片连接端子连接的部分; 以及将每个部分布线连接到相应的外部连接端子的部分。等效电路模型提取部分通过电磁场分析提取集中常数等效电路模型，其中固定电位线在每个分割位置被划分。

2. 发明专利

JP2010093149A Low noise semiconductor package 有权
标题翻译：低噪声半导体封装
公开(公告)号：JP2010093149A
公开(公告)日：2010-04-22
申请号：JP2008263422
申请日：2008-10-10
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： UEMATSU YUTAKA , HIROSE YUKITOSHI
IPC分类号： H01L25/10 , H01L25/11 , H01L25/18
CPC分类号： H01L25/0657 , H01L23/3128 , H01L23/50 , H01L24/48 , H01L25/105 , H01L25/18 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2225/0651 , H01L2225/06562 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： PROBLEM TO BE SOLVED: To provide a package structure for achieving a reduction in noise without changing a package size in a semiconductor device of taking the form of a stacked type package such as a PoP package, because of the problem of an increase in noise associated with an increase in area of a return path by having a stacked type package structure.
SOLUTION: In a lower PoP package 3 having a PoP structure, the package is newly provided with a power supply wiring 12 parallel to a signal wiring between the upper PoP and the lower PoP.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种用于在不改变采用诸如PoP封装的堆叠式封装形式的半导体器件中的封装尺寸的情况下实现噪声降低的封装结构，由于增加的问题通过具有堆叠式封装结构而与返回路径的面积增加相关联的噪声。解决方案：在具有PoP结构的较低PoP封装3中，封装新设有与上部PoP和下部PoP之间的信号布线并联的电源布线12。版权所有（C）2010，JPO＆INPIT

3. 发明专利

JP2010027137A Semiconductor device and information processing system 有权
标题翻译：半导体器件和信息处理系统
公开(公告)号：JP2010027137A
公开(公告)日：2010-02-04
申请号：JP2008186707
申请日：2008-07-18
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： UEMATSU YUTAKA , SAITO TATSUYA , NISHIO YOJI , HIROSE YUKITOSHI
IPC分类号： G11C11/4076 , G11C11/401 , G11C11/406
CPC分类号： G11C11/406 , G11C11/40618 , G11C11/4074 , G11C2211/4067
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and an information processing system, which reduces a power source noise.
SOLUTION: A DRAM memory includes 8 memory banks MBK0-MBK7, for instance. A control is made to refresh each of the memory banks MBK0-MBK7 with different time difference. Concretely, the time difference tRF_1 between the MBK0 and MBK1 in an initial stage is made large, the time difference is stepwise reduced up to the time difference tRF_4 between the MBK3 and MBK4 in an intermediate stage, and then the difference is stepwise increased up to the time difference tRF_7 between the MBK6 and MBK7 in a final stage. Thus, a power source current waveform in refresh operation becomes sinusoidal, thereby the power source noise can be reduced in accordance with the reduction in harmonic components.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：提供减少电源噪声的半导体器件和信息处理系统。解决方案：DRAM存储器包括例如8个存储体MBK0-MBK7。进行控制以用不同的时间差刷新每个存储体MBK0-MBK7。具体地说，在初始阶段MBK0与MBK1之间的时差tRF_1变大，在中间阶段将时差逐步减小到MBK3与MBK4之间的时间差tRF_4，然后逐渐增加到在最后阶段MBK6和MBK7之间的时差tRF_7。因此，刷新动作中的电源电流波形变为正弦波，从而能够根据谐波分量的降低来降低电源噪声。版权所有（C）2010，JPO＆INPIT

4. 发明专利

JP2007065765A Designing method for semiconductor device, designing support system, program and semiconductor package 有权
标题翻译：半导体器件设计方案，设计支持系统，程序和半导体封装
公开(公告)号：JP2007065765A
公开(公告)日：2007-03-15
申请号：JP2005247935
申请日：2005-08-29
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： KATAGIRI MITSUAKI , NAKAMURA SATOSHI , SUGA TAKU , ISA SATOSHI , NISHIO YOJI , SENBA SEIJI , HIROSE YUKITOSHI
IPC分类号： G06F17/50 , H01L21/82 , H01L23/12 , H05K3/00
CPC分类号： H05K3/0005 , G06F17/5068 , H01L2224/05553 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2924/15311 , H01L2924/181 , H01L2924/3011 , H05K1/0231 , H05K2201/10545 , H05K2201/10734 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To propose a new design method for reducing a designing period. SOLUTION: In this designing method, an impedance model of an adjustment target system is calculated from adjustment target system information (step S101), a model of the whole semiconductor system is derived from a previously created chip model or a chip model created on the basis of design data and the impedance model, and a voltage fluctuation spectrum (an adjustment target value) is calculated (step S102). It is compared with a restriction value (a voltage fluctuation spectrum) in a frequency area (step S103). When a frequency portion regarded as questionable is present, a part to be performed with a design change is specified from a corresponding frequency portion, and the design change to be performed (a design guideline) is determined (step S104). COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提出一种减少设计周期的新设计方法。解决方案：在该设计方法中，根据调整目标系统信息计算调整目标系统的阻抗模型（步骤S101），从先前创建的芯片模型或创建的芯片模型导出整个半导体系统的模型根据设计数据和阻抗模型，计算电压波动谱（调整对象值）（步骤S102）。将其与频率区域中的限制值（电压波动谱）进行比较（步骤S103）。当存在被认为有问题的频率部分时，从对应的频率部分指定要进行设计变更的部分，并且确定要执行的设计变更（设计准则）（步骤S104）。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2006266702A Multi-chip package or system-in package 有权
标题翻译：多芯片封装或系统封装
公开(公告)号：JP2006266702A
公开(公告)日：2006-10-05
申请号：JP2005081261
申请日：2005-03-22
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： NAKAMURA SATOSHI , SUGA TAKU , KATAGIRI MITSUAKI , HIROSE YUKITOSHI
IPC分类号： G01R31/28 , G11C29/02 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： G11C5/04 , G11C5/063 , G11C29/1201 , G11C29/48 , G11C2029/0401 , G11C2029/3602 , H01L2224/32145 , H01L2224/48145 , H01L2224/48227 , H01L2225/06568 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a multi-chip package or a system-in package that has low noise and high operational reliability.
SOLUTION: In the multi-chip package or system-in package, a selector circuit allowing access to a memory control signal from a logic signal connected to the logic chip to m memory chips by transmitting a test mode change signal or test mode change command to the logic chip is built in the logic chip. The memory control signal is connected via a one-to-one wire or a one-to-m branch wires in the view from the logic chip between the selector circuit and m memory chips.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供具有低噪声和高操作可靠性的多芯片封装或系统级封装。解决方案：在多芯片封装或系统级封装中，选择器电路允许通过发送测试模式改变信号或测试模式来访问连接到逻辑芯片的逻辑信号到存储器芯片的存储器控制信号逻辑芯片内置了改变命令的逻辑芯片。存储器控制信号通过选择器电路和m个存储器芯片之间的逻辑芯片的一对一线或一对m分支线连接。版权所有（C）2007，JPO＆INPIT

6. 发明专利

JP2006032823A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2006032823A
公开(公告)日：2006-02-02
申请号：JP2004212654
申请日：2004-07-21
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： UEMATSU YUTAKA , OSAKA HIDEKI , NISHIO YOJI , HIROSE YUKITOSHI
IPC分类号： H01L27/04 , H01L21/82 , H01L21/822
CPC分类号： H01L23/642 , H01L23/5223 , H01L23/5228 , H01L23/5286 , H01L23/647 , H01L25/105 , H01L2224/73204 , H01L2924/19105 , H01L2924/3011
摘要： PROBLEM TO BE SOLVED: To solve the problem wherein the number of power/ground pins is increased and the inductance of the power lines is increased, in the prior art method for providing an output buffer separately from a power line for a control circuit to avoid power noise generated in the control circuit from affecting the output buffer.
SOLUTION: A technique for avoiding noise as a problem in the control circuit from being passed to the output buffer, while preventing (1) an increase in the number of power/ground pins and (2) increase in the inductance of the power lines is provided. There are two methods (A) and (B) in the specific technique; that is, (A) an on-chip bypass capacitance for the control circuit is provided to separate the control circuit from the power supply path of the output buffer when viewed as an AC circuit, and (B) such a design is made that the vibration mode of electrical parameter noise of the power supply path becomes overdamping (resistance insertion).
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题为了解决电力/接地引脚数量增加并且电力线路的电感增加的问题，在用于提供与用于控制的电力线路分开的输出缓冲器的现有技术方法中电路，以避免控制电路中产生的功率噪声影响输出缓冲器。解决方案：在防止（1）增加电源/接地引脚数量的同时，防止噪声作为控制电路中的问题传递到输出缓冲器的技术，（2）增加电感/ 提供电源线。具体技术有两种方法（A）和（B）; 也就是说，（A）用于控制电路的片上旁路电容被提供以将其视为AC电路时将控制电路与输出缓冲器的电源路径分开，并且（B）这样设计使得供电路径的电气参数噪声的振动模式变得过阻（电阻插入）。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2011199164A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2011199164A
公开(公告)日：2011-10-06
申请号：JP2010066542
申请日：2010-03-23
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： IKEDA YASUHIRO , UEMATSU YUTAKA , KATAGIRI MITSUAKI , HIROSE YUKITOSHI , MORIYA TAKUYA
IPC分类号： H01L27/04 , H01L21/822
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device 10, capable of reducing both SSO noise between V-G and SSO noise between S-G.SOLUTION: The semiconductor device 10 provides a near on-chip bypass capacitor 23 of capacity having a predetermined relationship to an input capacitance 34 of a receiving circuit 15 for each output circuit 12 as to be a predetermined wiring resistance, and a distant on-chip bypass capacitor 24 whose capacity and wiring resistance have the predetermined relationship for each output circuit 12 is provided to a plurality of output circuits 12 in common.
摘要翻译：要解决的问题：提供一种半导体器件10，其能够降低SG和SG之间的VG和SSO噪声之间的SSO噪声。解决方案：半导体器件10提供具有与输入的预定关系的容量的近似片上旁路电容器23 每个输出电路12的接收电路15的电容34作为预定的布线电阻，并且具有对于每个输出电路12具有预定关系的容量和布线电阻的远的片上旁路电容器24被提供给多个输出电路12相同。

8. 发明专利

JP2011196934A Testing method and interposer used for the same 审中-公开
标题翻译：测试方法和使用它的插入器
公开(公告)号：JP2011196934A
公开(公告)日：2011-10-06
申请号：JP2010066543
申请日：2010-03-23
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： UEMATSU YUTAKA , OSAKA HIDEKI , NAKAMURA SATOSHI , MURAOKA SATOSHI , KATAGIRI MITSUAKI , IWAKURA KEN , HIROSE YUKITOSHI
IPC分类号： G01R31/26
CPC分类号： G01R31/2889
摘要： PROBLEM TO BE SOLVED: To provide a test system 10 for finding an eliminable terminal in an IC of a BGA package.SOLUTION: The test system 10 includes: connecting an IC 11 of a BGA package with a test substrate 16 via an interposer 20 where a probe for detecting current and a switch are provided for each terminal of the BGA package; turning off the switch connected to at least one power terminal of the IC 11 to input a test pattern signal to the IC 11 via the test substrate 16; and specifying a power terminal connected to the switch that has been turned off as an eliminable terminal, when the IC 11 operates normally and current values of all the terminals of the IC 11 are within tolerance.
摘要翻译：要解决的问题：提供一种用于在BGA封装的IC中找到可消除端子的测试系统10.解决方案：测试系统10包括：通过插入器20将BGA封装的IC 11与测试衬底16连接，为BGA封装的每个端子提供用于检测电流和开关的探针; 关闭连接到IC 11的至少一个电源端子的开关，以经由测试基板16将测试图案信号输入到IC 11; 并且当IC 11正常工作并且IC 11的所有端子的当前值在公差内时，指定连接到已经被关闭的开关的电源端子作为可消除端子。

9. 发明专利

JP2008004853A Laminated semiconductor device, and module 审中-公开
标题翻译：层压半导体器件和模块
公开(公告)号：JP2008004853A
公开(公告)日：2008-01-10
申请号：JP2006174687
申请日：2006-06-26
申请人： Elpida Memory Inc , Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： UEMATSU YUTAKA , OSAKA HIDEKI , SHOJI KAZUYOSHI , NISHIO YOJI , HIROSE YUKITOSHI , ITAYA SATORU
IPC分类号： H01L25/065 , H01L23/12 , H01L25/07 , H01L25/18
CPC分类号： H01L2224/16145 , H01L2924/01055
摘要： PROBLEM TO BE SOLVED: To provide a technique contributing to an improvement of power supply efficiency to an upper layer semiconductor chip, reduction of power supply noise interference between upper and lower semiconductor chips, attainment of the low power supply noise, and high speed operation of a laminated semiconductor device (CoC).
SOLUTION: In the laminated semiconductor device, an interposer 11 is inserted between laminated semiconductor chips 1, 1. The interposer 11 has a feature of its being a high dielectric material such as ceramic whereby the intereposer enjoys both of an electric charge storage function by high capacitance, and of small size filter function. Use of a ceramic interposer having such functions ensures an improvement of power supply capability to the upper layer semiconductor chip noise interference reduction between the upper and lower semiconductor chips.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种有助于提高上层半导体芯片的电源效率的技术，降低上下半导体芯片之间的电源噪声干扰，实现低电源噪声和高层叠半导体器件（CoC）的快速操作。解决方案：在层叠半导体器件中，插入层11插入层叠的半导体芯片1,1之间。插入件11具有诸如陶瓷之类的高介电材料的特征，由此，插入器既具有电荷存储功能由高电容和小尺寸滤波功能。使用具有这种功能的陶瓷插入件确保了上层半导体芯片对上半导体芯片和下半导体芯片之间的噪声干扰降低的电力供应能力的改善。版权所有（C）2008，JPO＆INPIT

10. 发明专利

JP2011124995A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2011124995A
公开(公告)日：2011-06-23
申请号：JP2010260155
申请日：2010-11-22
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： UEMATSU YUTAKA , OSAKA HIDEKI , NISHIO YOJI , HIROSE YUKITOSHI
IPC分类号： H03K19/00 , H01L21/822 , H01L27/04 , H03K19/003
摘要： PROBLEM TO BE SOLVED: To solve the following problem: in the conventional arts, there is a method of separately providing power supply lines of an output buffer and a control circuit in order to prevent the output buffer from being affected by power supply noise caused in the control circuit, but this method has problems such as an increase in the number of power supply/ground pins and an increase in feed line inductance. SOLUTION: This invention relates to a technology such that noise becoming a problem in a control circuit does not sneak into an output buffer without increasing the number of power supply/ground pins (1) and without increasing the feed line inductance (2). As a specific technique, there are provided methods for (A) providing on-chip bypass capacitance for the control circuit to separate power feeding routes of the control circuit and the output buffer in an AC manner and (B) designing (inserting resistance) in such a manner that the vibration mode of electric parameter noise in the power feeding route becomes over-attenuation. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：解决以下问题：在现有技术中，存在分开设置输出缓冲器和控制电路的电源线的方法，以防止输出缓冲器受电源的影响在控制电路中引起的噪声，但是该方法具有电源/接地引脚数量的增加和馈线电感的增加等问题。解决方案本发明涉及一种技术，使得成为控制电路中的问题的噪声不会在不增加电源/接地引脚（1）的数量的情况下潜入输出缓冲器而不增加馈线电感（2 ）。作为具体技术，提供了用于（A）为控制电路提供片上旁路电容以以AC方式分离控制电路和输出缓冲器的馈电路径的方法，（B）设计（插入电阻）使得馈电路径中的电参数噪声的振动模式变得过度衰减。版权所有（C）2011，JPO＆INPIT

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