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1. 发明专利

JP2003044349A Register and signal generating method 审中-公开
标题翻译：寄存器和信号发生方法
公开(公告)号：JP2003044349A
公开(公告)日：2003-02-14
申请号：JP2001229039
申请日：2001-07-30
申请人： Eastern Japan Semiconductor Technologies Inc , Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所 , 株式会社東日本セミコンダクタテクノロジ−ズ
发明人： NISHIO YOJI , SENBA SEIJI , SHIBATA KAYOKO , KANNO TOSHIO , IKEDA HIROAKI , IIZUKA TAKUO , TANMACHI MASAYUKI
IPC分类号： G11C11/407 , G06F12/00 , G06F12/06 , G11C5/00 , G11C7/00 , G11C7/10 , G11C11/401 , G11C11/4076 , G11C11/409 , G11C11/4093 , H03K5/14 , H03L7/081
CPC分类号： G11C5/04 , G11C5/00 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/222 , H03L7/0814
摘要： PROBLEM TO BE SOLVED: To provide a register capable of coping with a wide frequency range and without depending on the number of mounted devices.
SOLUTION: A value of an external delay replica 50 is fixed and set by assuming the maximum value of the number of devices to be coped with. Setting of the realistic maximum and minimum values to an internal delay replica 403 is possible by dividing a desired frequency range into a plurality of sub- frequency ranges and using delay quantity of an output buffer and the internal delay replica 403 by switching them by every individual sub-frequency range. Selection of the delay quantity in the internal delay replica 403 can be performed by a selection pin 404. Thus, sufficient setup time and hold time are secured to an internal clock signal intCLK generated by DLL(Delay Locked Loop) regarding a latch operation inside the register without depending high/low of frequency and the number of mounted devices if the frequency is within the desired range and unless the permitted number of devices is exceeded.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供能够应付宽频率范围并且不依赖于安装的装置的数量的寄存器。解决方案：外部延迟复制品50的值是固定的，并通过假设要处理的设备的数量的最大值进行设置。通过将期望的频率范围分割成多个子频率范围并使用输出缓冲器和内部延迟复制品403的延迟量通过每个个体切换它们来实现对内部延迟复制品403的实际最大值和最小值的设置次频范围。可以通过选择引脚404来执行内部延迟复制品403中的延迟量的选择。因此，足够的建立时间和保持时间被确保到关于DLL内的锁存操作的DLL（延迟锁定环）产生的内部时钟信号intCLK 寄存器，不依赖于高/低频率和安装设备的数量，如果频率在期望的范围内，除非超过允许的设备数量。

2. 发明专利

JP2003044350A Register, memory module and memory system 有权
标题翻译：寄存器，存储器模块和存储器系统
公开(公告)号：JP2003044350A
公开(公告)日：2003-02-14
申请号：JP2001229230
申请日：2001-07-30
申请人： Eastern Japan Semiconductor Technologies Inc , Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所 , 株式会社東日本セミコンダクタテクノロジ−ズ
发明人： NISHIO YOJI , SENBA SEIJI , SHIBATA KAYOKO , KANNO TOSHIO , IKEDA HIROAKI , IIZUKA TAKUO , TANMACHI MASAYUKI
IPC分类号： G11C11/407 , G06F12/00 , G06F12/06 , G11C7/10 , G11C8/00 , G11C8/06 , G11C11/409
CPC分类号： G11C7/109 , G11C7/1078 , G11C7/1087 , G11C8/06 , G11C2207/107
摘要： PROBLEM TO BE SOLVED: To provide a register capable of coping with a wide frequency range and without depending on the number of mounted devices. SOLUTION: First and second preprocessing flip-flop FF1a and FF1b latch a C/A signal (CAint) inputted in a register 40a with a clock (0.5WCLKint) having a frequency of a half of that of an external clock signal WCLK and its inversion clock. Thus, the C/A signal is temporarily extended to a set of signals (0.5CA-a and 0.5CA-b) having double cycle. Since the signals 0.5CA-a and 0.5CA-b have the double cycle of that of the C/A signal (CAint), first and second post-processing flip-flops FF2a and FF2b can perform the latch operations according to an internal clock signal intCLK generated by a DLL circuit in a state that the sufficient setup time and hold time are secured.
摘要翻译：要解决的问题：提供能够应付宽频率范围并且不依赖于安装的装置的数量的寄存器。解决方案：第一和第二预处理触发器FF1a和FF1b使用具有外部时钟信号WCLK的一半的频率的时钟（0.5WCLKint）来锁存在寄存器40a中输入的C / A信号（CAint），并且其反相时钟。因此，C / A信号被暂时扩展到具有双周期的一组信号（0.5CA-a和0.5CA-b）。由于信号0.5CA-a和0.5CA-b具有C / A信号（CAint）的双周期，因此第一和第二后处理触发器FF2a和FF2b可以根据内部时钟执行锁存操作在保证足够的建立时间和保持时间的状态下由DLL电路生成的信号intCLK。

3. 发明专利

JP2006173409A Module 有权
标题翻译： MODULE
公开(公告)号：JP2006173409A
公开(公告)日：2006-06-29
申请号：JP2004365004
申请日：2004-12-16
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： UEMATSU YUTAKA , OSAKA HIDEKI , NISHIO YOJI , SENBA SEIJI
IPC分类号： H01L21/8238 , G06F3/00 , G11C11/401 , H01L27/092
CPC分类号： H05K1/023 , H01L23/50 , H01L23/66 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L2224/32145 , H01L2224/48091 , H01L2224/48145 , H01L2224/48195 , H01L2224/48472 , H01L2224/49 , H01L2225/0651 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H05K1/0227 , H05K1/0231 , H05K1/0233 , H05K1/025 , H05K1/181 , H05K2201/093 , H05K2201/09663 , H05K2201/10022 , H05K2201/1003 , H05K2201/10159 , H05K2201/10522 , H05K2201/10545 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a module wiring method by which both auto-noise and propagation noise can be effectively reduced. SOLUTION: In a memory module, a plurality of memories 2 are mounted on a module substrate 1, Vref-Vss impedance near the memories 2 is coupled with Vss by a decoupling capacitor 5 and Vref planes 4 to reduce impedance, the Vref plane 4 is individually provided for each memory 2, and the Vref planes 4 are connected by high-impedance wiring or high-impedance chip components 3-1, 3-2. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供可以有效降低自噪声和传播噪声的模块布线方法。解决方案：在存储器模块中，多个存储器2安装在模块基板1上，存储器2附近的Vref-Vss阻抗通过去耦电容器5和Vref平面4与Vss耦合以减小阻抗，Vref 每个存储器2分别提供平面4，并且Vref平面4通过高阻抗布线或高阻抗芯片组件3-1,3-2连接。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2009303245A Semiconductor device with digital interface 有权
标题翻译：具有数字接口的半导体器件
公开(公告)号：JP2009303245A
公开(公告)日：2009-12-24
申请号：JP2009216805
申请日：2009-09-18
申请人： Elpida Memory Inc , Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： OSAKA HIDEKI , NISHIO YOJI , SENBA SEIJI , SHOJI KAZUYOSHI
IPC分类号： H04L7/02 , G06F3/00 , H03K5/00 , H03K5/135 , H04L25/03
摘要： PROBLEM TO BE SOLVED: To provide an LSI, for reducing jitter depending on a data pattern by using a receiver of an interface, which is capable of automatically adjusting setting of a delay amount for reduction. SOLUTION: In a semiconductor device, since a previous state of data pattern dependent jitter is predictable, a state of data received by a receiver is held and timing to capture input data is adjusted from the held state and from input data. As an adjustment mechanism inside the receiver for determining a delay amount depending on a mounting form, pulse data at intervals of one cycle and pulse data at intervals of two cycles are transmitted/received from a driver as a test pattern. An automatic adjustment mechanism for determining a delay amount optimal for a system from a rising and falling time difference of pulses having different pulse widths, is provided. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种用于通过使用能够自动调整用于减小的延迟量的设置的接口的接收器来减少根据数据模式的抖动的LSI。解决方案：在半导体器件中，由于数据模式相关抖动的先前状态是可预测的，因此保持由接收器接收的数据的状态，并且从保持状态和输入数据调整捕获输入数据的定时。作为用于根据安装形式确定延迟量的接收器内的调节机构，以一个周期的间隔的脉冲数据和以两个周期的间隔的脉冲数据作为测试图案从驾驶员发送/接收。提供了一种用于从具有不同脉冲宽度的脉冲的上升和下降时间差确定系统最优的延迟量的自动调整机构。版权所有（C）2010，JPO＆INPIT

5. 发明专利

JP2007065765A Designing method for semiconductor device, designing support system, program and semiconductor package 有权
标题翻译：半导体器件设计方案，设计支持系统，程序和半导体封装
公开(公告)号：JP2007065765A
公开(公告)日：2007-03-15
申请号：JP2005247935
申请日：2005-08-29
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： KATAGIRI MITSUAKI , NAKAMURA SATOSHI , SUGA TAKU , ISA SATOSHI , NISHIO YOJI , SENBA SEIJI , HIROSE YUKITOSHI
IPC分类号： G06F17/50 , H01L21/82 , H01L23/12 , H05K3/00
CPC分类号： H05K3/0005 , G06F17/5068 , H01L2224/05553 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2924/15311 , H01L2924/181 , H01L2924/3011 , H05K1/0231 , H05K2201/10545 , H05K2201/10734 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To propose a new design method for reducing a designing period. SOLUTION: In this designing method, an impedance model of an adjustment target system is calculated from adjustment target system information (step S101), a model of the whole semiconductor system is derived from a previously created chip model or a chip model created on the basis of design data and the impedance model, and a voltage fluctuation spectrum (an adjustment target value) is calculated (step S102). It is compared with a restriction value (a voltage fluctuation spectrum) in a frequency area (step S103). When a frequency portion regarded as questionable is present, a part to be performed with a design change is specified from a corresponding frequency portion, and the design change to be performed (a design guideline) is determined (step S104). COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提出一种减少设计周期的新设计方法。解决方案：在该设计方法中，根据调整目标系统信息计算调整目标系统的阻抗模型（步骤S101），从先前创建的芯片模型或创建的芯片模型导出整个半导体系统的模型根据设计数据和阻抗模型，计算电压波动谱（调整对象值）（步骤S102）。将其与频率区域中的限制值（电压波动谱）进行比较（步骤S103）。当存在被认为有问题的频率部分时，从对应的频率部分指定要进行设计变更的部分，并且确定要执行的设计变更（设计准则）（步骤S104）。版权所有（C）2007，JPO＆INPIT

6. 发明专利

JP2004165605A Semiconductor unit, semiconductor module, and memory system 有权
公开(公告)号：JP2004165605A
公开(公告)日：2004-06-10
申请号：JP2003103681
申请日：2003-04-08
申请人： Elpida Memory Inc , Hitachi Ltd , Renesas Eastern Japan Semiconductor Inc , エルピーダメモリ株式会社 , 株式会社ルネサス東日本セミコンダクタ , 株式会社日立製作所
发明人： SENBA SEIJI , ANPO HISASHI , ONO TAKAO , HOSOKAWA KOJI , NISHIO YOJI , NAKAMURA ATSUSHI , SATO TOMOHIKO
IPC分类号： G06F12/00 , G06F13/16 , G11C5/00 , G11C11/24 , H01L23/12 , H01L23/52 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L25/105 , H01L23/50 , H01L23/552 , H01L23/60 , H01L23/64 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2223/6627 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/05599 , H01L2224/06136 , H01L2224/48091 , H01L2224/4824 , H01L2224/49171 , H01L2224/85399 , H01L2225/1023 , H01L2225/1058 , H01L2225/107 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/0102 , H01L2924/01029 , H01L2924/01033 , H01L2924/014 , H01L2924/13091 , H01L2924/15173 , H01L2924/15192 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/19032 , H01L2924/19041 , H01L2924/19051 , H01L2924/19106 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H01L2924/3025 , H05K1/112 , H05K1/14 , H05K1/181 , H05K2201/09236 , H05K2201/10159 , H05K2201/10545 , Y02P70/611 , H01L2224/45099 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor unit capable of a high-speed operation, by contracting the wiring length of a branch wiring existent in its signal wiring. SOLUTION: A semiconductor unit 104, constituting a memory device comprises a memory chip 120 and a package board 121, has three wiring layers. The wirings of power-supply surfaces 118 (a VDD surface), 119 (a GND surface) are formed in the package board 121, and the wiring of an intra-package DQ bus 114 is formed in an intermediate wiring layer, interposed between both the power-supply surfaces 118, 119. The memory device 120 has two DQ pins 112 inside the one intra-package DQ bus 114. The intra-package DQ bus 114 and a signal-terminal pad 115 of the memory chip 120 are connected through the intermediary of a via. The via, whereby the intra-package DQ bus 114 and the signal-terminal pad are connected, constitutes a branch wiring, as viewed from the two DQ pins. COPYRIGHT: (C)2004,JPO

7. 发明专利

JP2006041818A Semiconductor device having digital interface, memory element and memory module 有权
标题翻译：具有数字接口，存储器元件和存储器模块的半导体器件
公开(公告)号：JP2006041818A
公开(公告)日：2006-02-09
申请号：JP2004217509
申请日：2004-07-26
申请人： Elpida Memory Inc , Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： OSAKA HIDEKI , NISHIO YOJI , SENBA SEIJI , SHOJI KAZUYOSHI
IPC分类号： H04L7/02 , H03K5/00 , H03K5/135
CPC分类号： H03K5/082 , H03K5/135
摘要： PROBLEM TO BE SOLVED: To provide an LSI in which the setting of a delay amount for reducing jitter dependent on data pattern can be adjusted automatically for each device by a receiver at an interface. SOLUTION: Since data pattern dependent jitter can be predicted from a previous state, the state of data received by a receiver is held and timing for taking in the input data is adjusted based on the held state and the inputted data. On the other hand, pulse data of a 1 cycle interval and a 2 cycle interval are transmitted and received as test data to/from a driver as an adjusting mechanism in the receiver for determining a delay amount dependent on the mounting state. An automatic adjusting mechanism for determining a delay amount optimal to the system from the difference of rising and falling times of pulses having different pulse widths is provided. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种LSI，其中可以通过接口处的接收机自动地针对每个设备来调整用于减少依赖于数据模式的抖动的延迟量的设置。解决方案：由于可以从先前状态预测数据模式相关的抖动，所以保持由接收机接收的数据的状态，并且基于保持状态和输入的数据调整用于接收输入数据的定时。另一方面，1周期间隔和2周期间隔的脉冲数据作为测试数据作为测试数据作为测试数据作为接收机中的调整机构发送和接收，用于根据安装状态确定延迟量。提供了一种用于根据具有不同脉冲宽度的脉冲的上升和下降时间的差确定对系统最佳的延迟量的自动调整机构。版权所有（C）2006，JPO＆NCIPI

8. 发明专利

JP2005209168A Semiconductor memory module, memory system, circuit, semiconductor device and dimm 有权
标题翻译：半导体存储器模块，存储器系统，电路，半导体器件和DIMM
公开(公告)号：JP2005209168A
公开(公告)日：2005-08-04
申请号：JP2004364743
申请日：2004-12-16
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： OSAKA HIDEKI , NISHIO YOJI , SENBA SEIJI
IPC分类号： G06F12/00 , G06F1/10 , G06F13/16 , G11C7/10 , G11C7/22 , G11C8/00 , G11C11/4076 , G11C11/4093 , G11C29/02
CPC分类号： G11C29/028 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/4076 , G11C11/4093 , G11C29/02 , G11C29/50012
摘要： PROBLEM TO BE SOLVED: To solve a problem that it is hard to synchronize timing since a DQ signal is directly wired from a terminal of DIMM(Dual Inline Memory Module) while a C/A signal in the DIMM is distributed to each DRAM via a register in the DIMM. SOLUTION: The register is provided to speed up the C/A signal of the DIMM to perform high speed operation and wiring from the register is wired as daisy chain wiring. Then, the sum of delay time from the register to each DRAM and delay amount of a timing adjusting circuit becomes equal to delay time in a DRAM at the farthest end by the timing adjustment circuit provided with wiring delay time difference of the C/A signal and a clock signal different by DRAM locations in the DRAM. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了解决由于将DIMM信号直接从DIMM（双列直插式存储器模块）的端子直接连接而将DIMM中的C / A信号分配给每个时，难以同步定时的问题 DRAM通过DIMM中的寄存器。
解决方案：提供寄存器以加快DIMM的C / A信号，以执行高速运行，寄存器中的布线以菊花链布线布线。然后，由寄存器到每个DRAM的延迟时间和定时调整电路的延迟量的和等于由最后一端的DRAM中的延迟时间，该定时调整电路具有C / A信号的布线延迟时间差以及DRAM中DRAM位置不同的时钟信号。版权所有（C）2005，JPO＆NCIPI

9. 发明专利

JP2007219930A Simulation method and program 审中-公开
标题翻译：模拟方法与程序
公开(公告)号：JP2007219930A
公开(公告)日：2007-08-30
申请号：JP2006041009
申请日：2006-02-17
申请人： Elpida Memory Inc , Hitachi Ulsi Systems Co Ltd , エルピーダメモリ株式会社 , 株式会社日立超エル・エス・アイ・システムズ
发明人： NISHIO YOJI , SENBA SEIJI , AOKI HIYAKUGOUKO , SHOJI KAZUYOSHI , MATSUO KOJI , OTSUKA MARIKO , IKEMATSU RYUICHI , NONOYAMA SADAHIRO , FUJII YOSHIE
IPC分类号： G06F17/50 , G01R31/28
CPC分类号： G06F17/5009
摘要： PROBLEM TO BE SOLVED: To provide a simulation method allowing setting of a parameter related to an input/output characteristic on a user side about a memory having a plurality of chips.
SOLUTION: The simulation method has steps of: selecting one from a plurality of parameters related to the input/output characteristic; determining whether to set selection by a comment symbol for preventing execution of a corresponding line or to set the selection by an identification code that is an identifier common to the chips set to the same selection, to the setting line provided in a file for setting the necessary selection from a plurality of pieces of the selection of the selected parameter; deleting the comment symbol of the setting line of the necessary selection of the plurality of pieces of the selection and making the setting line effective when setting the selection by the comment symbol, and replacing the identification code included in the setting line with information for setting the necessary selection when setting the selection by the identification code; and executing simulation.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种允许在具有多个芯片的存储器上设置与用户侧的输入/输出特性有关的参数的模拟方法。解决方案：模拟方法具有以下步骤：从与输入/输出特性相关的多个参数中选择一个; 确定是否通过用于防止相应行的执行的注释符号来设置选择，或者通过作为设置为相同选择的芯片共有的标识符的识别码将选择设置到设置在用于设置从所选择的参数的多个选择中进行必要的选择; 删除多条选择的必要选择的设定行的注释符号，并且在通过注释符号设置选择时使设置行有效，并且将包括在设置行中的识别码替换为用于设置通过识别码设置选择时的必要选择; 并执行仿真。版权所有（C）2007，JPO＆INPIT

10. 发明专利

JP2004312262A Signal transmission system 有权
标题翻译：信号传输系统
公开(公告)号：JP2004312262A
公开(公告)日：2004-11-04
申请号：JP2003101741
申请日：2003-04-04
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： NISHIO YOJI , SENBA SEIJI
IPC分类号： H03K19/0175 , G11C7/10
CPC分类号： H04L5/16 , G11C7/1006 , H04L25/0278
摘要： PROBLEM TO BE SOLVED: To provide a signal transmission system for suppressing a timing skew between semiconductor integrated circuit devices operated at different power supply voltages and suppressing a cost increase. SOLUTION: The signal transmission system wherein a signal is transmitted / received between the semiconductor integrated circuit devices operated at different power supply voltages includes: a transmission line with a prescribed characteristic impedance for interconnecting the semiconductor integrated circuit devices; drivers of a Push-pull configuration respectively provided to the semiconductor integrated circuit devices; and a receiver the signal receiving end of which is CTT-terminated by a termination resistor, and the termination resistor is configured such that the ON-resistance of the driver is selected so that an identical reference voltage is applied to the two semiconductor integrated circuit devices when the termination resistance is coincident with the characteristic impedance, and an identical reference voltage is applied to the two semiconductor integrated circuit devices when the ON-resistance of the driver is coincident with the characteristic impedance. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于抑制在不同电源电压下操作的半导体集成电路器件之间的定时偏移的信号传输系统，并抑制成本增加。解决方案：在以不同电源电压工作的半导体集成电路器件之间发送/接收信号的信号传输系统包括：具有用于互连半导体集成电路器件的规定特性阻抗的传输线; 分别提供给半导体集成电路器件的推挽配置的驱动器; 以及接收器，其信号接收端由端接电阻CTT端接，并且终端电阻被配置为使得驱动器的导通电阻被选择，使得相同的参考电压被施加到两个半导体集成电路器件当终端电阻与特性阻抗一致时，并且当驱动器的导通电阻与特性阻抗一致时，相同的参考电压被施加到两个半导体集成电路器件。版权所有（C）2005，JPO＆NCIPI

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