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1. 发明专利

JP2012069797A Insulated gate transistor 审中-公开
标题翻译：绝缘栅晶体管
公开(公告)号：JP2012069797A
公开(公告)日：2012-04-05
申请号：JP2010214240
申请日：2010-09-24
申请人： Denso Corp , Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： SUGIMOTO MASAHIRO , ISHIKAWA TAKESHI , SOEJIMA SHIGEMASA , WATANABE YUKIHIKO , SUZUKI MASAHIRO , MATSUKI HIDEO
IPC分类号： H01L29/78 , H01L29/739
摘要： PROBLEM TO BE SOLVED: To provide an insulated gate transistor, having a trench gate electrode with a high breakdown voltage characteristic, hardly producing a manufacturing error in the breakdown voltage characteristic.SOLUTION: The insulated gate transistor includes: a first region of first conductive type, formed in the range facing the upper surface of a semiconductor layer and connected to a first electrode; a second region of second conductive type, formed on the lower side of the first region; a third region of first conductive type formed on the lower side of the second region; a pair of fourth regions of second conductive type, connected to the first electrode; and a trench gate electrode. Each of the pair of fourth regions is formed on each side of a trench to sandwich the center of the trench. Each of the fourth regions has a vertical region extending to a position deeper than the lower end of an insulating film in the third region, and a horizontal region extending to the center side of the trench from the vertical region in the third region, in the position deeper than the lower end of the insulating film.
摘要翻译：解决的问题：为了提供具有高击穿电压特性的沟槽栅电极的绝缘栅晶体管，几乎不产生击穿电压特性的制造误差。解决方案：绝缘栅晶体管包括：第一导电类型的第一区域，形成在面向半导体层的上表面并连接到第一电极的范围内; 第二导电类型的第二区域，形成在第一区域的下侧; 形成在所述第二区域的下侧的第一导电类型的第三区域; 连接到第一电极的一对第二导电类型的第四区域; 和沟槽栅电极。一对第四区域中的每一个形成在沟槽的每一侧以夹住沟槽的中心。每个第四区域具有延伸到比第三区域中的绝缘膜的下端更深的位置的垂直区域，以及从第三区域中的垂直区域延伸到沟槽的中心侧的水平区域，在位置比绝缘膜的下端深。版权所有（C）2012，JPO＆INPIT

2. 发明专利

JP2012169385A Silicon carbide semiconductor device 审中-公开
标题翻译：硅碳化硅半导体器件
公开(公告)号：JP2012169385A
公开(公告)日：2012-09-06
申请号：JP2011027996
申请日：2011-02-11
申请人： Denso Corp , Toyota Motor Corp , Toyota Central R&D Labs Inc , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： MATSUKI HIDEO , YAMAMOTO KENSAKU , NOBORIO MASATO , SUZUKI MASAHIRO , TAKATANI HIDESHI , SUGIMOTO MASAHIRO , MORIMOTO JUN , SOEJIMA SHIGEMASA , ISHIKAWA TAKESHI , WATANABE YUKIHIKO
IPC分类号： H01L29/78 , H01L21/336 , H01L29/12 , H01L29/739
CPC分类号： H01L29/66068 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/7397 , H01L29/7813
摘要： PROBLEM TO BE SOLVED: To reduce the on-resistance when a deep layer is formed so as to intersect a trench configuring a trench gate structure.SOLUTION: The structure where a p-type deep layer 10 is separated entirely or partially from the inner wall surface of a trench 6, i.e. a layout where the p-type deep layer 10 is not in contact with any one of the side surface or the bottom face of the trench 6, is employed. For example, the p-type deep layer 10 is formed only in a place separated from a trench gate structure, so as not to come into contact with both the side surface and the bottom face of the trench gate structure. Consequently, the channel width can be widened when a channel is formed by applying a gate voltage to a gate electrode 9 during the on-time. When compared with a case where the p-type deep layer 10 is formed so as to come into contact with the trench 6, width of a JFET region can be widened and since the JFET resistance can be reduced, the on-resistance can be reduced.
摘要翻译：要解决的问题：当形成深层以与构成沟槽栅极结构的沟槽交叉时，降低导通电阻。解决方案：p型深层10完全或部分地从沟槽6的内壁表面分离的结构，即p型深层10不与任何一种使用沟槽6的侧表面或底面。例如，p型深层10仅形成在与沟槽栅极结构分离的位置，以便不与沟槽栅极结构的侧面和底面接触。因此，通过在导通时间对栅电极9施加栅极电压来形成通道时，可以扩大通道宽度。当与形成p型深层10以与沟槽6接触的情况相比较，可以扩大JFET区域的宽度，并且由于可以减小JFET电阻，可以降低导通电阻。版权所有（C）2012，JPO＆INPIT

3. 发明专利

JP2012009502A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2012009502A
公开(公告)日：2012-01-12
申请号：JP2010141744
申请日：2010-06-22
申请人： Denso Corp , Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： YAMAMOTO KENSAKU , SUZUKI MASAHIRO , TAKATANI HIDESHI , SUGIMOTO MASAHIRO , MORIMOTO ATSUSHI , SOEJIMA SHIGEMASA , ISHIKAWA TAKESHI , WATANABE YUKIHIKO
IPC分类号： H01L29/78 , H01L29/06 , H01L29/12
CPC分类号： H01L29/7811 , H01L29/0619 , H01L29/0661 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/407 , H01L29/66068 , H01L29/7397 , H01L29/7813 , H01L29/8613
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which enhances breakdown voltage by resolving occurence of discontinuity of material at an area contacting an electric field relaxation layer and omitting bent portions from the electric field relaxation layer.SOLUTION: The semiconductor device includes an electric field relaxation layer 3a for providing a peripheral breakdown voltage structure by using a p-type base layer 3. Accordingly, bent portions can be omitted from the electric field relaxation layer 3a. Since only an n-type drift layer 2a is a semiconductor which the electric field relaxation layer 3a is in contact with, discontinuity of materials does not occur. Consequently, breakdown voltage of an SiC semiconductor device can be enhanced.
摘要翻译：解决的问题：提供一种半导体器件，其通过解决在与电场弛豫层接触的区域处的材料不连续的发生并且从电场弛豫层省略弯曲部分来提高击穿电压。解决方案：半导体器件包括用于通过使用p型基极层3提供外围击穿电压结构的电场弛豫层3a。因此，可以从电场弛豫层3a省略弯曲部分。由于只有n

4. 发明专利

JP2011216783A Semiconductor device and method of manufacturing semiconductor device 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：JP2011216783A
公开(公告)日：2011-10-27
申请号：JP2010085438
申请日：2010-04-01
申请人： Denso Corp , Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： TAKATANI HIDESHI , MATSUKI HIDEO , SUZUKI MASAHIRO , ISHIKAWA TAKESHI
IPC分类号： H01L29/78 , H01L21/336 , H01L29/12
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having a structure such that a trench gate insulating film is not broken by an applied electric field without increasing the on resistance.SOLUTION: The semiconductor device includes a first semiconductor layer 12a of a first conductivity type formed on a semiconductor substrate 16, a second semiconductor layer 12b of the first conductivity type formed in a partial region on the first semiconductor layer, a third semiconductor layer 13 of a second conductivity type formed on the first semiconductor layer and second semiconductor layer, a trench having a bottom at the second semiconductor layer, a fourth semiconductor layer 17 of a first conductivity type formed on both sides of the trench, a gate insulating film 14 formed in the trench, and a gate electrode 15, wherein the gate insulating film is formed having a thicker film thickness on the bottom of the trench than that on a side face of the trench, and a depth-directional interface between the gate insulating film and gate electrode on the bottom of the trench is formed at a position deeper than a depth-directional interface between the second semiconductor layer and third semiconductor layer.
摘要翻译：要解决的问题：提供一种半导体器件，其具有这样的结构，使得沟槽栅极绝缘膜在不增加导通电阻的情况下不受施加的电场的破坏。解决方案：半导体器件包括第一导电类型的第一半导体层12a 形成在半导体基板16上，形成在第一半导体层上的部分区域中的第一导电类型的第二半导体层12b，形成在第一半导体层和第二半导体层上的第二导电类型的第三半导体层13，在第二半导体层具有底部的沟槽，形成在沟槽的两侧的第一导电类型的第四半导体层17，形成在沟槽中的栅极绝缘膜14和栅极电极15，其中栅极绝缘膜为在沟槽的底部形成的厚度比沟槽的侧面上的膜厚更深，并具有深度方向的相互之间沟槽底部的栅极绝缘膜与栅电极之间的面形成在比第二半导体层与第三半导体层之间的深度方向界面更深的位置。

5. 发明专利

JP2012216675A Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012216675A
公开(公告)日：2012-11-08
申请号：JP2011080794
申请日：2011-03-31
申请人： Toyota Motor Corp , Denso Corp , Toyota Central R&D Labs Inc , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： TAKATANI HIDESHI , MATSUKI HIDEO , SUZUKI MASAHIRO , ISHIKAWA TAKESHI , SOEJIMA SHIGEMASA , WATANABE YUKIHIKO
IPC分类号： H01L29/78 , H01L21/336 , H01L29/12
摘要： PROBLEM TO BE SOLVED: To improve voltage withstanding characteristics of a semiconductor device.SOLUTION: A semiconductor device 100 comprises a semiconductor substrate 102. On the semiconductor substrate, a p-type body region 141 is laminated on a surface of an n-type drift region 112. A trench 113 penetrates a surface of the semiconductor substrate 102 through the body region 141 to reach the drift region 112. A bottom of the trench 113 is coated with an oxide film 171. Lateral walls of the trench 113 are coated with an oxide film 171 and a gate oxide film 172. A top face 171a of the oxide film 171 is located on the lower side than a boundary surface B1 of the drift region 112 and the body region 141. A film thickness of the gate oxide film 172 is assumed to be a first film thickness t1 at least in a partial region on the upper side than the boundary surface B1. The film thickness of the oxide film 171 is made to be thicker than the first film thickness t1 in a region A1 from the top face 171a to the boundary surface B1.
摘要翻译：要解决的问题：提高半导体器件的耐压特性。解决方案：半导体器件100包括半导体衬底102.在半导体衬底上，p型体区141层压在n型漂移区112的表面上。沟槽113穿透半导体衬底102的表面衬底102通过体区141到达漂移区112.沟槽113的底部涂覆有氧化膜171.沟槽113的侧壁涂覆有氧化膜171和栅极氧化膜172。顶部氧化膜171的表面171a位于比漂移区域112和体区141的边界面B1的下侧。栅极氧化膜172的膜厚度假设为至少在在边界面B1上方的局部区域。在从顶面171a到边界面B1的区域A1中，氧化膜171的膜厚比第一膜厚度t1厚。版权所有（C）2013，JPO＆INPIT

6. 发明专利

JP2012019188A Semiconductor device and method of manufacturing semiconductor device 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：JP2012019188A
公开(公告)日：2012-01-26
申请号：JP2010275477
申请日：2010-12-10
申请人： Denso Corp , Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： TAKATANI HIDESHI , MATSUKI HIDEO , SUZUKI MASAHIRO , ISHIKAWA TAKESHI
IPC分类号： H01L29/06 , H01L21/336 , H01L29/78
CPC分类号： H01L29/1608 , H01L21/046 , H01L29/0619 , H01L29/0623 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/407 , H01L29/41741 , H01L29/4236 , H01L29/42368 , H01L29/49 , H01L29/66068 , H01L29/7397 , H01L29/7811 , H01L29/7813
摘要： PROBLEM TO BE SOLVED: To improve breakdown voltage characteristics of a semiconductor device.SOLUTION: A semiconductor device 100 comprises a termination area 107 surrounding a cell area 105. In the cell area 105, main trenches 113 are formed. In the termination area 107, termination trenches 161 to 163 that surround the cell area 105 are formed. The termination trench 161 is located at the innermost peripheral side of the termination trenches. A body region 141 is laminated on a surface of a drift region 112. The main trenches 113 reach the drift region 112, and have a gate electrode 122 formed therein. The termination trench 161 reaches the drift region 112. The sidewall and the bottom surface of the termination trench 161 are coated with an oxide film 171. The surface of the oxide film 171 coating the bottom surface of the termination trench 161 is coated with a buried electrode 124. A gate voltage is applied to the buried electrode 124.
摘要翻译：要解决的问题：提高半导体器件的击穿电压特性。解决方案：半导体器件100包括围绕单元区域105的终止区域107.在单元区域105中，形成主沟槽113。在终端区域107中，形成围绕单元区域105的终端沟槽161至163。终端沟槽161位于终端沟槽的最内侧。主体区域141层叠在漂移区域112的表面上。主沟槽113到达漂移区域112，并且在其中形成栅电极122。终端沟槽161到达漂移区域112.终端沟槽161的侧壁和底表面涂覆有氧化膜171.覆盖终端沟槽161的底表面的氧化膜171的表面涂覆有埋置电极124.栅极电压施加到埋入电极124.版权所有：（C）2012，JPO＆INPIT

7. 发明专利

JP2008185124A Sliding component 有权
标题翻译：滑动组件
公开(公告)号：JP2008185124A
公开(公告)日：2008-08-14
申请号：JP2007018980
申请日：2007-01-30
申请人： Toyota Central R&D Labs Inc , Toyota Industries Corp , 株式会社豊田中央研究所 , 株式会社豊田自動織機
发明人： SUGIOKA TAKAHIRO , KATO TAKAYUKI , YASUDA SHUICHI , SAITO ATSUSHI , SUZUKI MASAHIRO , MURASE KIMITOSHI , IZEKI TAKASHI , TACHIKAWA HIDEO , NAKANISHI KAZUYUKI , KOBAYASHI TAKAO , SUZUKI KENICHI
IPC分类号： F16C33/20 , F04B27/08 , F04B39/00
CPC分类号： F04B27/1054 , F05C2203/0817 , F05C2203/0882 , F05C2225/00 , F05C2251/14 , F05C2253/12 , F16C33/201
摘要： PROBLEM TO BE SOLVED: To provide a sliding component which shows furthermore excellent durability and contains no lead. SOLUTION: A swash plate 8 serving as the sliding component based on the present invention comprises a base material 81, and a sliding layer 82 which is formed on the surface of the base material 81, and at least composes a sliding surface 8a on which a shoe 21 slides. The sliding layer 82 is composed of a first layer 82a which is formed on the base material 81, and is composed of an amorphous hard carbon film (diamond-like carbon (DLC-Si)) containing Si, and a second layer 82b which is formed on the first layer 82a, and is composed of polyamideimide (PAI) containing solid lubricant, such as MoS 2 . COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种显示出更好的耐久性并且不含铅的滑动部件。解决方案：基于本发明的用作滑动部件的斜盘8包括基材81和形成在基材81的表面上的滑动层82，并且至少构成滑动面8a 鞋21滑动在其上。滑动层82由形成在基材81上的第一层82a构成，由含有Si的非晶硬质碳膜（类金刚石碳（DLC-Si））构成，第二层82b为形成在第一层82a上，并且由含有固体润滑剂的聚酰胺酰亚胺（PAI）如MoS SB2组成。版权所有（C）2008，JPO＆INPIT

8. 发明专利

JP2013089778A Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2013089778A
公开(公告)日：2013-05-13
申请号：JP2011229183
申请日：2011-10-18
申请人： Toyota Motor Corp , トヨタ自動車株式会社 , Denso Corp , 株式会社デンソー
发明人： TAKATANI HIDESHI , MATSUKI HIDEO , SUZUKI MASAHIRO , ISHIKAWA TAKESHI , SOEJIMA SHIGEO , WATANABE YUKIHIKO
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/4236 , H01L21/047 , H01L21/28008 , H01L21/823487 , H01L29/0619 , H01L29/0623 , H01L29/1608 , H01L29/41741 , H01L29/42368 , H01L29/66068 , H01L29/66666 , H01L29/7806 , H01L29/7813 , H01L29/7827
摘要： PROBLEM TO BE SOLVED: To inhibit a damage of a gate insulation film when breakdown occurs in a semiconductor device using a trench electrode.SOLUTION: A semiconductor manufacturing method comprises: forming source regions of a second conductivity type electrically connected to source electrodes 133, respectively, which are adjacent to a trench 113 penetrating a body region from a surface of a semiconductor substrate 102 to reach a drift region 112; forming a drain electrode 111 on a rear face of the semiconductor substrate; arranging at a bottom of the trench, a specific layer 181 having characteristics forming a depletion layer at a junction with the drift region; covering a top face of the specific layer and side walls of the trench with an insulation layer; forming a gate electrode 122 inside the trench covered with the insulation layer; forming on a part of trench side walls, conductive parts 182 extending along the trench side walls and in a depth direction of the semiconductor substrate; bonding first ends of the conductive parts to the specific layer; and making second ends of the conductive parts reach a surface of the semiconductor substrate and connecting the second ends to the source electrodes.
摘要翻译：要解决的问题：在使用沟槽电极的半导体器件中发生击穿时，抑制栅极绝缘膜的损坏。解决方案：半导体制造方法包括：分别形成与源电极133电连接的第二导电类型的源区，其与从半导体衬底102的表面穿透体区的沟槽113相邻以到达漂移区域112; 在半导体衬底的背面上形成漏电极111; 布置在沟槽的底部，具有在与漂移区域的接合处形成耗尽层的特性的特定层181; 用绝缘层覆盖沟槽的特定层和侧壁的顶面; 在覆盖有绝缘层的沟槽内形成栅电极122; 在沟槽侧壁的一部分上形成导电部分182，沿着沟槽侧壁延伸并沿着半导体衬底的深度方向延伸; 将导电部件的第一端接合到特定层; 并且使导电部件的第二端到达半导体基板的表面，并将第二端连接到源电极。版权所有（C）2013，JPO＆INPIT

9. 发明专利

JP2010147222A Silicon carbide semiconductor device and method of manufacturing the same 审中-公开
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：JP2010147222A
公开(公告)日：2010-07-01
申请号：JP2008322233
申请日：2008-12-18
申请人： Denso Corp , 株式会社デンソー
发明人： SUZUKI MASAHIRO , MATSUKI HIDEO , OKUNO HIDEKAZU
IPC分类号： H01L29/12 , H01L21/336 , H01L29/06 , H01L29/78
CPC分类号： H01L29/7813 , H01L29/0615 , H01L29/0619 , H01L29/0638 , H01L29/0661 , H01L29/1095 , H01L29/1608 , H01L29/66068 , H01L29/7811
摘要： PROBLEM TO BE SOLVED: To achieve a high withstand voltage by preventing breakdown in a deep layer in an SiC semiconductor device having the deep layer so as to cross a trench gate structure. SOLUTION: The SiC semiconductor device has a structure in which a p-type deep layer 10 is formed in the entire outer edge portion of a cell region to reach an outer peripheral region. With this structure, an equipotential line distribution is almost horizontal to the substrate plane in a joint portion between the p-type deep layer 10 and a p-type resurf layer 15 so that an electric field can be applied to almost the substrate vertical direction, i.e., the azimuth of [0001] plane. In this way, an electric field concentration portion when a drain voltage is high voltage is not a lower part of the joint portion between the p-type deep layer 10 and the p-type resurf layer 15, but a guard ring portion. As a result, breakdown in the p-type deep layer 10 can be prevented to achieve high withstand voltage. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：通过防止具有深层的SiC半导体器件中的深层中的破坏以跨越沟槽栅极结构来实现高耐受电压。解决方案：SiC半导体器件具有在单元区域的整个外边缘部分中形成p型深层10以到达外周区域的结构。利用这种结构，等电位线分布在p型深层10和p型重结晶层15之间的接合部分中与衬底平面几乎水平，使得电场几乎可以施加在衬底垂直方向上，即[0001]平面的方位角。以这种方式，当漏极电压为高电压时的电场集中部分不是p型深层10和p型再结晶层15之间的接合部分的下部，而是保护环部分。结果，可以防止p型深层10的击穿达到高耐压。版权所有（C）2010，JPO＆INPIT

10. 发明专利

JP2011101036A Silicon carbide semiconductor device and manufacturing method thereof 有权
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：JP2011101036A
公开(公告)日：2011-05-19
申请号：JP2011002286
申请日：2011-01-07
申请人： Denso Corp , 株式会社デンソー
发明人： SUZUKI MASAHIRO , MATSUKI HIDEO , OKUNO HIDEKAZU
IPC分类号： H01L29/78 , H01L21/336 , H01L29/06 , H01L29/12
摘要： PROBLEM TO BE SOLVED: To obtain high-pressure resistance by suppressing breakdown at a deep layer, in an SiC semiconductor device arranged with the deep layer so that the semiconductor device intersects with a trench gate structure. SOLUTION: In an entire area of an outer edge of a cell region including an outer peripheral region, p-type deep layers 10 are formed, and a p-type resurf layer 15 which is formed in a boundary position between the cell region of a mesa structure 14 and its periphery has the same depth as the p-type deep layer 10. This causes an equipotential-line distribution to be nearly horizontal to a substrate plane at a junction between the p-type deep layer 10 and the p-type resurf layer 15, thus enabling an electric field to match a direction substantially vertical to the substrate plane, or the azimuth direction of a [0001] plane. As a result, when a drain voltage becomes high, the electric field is concentrated on a guard ring rather than a lower portion of the junction between the p-type deep layer 10 and the p-type resurf layer 15. Therefore, it becomes possible to suppress breakdown at the p-type deep layer 10 and obtain the high-pressure resistance. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了通过抑制深层的击穿来获得高压电阻，在配置有深层的SiC半导体器件中，半导体器件与沟槽栅极结构相交。解决方案：在包括外围区域的单元区域的外边缘的整个区域中，形成p型深层10，以及形成在单元格之间的边界位置的p型复层15 台面结构14的区域及其周边具有与p型深层10相同的深度。这导致等电位线分布在p型深层10和因此能够使电场与基板平面基本垂直的方向或[0001]平面的方位方向相匹配。结果，当漏极电压变高时，电场集中在保护环上而不是p型深层10和p型重结晶层15之间的接合部的下部。因此，以抑制p型深层10的击穿并获得高压电阻。版权所有（C）2011，JPO＆INPIT

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