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1. 发明专利

JP2012169904A Semiconductor switching element driving circuit 有权
标题翻译：半导体开关元件驱动电路
公开(公告)号：JP2012169904A
公开(公告)日：2012-09-06
申请号：JP2011029731
申请日：2011-02-15
申请人： Denso Corp , 株式会社デンソー
发明人： KIMURA TOMONORI , TAKASU HISASHI
IPC分类号： H03K17/04 , H02M1/08 , H03K17/687
CPC分类号： H03K17/04123 , H03K2217/0081 , H03K2217/009
摘要： PROBLEM TO BE SOLVED: To provide a driving circuit which can switch, at a high frequency and at high speed, a semiconductor switching element limited in driving voltage to be applied.SOLUTION: By controlling four switches S1-S4 together with switches Sa1 and Sa2 by a conduction control circuit 4, a current is applied to an inductor L1 in two directions. A gate of an N-channel FET 1 is charged with the current flowing through the inductor L1 and the current is discharged from the gate. In particular, the conduction control circuit 4 includes a series circuit of the switches S1 and S2 connected between a cathode of a diode Da1 and an anode of a diode Da2, and a series circuit of the switches S3 and S4 connected between a capacitor C1 and a capacitor C2 with a common connection point being connected to a gate of the N-channel FET 1. The inductor L1 is connected between a common connection point of the switches S1 and S2, and the common connection point of the switches S3 and S4.
摘要翻译：要解决的问题：提供一种驱动电路，其能够以高频和高速切换限制要施加的驱动电压的半导体开关元件。解决方案：通过由导通控制电路4与开关Sa1和Sa2一起控制四个开关S1-S4，在两个方向上将电流施加到电感器L1。 N沟道FET1的栅极对流过电感器L1的电流进行充电，并且电流从栅极放电。特别地，导通控制电路4包括连接在二极管Da1的阴极和二极管Da2的阳极之间的开关S1和S2的串联电路，以及连接在电容器C1和具有公共连接点的电容器C2连接到N沟道FET1的栅极。电感器L1连接在开关S1和S2的公共连接点与开关S3和S4的公共连接点之间。版权所有（C）2012，JPO＆INPIT

2. 发明专利

JP2013207552A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2013207552A
公开(公告)日：2013-10-07
申请号：JP2012074437
申请日：2012-03-28
申请人： Denso Corp , 株式会社デンソー
发明人： TAKASU HISASHI , KIMURA TOMONORI
IPC分类号： H03K17/08 , H01L21/822 , H01L27/04 , H01L27/06
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of achieving a structure which can effectively protect a semiconductor switch element from surge voltage, while suppressing a reduction of a switching rate.SOLUTION: A semiconductor device 1 comprises: a voltage setting circuit 5 in which a first voltage setting circuit 11 and a second voltage setting circuit 12 are connected in series, formed between a drain terminal and a source terminal of a switch element SW1; and a first rectifier D1 in which its input terminal is connected to a connection part 6 side in the voltage setting circuit 5 and its output terminal is connected to a gate terminal side. A voltage applied to the gate terminal via the first rectifier D1, is less than a threshold value in normal time when an electric potential difference between the drain and the source is equal to or less than a predetermined value, and the voltage applied to the gate terminal via the first rectifier D1, increases so as to exceed the threshold value, and thereby the switch element SW1 turns ON to flow the current between the drain and the source in abnormal time when the electric potential difference between the drain and the source is more than the predetermined value.
摘要翻译：要解决的问题：提供能够实现能够有效地保护半导体开关元件免受浪涌电压的结构的半导体器件，同时抑制开关速率的降低。解决方案：半导体器件1包括：电压设定电路5，第一电压设定电路11和第二电压设定电路12串联连接，形成在开关元件SW1的漏极端子和源极端子之间; 以及第一整流器D1，其输入端子连接到电压设定电路5中的连接部分6侧，并且其输出端子连接到栅极端子侧。通过第一整流器D1施加到栅极端子的电压在漏极和源极之间的电位差等于或小于预定值的正常时间内小于阈值，并且施加到栅极的电压通过第一整流器D1的端子增加以超过阈值，从而当漏极和源极之间的电位差更多时，开关元件SW1导通以在异常时间内在漏极和源极之间流过电流超过预定值。

3. 发明专利

JP2013110515A Circuit for driving power semiconductor element 有权
标题翻译：电力半导体元件电路
公开(公告)号：JP2013110515A
公开(公告)日：2013-06-06
申请号：JP2011252884
申请日：2011-11-18
申请人： Denso Corp , 株式会社デンソー
发明人： KOBAYASHI ATSUSHI , TAKASU HISASHI
IPC分类号： H03K17/16 , H03K17/08 , H03K19/003
CPC分类号： H03K17/0822 , H03K17/08 , H03K2217/0027 , H03K2217/0045
摘要： PROBLEM TO BE SOLVED: To implement surge capacity improvement and overvoltage protection of a power semiconductor element without deteriorating high speed switching performance.SOLUTION: A gate control terminal 5 is provided in a position spaced by a predetermined distance from a drain terminal 1b, and a discharge is allowed to take place between the drain terminal 1b and the gate control terminal 5 in the event of a surge. The discharge phenomenon applies a surge voltage to the gate control terminal 5 to charge a gate of a power semiconductor element 1 until turning on the power semiconductor element 1 to absorb surge energy. This can reduce a surge voltage applied to the drain terminal 1b to prevent the power semiconductor element 1 from breaking down.
摘要翻译：要解决的问题：实现功率半导体元件的浪涌能力改进和过电压保护，而不会降低高速开关性能。解决方案：栅极控制端子5设置在与漏极端子1b隔开预定距离的位置，并且在漏极端子1b和栅极控制端子5之间允许放电发生在浪涌。放电现象向栅极控制端子5施加浪涌电压，以对功率半导体元件1的栅极充电直到接通功率半导体元件1以吸收浪涌能量。这可以减小施加到漏极端子1b的浪涌电压，以防止功率半导体元件1破裂。版权所有（C）2013，JPO＆INPIT

4. 发明专利

JP2014107662A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2014107662A
公开(公告)日：2014-06-09
申请号：JP2012258499
申请日：2012-11-27
申请人： Denso Corp , 株式会社デンソー
发明人： TAKASU HISASHI , KOBAYASHI ATSUSHI
IPC分类号： H03K17/08 , H02M1/00 , H02M1/08 , H03K17/695
摘要： PROBLEM TO BE SOLVED: To increase a tolerance to surge voltage while keeping a low parasitic capacitance of a gate and maintaining high speed switching performance.SOLUTION: When an off driving signal turns a FET 5 off, a surge voltage occurs to bring a drain-source voltage VDS of the FET 5 to or above a protective voltage Vm1. Meanwhile, a detection voltage by a first voltage detection circuit 6A becomes higher than a threshold voltage Vth to turn a FET 13 off and a FET 14 on in a control circuit 9, which in turn turns a FET 11 off to bring a switch circuit 8 to a high impedance. A detection voltage by a second voltage detection circuit 6B later raises a gate voltage VGS of the FET 5 to or above a gate threshold voltage via a diode 15. The FET 5 then shoots through to release energy of the surge voltage to a source side.
摘要翻译：要解决的问题：增加对浪涌电压的容限，同时保持栅极的低寄生电容并保持高速开关性能。解决方案：当关断驱动信号使FET 5关断时，会产生浪涌电压， FET 5的源电压VDS为保护电压Vm1以上。同时，第一电压检测电路6A的检测电压变得高于阈值电压Vth，以使FET 13断开，并且在控制电路9中导通FET 14，而控制电路9又使FET 11断开以使开关电路8 到高阻抗。第二电压检测电路6B的检测电压稍后通过二极管15将FET 5的栅极电压VGS提高到栅极阈值电压以上。然后，FET 5通过放电将放电电压的能量释放到源极侧。

5. 发明专利

JP2008278552A Control method of vertical mosfet in bridge circuit 有权
标题翻译：桥式电路中垂直MOSFET的控制方法
公开(公告)号：JP2008278552A
公开(公告)日：2008-11-13
申请号：JP2007115584
申请日：2007-04-25
申请人： Denso Corp , 株式会社デンソー
发明人： TAKASU HISASHI , INOUE TSUYOSHI , KIMURA TOMONORI , SASAYA TAKUYA
IPC分类号： H02M1/08 , H01L27/04 , H01L29/78
CPC分类号： H03K17/6871 , H03K17/08142 , H03K17/0822 , H03K17/165 , H03K17/284 , H03K17/6877 , H03K17/785 , H03K2217/0036
摘要： PROBLEM TO BE SOLVED: To reduce the diode loss by eliminating the need for a reverse blocking diode, and to reduce the reverse recovery characteristics while suppressing self turn-on.
SOLUTION: At the initial stage of dead time, first off state is brought about by employing the gate signal Vg1 or Vg2 of Hi-MOSFET 2 or Lo-MOSFET 3 on the turn-off side as an output voltage Voff1. Since a large current can be prevented from flowing to an external diode D1, D2, diode loss due to a large current flowing to the external diode D1, D2 can be reduced. When both Hi-MOSFET 2 and Lo-MOSFET 3 are turned on, the gate signal Vg1 or Vg2 of Hi-MOSFET 2 or Lo-MOSFET 3 on the turn-off side is switched to an output voltage Voff2, thus bringing about second off state. Consequently, the reverse recovery characteristics can be improved by feeding a large current to the external diode D1, D2.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：通过消除对反向阻塞二极管的需要来减少二极管损耗，并且在抑制自身接通的同时降低反向恢复特性。解决方案：在死区时间的初始阶段，通过采用关断侧的Hi-MOSFET2或Lo-MOSFET3的栅极信号Vg1或Vg2作为输出电压Voff1来实现第一关断状态。由于可以防止大电流流向外部二极管D1，D2，所以可以减少由于流过外部二极管D1，D2的大电流引起的二极管损耗。当Hi-MOSFET 2和Lo-MOSFET 3都导通时，关断侧的Hi-MOSFET2或Lo-MOSFET3的栅极信号Vg1或Vg2被切换到输出电压Voff2，从而使第二次州。因此，通过向外部二极管D1，D2馈送大电流可以提高反向恢复特性。版权所有（C）2009，JPO＆INPIT

6. 发明专利

JP2004129207A Demodulation method and demodulator 有权
公开(公告)号：JP2004129207A
公开(公告)日：2004-04-22
申请号：JP2003143777
申请日：2003-05-21
申请人： Denso Corp , 株式会社デンソー
发明人： TAKASU HISASHI , TAKAHASHI MITSURU
IPC分类号： H03D3/04 , H04L27/156
CPC分类号： H04L27/1563 , H03D3/04
摘要： PROBLEM TO BE SOLVED: To provide a demodulation method and a demodulator which does not require an analog circuit so that a structure of a FSK receiver can be simplified. SOLUTION: Four counters C1 to C4 forming a count section 12 count the numbers of waves of a modulated signal at every expiration of a bit time width T at individual timings, which differ by T/4 from each other. Based on the count values, a first average value AV0 of the count values larger than a decision threshold (="9" in the figure), and a second average value AV1 of the count values smaller than the decision threshold are calculated, and a difference of the average values is designated as a determination value DAV (DAV=AV0-AV1). The counter Ci with the largest determination value DAV is specified as a counter operating at a synchronous timing with bit borders of the digital signal to be demodulated. The count values from the specified counter Ci are compared to the decision threshold to determine the signal level, and the digital signal is thereby restored. COPYRIGHT: (C)2004,JPO

7. 发明专利

JP2013047660A Current detector 有权
标题翻译：电流检测器
公开(公告)号：JP2013047660A
公开(公告)日：2013-03-07
申请号：JP2012029421
申请日：2012-02-14
申请人： Nippon Soken Inc , 株式会社日本自動車部品総合研究所 , Denso Corp , 株式会社デンソー
发明人： SUZUKI YOICHIRO , KIMURA TOMONORI , FUKAGAWA YASUHIRO , TAKASU HISASHI
IPC分类号： G01R15/18
CPC分类号： Y02P70/521
摘要： PROBLEM TO BE SOLVED: To reduce decrease in current detection sensitivity while suppressing influences of unnecessary external magnetic field and external electric field.SOLUTION: A current detector 10 includes a coil 12 that is formed in an annular shape and detects current flowing through a conductor that penetrates the coil, and a shield part 13 covering the coil 12. Part of the shield part 13 covering the inner part of the coil 12 is provided with a slit 13a annularly extending along the coil 12 and communicating the coil 12 with the outside.
摘要翻译：要解决的问题：减少电流检测灵敏度的降低，同时抑制不必要的外部磁场和外部电场的影响。电流检测器10包括形成为环状的线圈12，并检测流过穿过线圈的导体的电流以及覆盖线圈12的屏蔽部分13.屏蔽部分13的一部分覆盖线圈12的内部设置有沿着线圈12环状地延伸并使线圈12与外部连通的狭缝13a。版权所有（C）2013，JPO＆INPIT

8. 发明专利

JP2011130571A Controller for power conversion circuit 有权
标题翻译：电源转换电路控制器
公开(公告)号：JP2011130571A
公开(公告)日：2011-06-30
申请号：JP2009286184
申请日：2009-12-17
申请人： Denso Corp , 株式会社デンソー
发明人： TAKASU HISASHI , INOSHITA RYOSUKE
IPC分类号： H02M1/08 , H02M3/28 , H02M7/48
CPC分类号： H02M3/1582 , H02P27/06
摘要： PROBLEM TO BE SOLVED: To solve the problem, wherein when the voltage of a direct-current power supply is converted and outputted by repeating the operation of turning on and off a power switching element Si to increase or decrease the absolute value of current passing through a coil, when a period for which the power switching element is to be turned on is short, on-time controllability is degraded. SOLUTION: The voltage of a capacitor 58 is applied to the gate of the power switching element Si. Prior to the power switching element Si being turned on at this time, the maximum value of current passing during the on-operation period is estimated, and the voltage of the capacitor 58 is varied and set, according to whether the estimated value is equal to or higher than the threshold. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：解决问题的方案为了解决这样的问题，当通过重复打开和关闭功率开关元件Si的操作来转换和输出直流电源的电压时，增加或减少直流电源的绝对值通过线圈的电流，当功率开关元件要接通的周期短时，导通时间可控性降低。解决方案：将电容器58的电压施加到功率开关元件Si的栅极。在此时电源开关元件Si导通之前，估计接通运行期间的电流通过的最大值，并根据估计值是否等于电容器58的电压进行变化和设定或高于阈值。版权所有（C）2011，JPO＆INPIT

9. 发明专利

JP2014050179A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2014050179A
公开(公告)日：2014-03-17
申请号：JP2012190065
申请日：2012-08-30
申请人： Denso Corp , 株式会社デンソー
发明人： TAKASU HISASHI , KOBAYASHI ATSUSHI
IPC分类号： H02M1/00 , H02M1/08 , H03K17/16
摘要： PROBLEM TO BE SOLVED: To increase tolerance dose against a surge voltage while maintaining high speed switching performance while suppressing the parasitic capacity of a gate.SOLUTION: When an FET5 is turned off in accordance with an OFF driving signal, a surge voltage is generated, and an inter-drain/source voltage VDS of the FET5 is turned into a voltage Vm1 or more. In this case, a detection voltage by a voltage detection circuit 6 is turned to be higher than a threshold voltage Vth, and an FET 13 of a control circuit 9 is turned off, and the FET 14 is turned on, and a gate voltage VGS of the FET11 is turned to be approximately 0 V. Thus, the FET 11 is turned off, and a switch circuit 8 is turned into a high impedance. As a result, the gate of the FET 5 is turned into an open state, and the FET 5 is self-turned on such that the energy of the surge voltage is released to the source side.
摘要翻译：要解决的问题：在抑制栅极的寄生电容的同时保持高速开关性能同时增加浪涌电压的容许量。解决方案：当FET5根据OFF驱动信号关断时，产生浪涌电压，并且FET5的漏极/源极电压VDS变为电压Vm1以上。在这种情况下，通过电压检测电路6的检测电压变为高于阈值电压Vth，控制电路9的FET13截止，FET14导通，栅极电压VGS 使FET11变为约0V。因此，FET11截止，开关电路8变成高阻抗。结果，FET 5的栅极变为断开状态，并且FET 5自身导通，使得浪涌电压的能量被释放到源极侧。

10. 发明专利

JP2013207553A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2013207553A
公开(公告)日：2013-10-07
申请号：JP2012074438
申请日：2012-03-28
申请人： Denso Corp , 株式会社デンソー
发明人： TAKASU HISASHI , KIMURA TOMONORI , HOSHI SHINICHI
IPC分类号： H03K17/08 , H01L21/822 , H01L27/04 , H01L27/06
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of achieving a structure which can effectively protect a semiconductor switch element from surge voltage, while suppressing a reduction of a switching rate.SOLUTION: A semiconductor device 1 comprises: a voltage setting circuit 5 in which a first voltage setting circuit ZD1 and a second voltage setting circuit ZD2 are connected in series, formed between a drain terminal and a source terminal of a switch element SW1; and a first rectifier D1 in which its input terminal is connected to a connection part 6 side in the voltage setting circuit 5 and its output terminal is connected to a gate terminal side. A voltage applied to the gate terminal via the first rectifier D1, is less than a threshold value in normal time when an electric potential difference between the drain and the source is equal to or less than a predetermined value, and the voltage applied to the gate terminal via the first rectifier D1, increases so as to exceed the threshold value, and thereby the switch element SW1 turns ON to flow the current between the drain and the source in abnormal time when the electric potential difference between the drain and the source is more than the predetermined value.
摘要翻译：要解决的问题：提供能够实现能够有效地保护半导体开关元件免受浪涌电压的结构的半导体器件，同时抑制开关速率的降低。解决方案：半导体器件1包括：电压设定电路5，第一电压设定电路ZD1和第二电压设定电路ZD2串联连接，形成在开关元件SW1的漏极端子和源极端子之间; 以及第一整流器D1，其输入端子连接到电压设定电路5中的连接部分6侧，并且其输出端子连接到栅极端子侧。通过第一整流器D1施加到栅极端子的电压在漏极和源极之间的电位差等于或小于预定值的正常时间内小于阈值，并且施加到栅极的电压通过第一整流器D1的端子增加以超过阈值，从而当漏极和源极之间的电位差更多时，开关元件SW1导通以在异常时间内在漏极和源极之间流过电流超过预定值。

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