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1. 发明专利

JP2005269023A Ladder resistor type d/a conversion circuit 有权
标题翻译：梯形电阻型D / A转换电路
公开(公告)号：JP2005269023A
公开(公告)日：2005-09-29
申请号：JP2004076177
申请日：2004-03-17
申请人： Denso Corp , 株式会社デンソー
发明人： OKUMURA NAOO
IPC分类号： H03M1/76
摘要： PROBLEM TO BE SOLVED: To provide a ladder resistor type D/A conversion circuit whereby the cost can be reduced by decreasing the number of buffers in use while decreasing the number of resistors in use and a D/A conversion output with high accuracy can be obtained.
SOLUTION: A control circuit 23 applies switch control to analog switches 16, 18, 19, 21, 22 to form series connection of first and second ladder resistors 2, 3 thereby causing a state that a voltage V2 is applied between both end terminals of the ladder resistors 2, 3 in the series connection, and provides an output of a D/A conversion signal from an output terminal OUT 2 through a first buffer 14 or a second buffer 15 on the basis of a 4-bit digital signal. Further, the control circuit 23 applies switching control to the analog switches 16, 18, 19 so as to separate the first and second ladder resistors 2, 3 from each other and provides an output of 3-bit D/A conversion signals from output terminals OUT 1, OUT 2 through the first and second buffers 14, 15.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种梯形电阻器D / A转换电路，通过减少使用中的缓冲器数量，同时减少使用中的电阻器的数量和具有高的D / A转换输出，可以降低成本可以获得准确度。解决方案：控制电路23向模拟开关16,18,19,21,22施加开关控制，以形成第一和第二梯形电阻器2,3的串联连接，从而导致在两端之间施加电压V2的状态串联连接中的梯形电阻器2,3的端子，并且基于4位数字信号，通过第一缓冲器14或第二缓冲器15提供来自输出端子OUT 2的D / A转换信号的输出。此外，控制电路23对模拟开关16,18,19施加切换控制，以将第一和第二梯形电阻器2,3彼此分离，并且从输出端子提供3位D / A转换信号的输出 OUT 1，OUT 2通过第一和第二缓冲器14,15。（C）版权所有（C）2005，JPO＆NCIPI

2. 发明专利

JP2001308705A DIGITAL TO ANALOG CONVERTER AND ITS CONVERSION ERROR REDUCTION METHOD 失效
公开(公告)号：JP2001308705A
公开(公告)日：2001-11-02
申请号：JP2000126002
申请日：2000-04-26
申请人： DENSO CORP
发明人： OKUMURA NAOO
IPC分类号： H03M1/10 , H03M1/66
摘要： PROBLEM TO BE SOLVED: To reduce a conversion error and to enhance yield. SOLUTION: An adding and subtracting circuit 4 subtracts and adds external digital data S1 held in an input register 2 and conversion error correction data S2 stored in a flash memory 3, and obtains correction digital data S3. A D/A converter circuit 6 performs D/A conversion of the correction digital data S3, and outputs analog voltage Vo. In an inspection process, an inspecting device 8 obtains conversion error voltage ΔV from ideal voltage Vr and output voltage Vo to the external digital data S1 and digitizes it by an A/D converter 12. A correction value setting circuit 13 sets the conversion error correction data S2 that the conversion error of a D/A converter 1 reduces based on conversion error data S4. A write-in circuit 14 writes the conversion error correction data S2 in the flash memory 3.

3. 发明专利

JP2010011012A Comparator with clamping function 审中-公开
标题翻译：具有钳位功能的比较器
公开(公告)号：JP2010011012A
公开(公告)日：2010-01-14
申请号：JP2008167223
申请日：2008-06-26
申请人： Denso Corp , 株式会社デンソー
发明人： OKUMURA NAOO , ISOMURA HIROBUMI
IPC分类号： H03K5/08 , H03G11/00 , H03K5/007
摘要： PROBLEM TO BE SOLVED: To set a fixed and arbitrary clamp voltage without requiring an additional manufacturing process. SOLUTION: When a voltage of a signal input line 6 is lower than a reference voltage VH, a signal Sc is set at an L level, a switch circuit 16 is turned off, and a switch circuit 17 is turned on, thereby turning off FETs 14, 15. When the voltage of the signal input line 6 exceeds the reference voltage VH, the signal Sc is set at an H level, the switch circuit 16 is turned on, and the switch circuit 17 is turned off, thereby making a clamp circuit 4 operable. When the input voltage is further increased and exceeds a clamp voltage VCL, a FET 13 is turned on so as to allow a current to flow into the FETs 13, 14 via a resistor 11, a terminal 1a, and a resistor 12 while the current is made to flow into the FET 15 in accordance with the current flow, thereby allowing the clamping operation. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：设置固定和任意的钳位电压，而不需要额外的制造工艺。解决方案：当信号输入线6的电压低于参考电压VH时，信号Sc被设置为L电平，开关电路16断开，开关电路17接通，从而关闭FET 14,15。当信号输入线6的电压超过基准电压VH时，信号Sc被设定为H电平，开关电路16导通，开关电路17断开使钳位电路4可操作。当输入电压进一步增加并超过钳位电压VCL时，FET 13导通，以便电流通过电阻器11，端子1a和电阻器12流入FET 13,14，而电流根据电流流入FET 15，从而允许夹紧操作。版权所有（C）2010，JPO＆INPIT

4. 发明专利

JP2004247826A Level shift circuit 有权
公开(公告)号：JP2004247826A
公开(公告)日：2004-09-02
申请号：JP2003033590
申请日：2003-02-12
申请人： Denso Corp , 株式会社デンソー
发明人： OKUMURA NAOO , HARADA TAKUYA , HORIE MASUMI
IPC分类号： H01L21/8238 , H01L27/092 , H03K19/0185
摘要： PROBLEM TO BE SOLVED: To provide a level shift circuit capable of outputting a voltage shifted from an input voltage as much as the shift voltage even when the received input voltage is negative.
SOLUTION: An operational amplifier 20 outputs a voltage the same as the input voltage to the drain of a transistor 10. The transistor 10 is configured to be a so-called source follower circuit wherein a constant current is supplied to the source of the transistor 10 and the same potential level is applied to the gate and the drain, and the transistor 10 outputs the source potential level as the output voltage. The source of the transistor 10 outputs a voltage whose level is shifted from the input voltage to the gate by the shift voltage. The operational amplifier 20 is configured such that a negative power supply of the operational amplifier 20 is fixed to a negative voltage and the output terminal of the operational amplifier 20 outputs a voltage the same as the input voltage even when the input voltage is negative. Thus, even when the input voltage is negative, the source of the transistor 10 outputs a voltage shifted from the input voltage by the shift voltage.
COPYRIGHT: (C)2004,JPO&NCIPI

5. 发明专利

JP2003273672A Differential amplifier circuit 有权
标题翻译：差分放大器电路
公开(公告)号：JP2003273672A
公开(公告)日：2003-09-26
申请号：JP2002070135
申请日：2002-03-14
申请人： Denso Corp , 株式会社デンソー
发明人： OKUMURA NAOO , HORIE MASUMI
IPC分类号： H03F3/45
摘要： PROBLEM TO BE SOLVED: To provide a differential amplifier circuit which is normally operated even when a power supply voltage and the voltage of a differential input are low voltages.
SOLUTION: The differential amplifier circuit is composed of P channel type transistors 1 and 2 of constant current sources, P channel type transistors 3 and 4 in which gates are applied with voltages Vin- and Vin+ of differential inputs, and an N channel type transistor 7 of an output stage. In such a case, low voltage resistance transistors are used as N channel type transistors 5-7. Besides, N channel type transistors 8 and 9 are provided for relaxing the voltages with which the N channel type transistors 5-7 are applied.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供即使当电源电压和差分输入的电压是低电压时也正常工作的差分放大器电路。解决方案：差分放大器电路由恒流源的P沟道型晶体管1和2，P沟道型晶体管3和4组成，其中门施加有差分输入的电压Vin-和Vin +，以及N沟道型晶体管7。在这种情况下，低电压电阻晶体管被用作N沟道晶体管5-7。此外，提供N沟道型晶体管8和9用于放宽施加N沟道型晶体管5-7的电压。版权所有（C）2003，JPO

6. 发明专利

JP2000347762A MICROCOMPUTER 失效
公开(公告)号：JP2000347762A
公开(公告)日：2000-12-15
申请号：JP15943499
申请日：1999-06-07
申请人： DENSO CORP
发明人： SANTSUKO TOSHIYUKI , NODA SHINICHI , MAEDA KOICHI , OKUMURA NAOO
IPC分类号： G06F1/04
摘要： PROBLEM TO BE SOLVED: To make low power consumption while continuing the operation of a specific peripheral circuit when a low power consumption mode is set. SOLUTION: A CPU 4 and peripheral circuits 5 and 6 constituting a microcomputer 1 operate on the basis of a system clock outputted from a 1st oscillation circuit 2. When a low power consumption mode is set to the microcomputer 1 here, the output of the system clock from the circuit 2 is stopped to stop them. On the other hand, since a selector 7 gives a sleep clock (having a lower frequency than the system clock) outputted from a 2nd oscillation circuit 3 to the 2nd circuit 6 that has to operate even in the low power consumption mode, the circuit 6 is made to operate at a low speed so that low power consumption can be made.

7. 发明专利

JP2008166628A Protective circuit of semiconductor device 审中-公开
标题翻译：半导体器件保护电路
公开(公告)号：JP2008166628A
公开(公告)日：2008-07-17
申请号：JP2006356825
申请日：2006-12-29
申请人： Denso Corp , 株式会社デンソー
发明人： OKUMURA NAOO
IPC分类号： H01L21/822 , H01L21/60 , H01L21/8238 , H01L27/04 , H01L27/06 , H01L27/092
CPC分类号： H01L24/06 , H01L2224/05553 , H01L2224/48091 , H01L2224/49 , H01L2224/49113 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01033 , H01L2924/01082 , H01L2924/1305 , H01L2924/13091 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a protective circuit of a semiconductor device capable of miniaturizing the semiconductor device and improving electrostatic discharge resistance compatibly. SOLUTION: In the protective circuit 23, since a Pch protective circuit 21 and an Nch protective circuit 22 are formed by individually forming a Pch protective diode 14 at the lower part of a bonding pad 16 for Pch protection and an Nch protective diode 15 at the lower part of a bonding pad 17 for Nch protection, a non-operating protective circuit is not formed at the lower part of the respective bonding pads. Thus, an area occupied by the protective circuit 23 is reduced to contribute to the miniaturization of the semiconductor device 10. Since an area at the lower part of the respective bonding pads is effectively utilized, the formation area of the Pch protective diode 14 and the Nch protective diode 15 can be increased and thus the electrostatic discharge resistance can be improved. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供能够使半导体器件小型化并且兼容地提高静电放电电阻的半导体器件的保护电路。解决方案：在保护电路23中，由于Pch保护电路21和Nch保护电路22是通过在用于Pch保护的焊盘16的下部分别形成Pch保护二极管14和Nch保护二极管 15在用于Nch保护的接合焊盘17的下部，在各个接合焊盘的下部不形成不工作的保护电路。因此，保护电路23占有的面积减小，有助于半导体器件10的小型化。由于有效地利用了各个焊盘的下部的区域，所以Pch保护二极管14的形成区域和 Nch保护二极管15可以增加，因此可以提高静电放电电阻。版权所有（C）2008，JPO＆INPIT

8. 发明专利

JP2007288609A A/d converter 审中-公开
标题翻译： A / D转换器
公开(公告)号：JP2007288609A
公开(公告)日：2007-11-01
申请号：JP2006114764
申请日：2006-04-18
申请人： Denso Corp , 株式会社デンソー
发明人： OKUMURA NAOO
IPC分类号： H03M1/12 , H03F3/45
摘要： PROBLEM TO BE SOLVED: To provide an A/D converter by which current consumption is reduced in sample-and-hold processing performed by one of two A/D conversion parts while performing A/D conversion processing by the other.
SOLUTION: Operation amplifiers 2d, 3d of A/D conversion circuits 2, 3 are provided with adjustment parts which adjust current for charging and discharging hold voltages VSH1, VSH2 to capacitors 2e, 3e and the charged and discharged current is adjusted so that the maximum value of sample-and-hold processing time approximately matches to performance time of A/D conversion processing by the adjustment parts.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种A / D转换器，在通过另一个进行A / D转换处理时，由两个A / D转换部分中的一个进行的采样和保持处理中的电流消耗减少。解决方案：A / D转换电路2,3的运算放大器2d，3d设有调节部分，调节电流用于将保持电压VSH1，VSH2充电和放电到电容器2e，3e，并且调节充电和放电电流采样保持处理时间的最大值大约与调整部分的A / D转换处理的性能时间相匹配。版权所有（C）2008，JPO＆INPIT

9. 发明专利

JP2006216205A Sample and hold circuit 审中-公开
标题翻译：示例和保持电路
公开(公告)号：JP2006216205A
公开(公告)日：2006-08-17
申请号：JP2005030839
申请日：2005-02-07
申请人： Denso Corp , 株式会社デンソー
发明人： OKUMURA NAOO , HARADA TAKUYA
IPC分类号： G11C27/02 , H03K17/00 , H03K17/687 , H03M1/12
摘要： PROBLEM TO BE SOLVED: To provide a highly accurate sample and hold circuit, capable of preventing generation of wrong voltage due to the clock field-through of the switching operation of a switch. SOLUTION: During a sampling period, a switching S1 and a switching circuit S4 are turned ON, while a switch S3 is turned OFF. During switching period, the switching circuit S4 is first switched to OFF state, the switch S1 is switched to OFF state, and then the switch S3 is switched to ON state. Transistors Q1 and Q2 are equal in size, and gate/drain capacitances Cn and Cp are equal. Thus, by properly setting the bias voltage TPH, when the switches S4a and S4b are switched to OFF states, charges Qn and Qp stored in the gate/drain capacitances Cn and Cp offset each other by clock field-through, so as not to be stored in a capacitor C1. During holding period, the switch S1 and the switch circuit S4 are switched to OFF states, and the switch S3 is switched to ON state. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种高精度的采样和保持电路，能够防止由于开关的开关操作的时钟导通而产生错误的电压。解决方案：在采样期间，开关S1和开关电路S4导通，而开关S3断开。在切换期间，切换电路S4首先切换为OFF状态，将开关S1切换到OFF状态，然后将开关S3切换到ON状态。晶体管Q1和Q2的尺寸相等，栅/漏电容Cn和Cp相等。因此，通过适当地设定偏置电压TPH，当开关S4a和S4b切换到截止状态时，存储在栅极/漏极电容Cn和Cp中的电荷Qn和Qp通过时钟输入彼此偏移，从而不会存储在电容器C1中。在保持期间，开关S1和开关电路S4切换到断开状态，开关S3切换到接通状态。版权所有（C）2006，JPO＆NCIPI

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