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1. 发明专利

JP2013012590A Silicon carbide semiconductor device 有权
标题翻译：硅碳化硅半导体器件
公开(公告)号：JP2013012590A
公开(公告)日：2013-01-17
申请号：JP2011144320
申请日：2011-06-29
申请人： Denso Corp , 株式会社デンソー , Toyota Motor Corp , トヨタ自動車株式会社 , Toyota Central R&D Labs Inc , 株式会社豊田中央研究所
发明人： MIYAHARA SHINICHIRO , TAKATANI HIDESHI , SUGIMOTO MASAHIRO , WATANABE YUKIHIKO , SOEJIMA SHIGEMASA , ISHIKAWA TAKESHI
IPC分类号： H01L29/78 , H01L21/336 , H01L29/12
CPC分类号： H01L29/7813 , H01L29/045 , H01L29/0865 , H01L29/1095 , H01L29/1608 , H01L29/4236 , H01L29/66068 , H01L29/7825 , H01L29/7827
摘要： PROBLEM TO BE SOLVED: To obtain a high channel mobility by bringing the side surface of a trench, in which a channel is formed, close to the (11-20) plane or the (1-100) plane capable of increasing the channel mobility.SOLUTION: An nsource region 5 is formed so as to come into contact with one side surface out of both side surfaces of a trench 7, i.e. the side surface which forms an angle of 90° or an angle close to it with respect to the (0001) plane, so that a channel is formed in only one of both side surfaces of the trench 7. Since the channel can be formed only in the side surface where a high channel mobility is formed out of both side surfaces of the trench 7, a high channel mobility can be obtained.
摘要翻译：要解决的问题：为了通过使形成沟道的沟槽的侧表面靠近能够增加的（11-20）面或（1-100）面来获得高沟道迁移率渠道流动性。源极区域5形成为与沟槽7的两个侧表面中的一个侧表面接触，即侧表面相对于（0001）面形成90°的角度或与其接近的角度，使得沟槽仅形成在沟槽7的两个侧表面中的一个中。由于沟道仅可以形成在侧表面其中在沟槽7的两个侧表面形成高沟道迁移率，可以获得高沟道迁移率。版权所有（C）2013，JPO＆INPIT

2. 发明专利

JP2012169384A Silicon carbide semiconductor device and method of manufacturing the same 审中-公开
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：JP2012169384A
公开(公告)日：2012-09-06
申请号：JP2011027995
申请日：2011-02-11
申请人： Denso Corp , Toyota Motor Corp , Toyota Central R&D Labs Inc , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： YAMAMOTO KENSAKU , NOBORIO MASATO , MATSUKI HIDEO , TAKATANI HIDESHI , SUGIMOTO MASAHIRO , MORIMOTO JUN , SOEJIMA SHIGEMASA , ISHIKAWA TAKESHI , WATANABE YUKIHIKO
IPC分类号： H01L29/78 , H01L21/336 , H01L29/12 , H01L29/739
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/66068 , H01L29/66348 , H01L29/7397
摘要： PROBLEM TO BE SOLVED: To reduce the on-resistance when a deep layer is formed so as to intersect a trench configuring a trench gate structure.SOLUTION: A p-type deep layer 10 has structure where the upper part is narrower than the lower part. For example, the p-type deep layer 10 is constituted by a lower layer region 10a and an upper layer region 10b, and the upper layer region 10b is made narrower than the lower layer region 10a. Consequently, when a channel is formed by applying a gate voltage to a gate electrode 9 during on time on the upper periphery of the p-type deep layer 10, the channel width can be widened. When compared with a case where the width of the p-type deep layer 10 is fixed entirely, i.e. fixed to the same width as that of the lower layer region 10a, a JFET region can be widened and the JFET resistance can be reduced. The on-resistance can thereby be reduced.
摘要翻译：要解决的问题：当形成深层以与构成沟槽栅极结构的沟槽交叉时，降低导通电阻。解决方案：p型深层10具有其上部比下部更窄的结构。例如，p型深层10由下层区域10a和上层区域10b构成，上层区域10b比下层区域10a窄。因此，当在p型深层10的上部周边上的栅极电极9上施加栅极电压而形成沟道时，可以扩大通道宽度。当与p型深层10的宽度完全固定即固定为与下层区域10a的宽度相同的宽度的情况相比，可以加宽JFET区域并且可以减小JFET电阻。因此可以降低导通电阻。版权所有（C）2012，JPO＆INPIT

3. 发明专利

JP2012116732A Method of manufacturing silicon carbide single crystal 有权
标题翻译：制造单晶碳化硅的方法
公开(公告)号：JP2012116732A
公开(公告)日：2012-06-21
申请号：JP2010270295
申请日：2010-12-03
申请人： Denso Corp , Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： WATANABE HIROKI , KITO YASUO , FURUKAWA TAIJI , YAMAMOTO KENSAKU , TAKATANI HIDESHI , SUGIMOTO MASAHIRO , WATANABE YUKIHIKO , SOEJIMA SHIGEMASA , ISHIKAWA TAKESHI
IPC分类号： C30B29/36 , C30B25/20 , H01L21/205
CPC分类号： H01L21/0262 , C30B25/186 , C30B29/36 , H01L21/02378 , H01L21/0243 , H01L21/02529 , H01L21/02658 , H01L21/046 , H01L21/0475 , H01L29/04
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing an SiC single crystal capable of reducing threading dislocations while suppressing transfer of polymorphism and dislocation without performing sequential lamination of p-layers and n-layers.SOLUTION: A very deep etch pit 1b is formed in the position corresponding to a leak portion by performing molten KOH etching and the like after Al ion implantation and activation annealing, based on findings that a dislocation causing leak such as a drain leak of a vertical MOSFET is a threading screw dislocation. When an SiC growth layer 4 is epitaxially grown on the surface of the etch pit 1b in such a condition that portions grown in the side wall parts of the etch pit 1b are brought into contact mutually, the dislocation is prevented from being transferred to the SiC growth layer 4. In this way, the SiC growth layer 4 having the surface including no threading screw dislocation 1a can be obtained. Therefore, without performing sequential lamination of p-layers and n-layers, the SiC single crystal capable of reducing threading screw dislocations can be produced while suppressing transfer of polymorphism and dislocation.
摘要翻译：要解决的问题：提供一种能够在不进行p层和n层的顺序层压的同时抑制多晶型转移和位错的同时能够减少穿透位错的SiC单晶的制造方法。解决方案：通过在Al离子注入和活化退火之后进行熔融KOH蚀刻等形成在与泄漏部分相对应的位置中的非常深的蚀刻坑1b，基于发现泄漏如泄漏泄漏的位错的垂直MOSFET是螺纹螺钉错位。当在蚀刻凹坑1b的表面上外延生长SiC生长层4，使得在蚀刻坑1b的侧壁部分中生长的部分相互接触的情况下，防止位错转移到SiC 以这种方式，可以获得具有不包括螺纹螺纹位错1a的表面的SiC生长层4。因此，在不进行p层和n层的顺序层叠的情况下，能够抑制多晶型和位错的转移而能够减少螺纹位错的SiC单晶。版权所有（C）2012，JPO＆INPIT

4. 发明专利

JP2012079945A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2012079945A
公开(公告)日：2012-04-19
申请号：JP2010224226
申请日：2010-10-01
申请人： Denso Corp , Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： KONISHI MASAKI , FUJIWARA HIROKAZU , MORIMOTO ATSUSHI , ENDO TAKESHI , MORINO TOMOO , ISHIKAWA TAKESHI , KATSUNO TAKASHI , WATANABE YUKIHIKO
IPC分类号： H01L27/04 , H01L21/336 , H01L29/12 , H01L29/739 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a technique capable of reducing losses of a diode without forming a step on a surface of a semiconductor layer between a transistor and the diode.SOLUTION: A semiconductor device 10 includes a semiconductor layer 12 composed of SiC. The semiconductor layer 12 includes a transistor region 20 in which an insulating gate type transistor is formed and a diode region 40 in which a diode is formed. In the transistor region 20, a first region 22, a second region 24, a third region 26, and a fourth region 28 are formed. In the diode region 40, a low concentration region 42 and a high concentration region 44 are formed. The thickness of the low concentration region 42 is thinner than the thickness of the second region 24 plus the third region 26. The thickness of the high concentration region 44 is thicker than that of the fourth region 28.
摘要翻译：要解决的问题：提供能够减小二极管损耗而不在晶体管和二极管之间的半导体层的表面上形成台阶的技术。解决方案：半导体器件10包括由SiC构成的半导体层12。半导体层12包括其中形成绝缘栅型晶体管的晶体管区域20和形成二极管的二极管区域40。在晶体管区域20中，形成第一区域22，第二区域24，第三区域26和第四区域28。在二极管区域40中，形成低浓度区域42和高浓度区域44。低浓度区域42的厚度比第二区域24加第三区域26的厚度薄。高浓度区域44的厚度比第四区域28的厚度厚。（C） 2012年，JPO＆INPIT

5. 发明专利

JP2012069797A Insulated gate transistor 审中-公开
标题翻译：绝缘栅晶体管
公开(公告)号：JP2012069797A
公开(公告)日：2012-04-05
申请号：JP2010214240
申请日：2010-09-24
申请人： Denso Corp , Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： SUGIMOTO MASAHIRO , ISHIKAWA TAKESHI , SOEJIMA SHIGEMASA , WATANABE YUKIHIKO , SUZUKI MASAHIRO , MATSUKI HIDEO
IPC分类号： H01L29/78 , H01L29/739
摘要： PROBLEM TO BE SOLVED: To provide an insulated gate transistor, having a trench gate electrode with a high breakdown voltage characteristic, hardly producing a manufacturing error in the breakdown voltage characteristic.SOLUTION: The insulated gate transistor includes: a first region of first conductive type, formed in the range facing the upper surface of a semiconductor layer and connected to a first electrode; a second region of second conductive type, formed on the lower side of the first region; a third region of first conductive type formed on the lower side of the second region; a pair of fourth regions of second conductive type, connected to the first electrode; and a trench gate electrode. Each of the pair of fourth regions is formed on each side of a trench to sandwich the center of the trench. Each of the fourth regions has a vertical region extending to a position deeper than the lower end of an insulating film in the third region, and a horizontal region extending to the center side of the trench from the vertical region in the third region, in the position deeper than the lower end of the insulating film.
摘要翻译：解决的问题：为了提供具有高击穿电压特性的沟槽栅电极的绝缘栅晶体管，几乎不产生击穿电压特性的制造误差。解决方案：绝缘栅晶体管包括：第一导电类型的第一区域，形成在面向半导体层的上表面并连接到第一电极的范围内; 第二导电类型的第二区域，形成在第一区域的下侧; 形成在所述第二区域的下侧的第一导电类型的第三区域; 连接到第一电极的一对第二导电类型的第四区域; 和沟槽栅电极。一对第四区域中的每一个形成在沟槽的每一侧以夹住沟槽的中心。每个第四区域具有延伸到比第三区域中的绝缘膜的下端更深的位置的垂直区域，以及从第三区域中的垂直区域延伸到沟槽的中心侧的水平区域，在位置比绝缘膜的下端深。版权所有（C）2012，JPO＆INPIT

6. 发明专利

JP2012004312A Method of manufacturing silicon carbide semiconductor device and silicon carbide semiconductor device 有权
标题翻译：制造碳化硅半导体器件和硅碳化硅半导体器件的方法
公开(公告)号：JP2012004312A
公开(公告)日：2012-01-05
申请号：JP2010137539
申请日：2010-06-16
申请人： Denso Corp , Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： MATSUKI HIDEO , SUGIMOTO MASAHIRO , TAKATANI HIDESHI , MORIMOTO ATSUSHI , SOEJIMA SHIGEMASA , ISHIKAWA TAKESHI , WATANABE YUKIHIKO
IPC分类号： H01L29/06 , H01L21/336 , H01L29/12 , H01L29/739 , H01L29/78
CPC分类号： H01L29/7813 , H01L29/0615 , H01L29/0619 , H01L29/0638 , H01L29/0661 , H01L29/1608 , H01L29/66068 , H01L29/7811
摘要： PROBLEM TO BE SOLVED: To simplify a manufacturing process by simplifying a step for forming a RESURF layer or an impurity layer constituting an EQR structure.SOLUTION: The surface layer of an n-type drift layer located below a recess 20 in a p-type RESURF layer 21 is connected, by migration of SiC, to a part formed on the surface layer of a p-type base region 3 in the p-type RESURF layer 21. Consequently, the p-type RESURF layer 21 can be connected to the p-type base region 3 without requiring oblique ion implantation even if the side wall of the recess 20 is steep. Since the step for forming the p-type RESURF layer 21 can be simplified, the manufacturing process can be simplified.
摘要翻译：解决的问题：为了简化制造工序，简化形成构成EQR结构的RESURF层或杂质层的工序。解决方案：通过SiC的迁移将位于p型RESURF层21中的凹部20下方的n

7. 发明专利

JP2011181553A Method for processing semiconductor wafer, and processed semiconductor wafer 有权
标题翻译：加工半导体波形的方法和加工半导体波形
公开(公告)号：JP2011181553A
公开(公告)日：2011-09-15
申请号：JP2010041648
申请日：2010-02-26
申请人： Denso Corp , Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： ISHIKAWA TAKESHI , WATANABE YUKIHIKO , KATSUNO TAKASHI , YAMAMOTO TAKEO , ENDO TAKESHI , FUJIWARA HIROKAZU , KONISHI MASAKI
IPC分类号： H01L29/47 , H01L29/872
CPC分类号： H01L29/872
摘要： PROBLEM TO BE SOLVED: To provide a processing technology capable of efficiently reducing the effect of heterogeneity by processing a semiconductor wafer in which the heterogeneity exists.
SOLUTION: In a method for processing a semiconductor wafer, a surface of the semiconductor wafer is divided into a plurality of sections, and an average density of a characteristics deterioration factor is specified for every divided section (S12). One kind of mask pattern is selected among plural kinds of mask patterns prepared preliminarily based on the average density in the section for every divided section (S15). The plural kinds of mask patterns include a plurality of openings, and comply with such restrictions that the openings are uniformly distributed and an opening ratio of each opening differs dependent on each of the kinds. A mask pattern of a kind having a higher opening ratio is selected as the average density is higher. A dissimilar material is injected through an opening of the mask pattern selected for every divided section (S21).
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供能够通过处理存在异质性的半导体晶片来有效地降低异质性的影响的处理技术。解决方案：在半导体晶片的处理方法中，半导体晶片的表面被划分为多个部分，并且对于每个分割部分规定了特性劣化因子的平均密度（S12）。在基于每个划分的部分的平均密度预先准备的多种掩模图案中选择一种掩模图案（S15）。多种掩模图案包括多个开口，并且符合这样的限制，即开口均匀分布，并且每个开口的开口率根据每种开口的不同而不同。选择具有较高开口率的类型的掩模图案，因为平均密度较高。通过针对每个分割区域选择的掩模图案的开口注入不同的材料（S21）。版权所有（C）2011，JPO＆INPIT

8. 发明专利

JP2008130879A Electronic device 有权
标题翻译：电子设备
公开(公告)号：JP2008130879A
公开(公告)日：2008-06-05
申请号：JP2006315321
申请日：2006-11-22
申请人： Denso Corp , 株式会社デンソー
发明人： HANDA NORIMASA , OKUDA RYOICHI , ISHIKAWA TAKESHI
IPC分类号： H01L23/36 , H01L23/34
CPC分类号： H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/73204 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a structure which attains the enhancement of heat radiation by a heat sink and is suitable to be miniaturized, in an electronic device in which a heat-generating element is mounted on one surface of a circuit substrate and heat is radiated from the surface opposed to the surface of circuit substrate of the heat-generating element. SOLUTION: The electronic device includes a case 10 having a first surface 11 and a second surface 12 which are opposed each other, the circuit substrate 20 which is mounted on the first surface 11 of the case 10, the heat-generating elements 30, 31 which are mounted on the upper surface of the circuit substrate 20, and the heat sink 50 which is provided on the upper surfaces of the heat-generating elements 30, 31 and thermally connected with the heat-generating elements 30, 31. The upper surface of the heat sink 50 is thermally connected with the second surface 12 of the case 10, a protrusion 51 protruded toward the circuit substrate 20 is located on the lower surface of the heat sink 50, and a connection portion 21 which thermally connects between the protrusion 51 and the first surface 11 of the case 10 is located on the circuit substrate 20. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种结构，其在发电元件安装在电路基板的一个表面上的电子设备中提供了通过散热器增强散热并且适于小型化的结构并且从与发热元件的电路基板的表面相对的表面辐射热量。解决方案：电子设备包括具有彼此相对的第一表面11和第二表面12的壳体10，安装在壳体10的第一表面11上的电路基板20，发热元件 30,31，其安装在电路基板20的上表面上，散热器50设置在发热元件30,31的上表面上并与发热元件30,31热连接。散热器50的上表面与壳体10的第二表面12热连接，朝向电路基板20突出的突起51位于散热器50的下表面上，并且连接部21热连接突起51与壳体10的第一表面11之间位于电路基板20上。版权所有（C）2008，JPO＆INPIT

9. 发明专利

JP2006032774A Electronic device 审中-公开
标题翻译：电子设备
公开(公告)号：JP2006032774A
公开(公告)日：2006-02-02
申请号：JP2004211596
申请日：2004-07-20
申请人： Denso Corp , 株式会社デンソー
发明人： SANADA SUKENORI , IMAIZUMI NORIHISA , ISHIKAWA TAKESHI
IPC分类号： H01L23/50 , H01L25/00
CPC分类号： H01L2224/48091 , H01L2224/48247 , H01L2224/49109 , H01L2224/73265 , H01L2924/19105 , H01L2924/19107 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To suitably prevent molding resin from peeling in an electronic device which has an electronic component mounted on a lead frame with a conductive adhesive, and in which the lead frame and electronic component are sealed with the molding resin. SOLUTION: The electronic device which has the electronic component 40 mounted on the lead frame 10 with the conductive adhesive 20, and in which the lead frame 10 and electronic component 40 are sealed with the molding resin 60 has a groove 15 as a recessed part in an outer periphery of the portion of the lead frame 10 where the electronic component 40 is arranged. The groove 15 is disposed at a distance less than twice as long as the height L of the electronic component 40. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了适当地防止在具有通过导电粘合剂安装在引线框架上的电子部件的电子设备中剥离树脂，并且其中引线框架和电子部件用模制树脂密封。解决方案：使用导电粘合剂20安装在引线框架10上并且其中引线框架10和电子部件40用模制树脂60密封的电子部件40的电子设备具有凹槽15作为凹陷部分在引线框架10的布置有电子部件40的部分的外周中。凹槽15的设置距离小于电子部件40的高度L的两倍。（C）2006，JPO＆NCIPI

10. 发明专利

JP2002373961A Resin sealed electronic device 审中-公开
标题翻译：树脂密封电子设备
公开(公告)号：JP2002373961A
公开(公告)日：2002-12-26
申请号：JP2001182034
申请日：2001-06-15
申请人： Denso Corp , 株式会社デンソー
发明人： ISHIKAWA TAKESHI , NAGASAKA TAKASHI
IPC分类号： H01L23/29 , H01L23/31 , H01L25/00
CPC分类号： H01L24/73 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/8592 , H01L2924/14 , H01L2924/181 , H01L2924/19105 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To obtain a resin sealed electronic device in which adhesion is enhanced between a circuit board and a sealing resin. SOLUTION: An electronic component, i.e. an IC chip 7, is mounted on one side 6a of a ceramic circuit board 6 and connected electrically to the conductor 2 on the circuit board 6 through a bonding wire 9. The IC chip 7 and the wire 9 are wrapped by a sealing resin 15, e.g. epoxy resin, wherein a polyamide based resin exhibiting better adhesion to the circuit board 6 than the sealing resin 15 is interposed, as an adhesion resin 14, between the circuit board 6 and the sealing resin 15.
摘要翻译：要解决的问题：获得在电路板和密封树脂之间增强粘合性的树脂密封电子器件。解决方案：电子部件即IC芯片7安装在陶瓷电路板6的一侧6a上，并通过接合线9与电路板6上的导体2电连接.IC芯片7和导线9 被密封树脂15包裹，例如环氧树脂，其中在电路板6和密封树脂15之间插入具有比密封树脂15更好地粘附到电路板6的聚酰胺基树脂作为粘合树脂14。

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