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    • 3. 发明专利
    • Specialized processing block for programmable logic device
    • 专用加工块可编程逻辑器件
    • JP2007215192A
    • 2007-08-23
    • JP2007029842
    • 2007-02-08
    • Altera Corpアルテラ コーポレイションAltera Corporation
    • LEE KWAN YEE MARTINLANGHAMMER MARTINLIN YI-WENNGUYEN TRIET M
    • H03K19/173G06F7/38
    • G06F7/49963G06F7/49921G06F7/49947G06F7/5443
    • PROBLEM TO BE SOLVED: To provide improved rounding and saturation capabilities of the DSP block of a PLD. SOLUTION: A specialized processing block for a programmable logic device includes circuitry for performing multiplications and sums thereof, as well as circuitry for rounding the result. The rounding circuitry can selectably perform round-to-nearest and round-to-nearest-even operations. In addition, the bit position at which rounding occurs is preferably selectable. The specialized processing block preferably also includes saturation circuitry to prevent overflows and underflows, and the bit position at which saturation occurs also preferably is selectable. The selectability of both the rounding and saturation positions provides control of the output data word width. The rounding and saturation circuitry may be selectably located in different positions based on timing needs. COPYRIGHT: (C)2007,JPO&INPIT
    • 要解决的问题:提供PLD的DSP块的改进的舍入和饱和能力。 解决方案:用于可编程逻辑器件的专用处理块包括用于执行其乘法和和的电路,以及用于对结果进行舍入的电路。 四舍五入电路可以选择性地执行圆到最近和从最接近平移的操作。 此外,优选地可选择进行舍入的位位置。 专门的处理块优选地还包括用于防止溢出和下溢的饱和电路,并且优选地可选择饱和发生的位位置。 舍入和饱和位置的选择性提供了输出数据字宽度的控制。 舍入和饱和电路可以基于定时需要可选地位于不同的位置。 版权所有(C)2007,JPO&INPIT