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1. 发明专利

JPS6189712A Two-terminal negative resistance circuit 失效
标题翻译：两端负电阻电路
公开(公告)号：JPS6189712A
公开(公告)日：1986-05-07
申请号：JP21209184
申请日：1984-10-08
申请人： Advantest Corp , Nippon Telegr & Teleph Corp
发明人： GOISHI AKIRA , SHIBAYAMA AKINORI
IPC分类号： H03H11/44 , H03H11/52
CPC分类号： H03H11/52
摘要： PURPOSE:To obtain a negative resistance at a large voltage and a current over a wide range by providing an active element whose drain current is de creased with a large source-gate voltage while keeping the drain-gate voltage constant, a transistor (TR) inserted in series between the source and a power terminal and a resistance voltage division circuit. CONSTITUTION:Resistance values R1, R2 of resistors 18, 19 of a resistance volt age division circuit 16 are selected to be a sufficiently large value so as not to give effect on the negative resistance value between two terminals 12 and 13 when a large current flows to the circuit 16. In an electrostatic induction TR SIT11 as the active element, the source-gate voltage VSG is increased when the drain-gate voltage VDG is increased while using a drain current ID as a parameter as shown in curves 21-24, the said VSG-VDG characteristic curve is changed comparatively largely when the drain current ID is changed, and the characteristic changes as the curve 24-21 when the source-gate voltage VSG is increased with the drain-gate voltage VDG kept constant and the drain current ID is decreased. In using the SIT as the active element 11, the negative resistance circuit operated at several 100V is obtained, which is activated over a wide range.
摘要翻译：目的：通过在保持漏极 - 栅极电压保持恒定的同时，通过提供漏极电流在较大的源极栅极电压下降低的有源元件，在大范围的大电压和电流下获得负电阻，晶体管（TR）源极与电源端子和电阻分压电路串联插入。构成：电阻分压电路16的电阻18,19的电阻值R1，R2被选择为足够大的值，以便当大电流流动时不会对两个端子12和13之间的负电阻值产生影响在作为有源元件的静电感应TR SIT11中，当使用漏极电流ID作为参数时，漏极 - 栅极电压VDG增加时，栅极 - 栅极电压VSG增加，如曲线21-24所示，当漏极电流ID改变时，所述VSG-VDG特性曲线变化较大，当栅极电压VDG保持恒定并且漏极 - 栅极电压VDG增加时，特性变化为曲线24-21 当前ID减少。在使用SIT作为有源元件11时，获得在几个100V下操作的负电阻电路，其在宽范围内被激活。

2. 发明专利

JPS58191524A Error detecting system in digital-analog converter 失效
标题翻译：数字模拟转换器中的错误检测系统
公开(公告)号：JPS58191524A
公开(公告)日：1983-11-08
申请号：JP7568782
申请日：1982-05-06
申请人： Advantest Corp , Nippon Telegr & Teleph Corp
发明人： SHIBAYAMA AKINORI , NIIJIMA HIRONOBU
IPC分类号： H03M1/10
CPC分类号： H03M1/10
摘要： PURPOSE:To constitute the detecting circuit system with a small size in high speed, by detecting an error of a current source with the difference between output signals of a D/A converter in response to digital signals different alternately. CONSTITUTION:The digital input signals are applied to terminals D1-D0 with the weight of binary-coding, given to switches J1-Jn, Jn+1-Jn+m via a microcomputer A and a current from current sources I1-In+m switched with the switches is applied to a current-voltage conversion amplifier K. The correction data in response to the input signal is given from a correction circuit 12 and summed at the amplifier K. Further, the detection circuit 12 detects the relative error of the current sources I1In+m of a D/A conversion section 10, converts it into a digital value and gives to the computer A, which calculates the correction data by using the error and stores the data in a memory B of the circuit 12. Thus, an A/D converter Q of a detection section 11 has only to be operated in a narrow range.
摘要翻译：目的：通过响应于交替不同的数字信号，通过检测D / A转换器的输出信号之间的差异来检测电流源的误差，构成高速小尺寸的检测电路系统。构成：通过微型计算机A将数字输入信号施加到具有二进制编码权重的端子D1-D0，给定给开关J1-Jn，Jn + 1-Jn + m，并且来自电流源I1-In + m的电流利用开关切换被施加到电流 - 电压转换放大器K.响应于输入信号的校正数据从校正电路12给出并在放大器K相加。此外，检测电路12检测到 D / A转换部分10的电流源I1In + m将其转换为数字值，并给予计算机A，计算机A通过使用该错误来计算校正数据，并将数据存储在电路12的存储器B中。因此，检测部11的A / D转换器Q只能在窄范围内工作。

3. 发明专利

JPS58181323A Digital-analog converter with calibrating function 失效
标题翻译：具有校准功能的数字模拟转换器
公开(公告)号：JPS58181323A
公开(公告)日：1983-10-24
申请号：JP6416682
申请日：1982-04-16
申请人： Advantest Corp , Nippon Telegr & Teleph Corp
发明人： SHIBAYAMA AKINORI , NIIJIMA HIRONOBU
IPC分类号： H03M1/10 , G05B19/23 , H03M1/00 , H03M1/74
CPC分类号： G05B19/231 , H03M1/1071 , H03M1/745
摘要： PURPOSE: To attain a high linearity, by correcting the linearity automatically by means of a digital technique.
CONSTITUTION: A D/A converter consists of a D/A conversion section 15 receiving a digital signal corrected for error and outputting an analog voltage corresponding to it, an error detection section 16, a code conversion section 17, and a digital control section 18 having an error correction circuit and a control circuit. A microcomputer 26 controls automatic correction in the control section 18. The error detection value of the detection section 16 is stored in an error storage circuit 29, a corection value is obtained from a storage value and it is sotred in a correction data storage circuit 31. The correction data and lower- order digits of a digital input signal at input terminals 1
1 ∼1
n+m are summed at a summing circuit 32, and the conversion section 15 controls current sources 2a, 2b for correction.
COPYRIGHT: (C)1983,JPO&Japio
摘要翻译：目的：达到高线性度，通过数字技术自动校正线性度。构成：AD / A转换器包括一个D / A转换部分15，它接收一个纠错的数字信号并输出与之对应的模拟电压，一个误差检测部分16，一个代码转换部分17和一个数字控制部分18，纠错电路和控制电路。微型计算机26控制控制部分18中的自动校正。检测部分16的误差检测值被存储在误差存储电路29中，从存储值获得相互作用的值，并将其记录在校正数据存储电路31中输入端子11-1n + m处的数字输入信号的校正数据和低位数字在求和电路32相加，转换部分15控制电流源2a，2b进行校正。

4. 发明专利

JPS57123731A Correction system of digital-to-analog converter 失效
标题翻译：数字到模拟转换器的校正系统
公开(公告)号：JPS57123731A
公开(公告)日：1982-08-02
申请号：JP880481
申请日：1981-01-23
申请人： Hitachi Ltd , Nippon Telegr & Teleph Corp
发明人： SHIBAYAMA AKINORI , SATOU NOBUO , TAKAMOTO KIICHI , KATOU YASUO , OKUMURA MASAHIDE
IPC分类号： H03M1/10 , H03K13/02
CPC分类号： H03M1/10
摘要： PURPOSE:To improve linearity precision while correcting an error due to the output-value variation of a reference power source, by measuring and calculating the input and output relation of a DA converter and by setting a corrected value for the DA converter on the basis of the input and output relation. CONSTITUTION:A control circuit 6 sets a correcting operation state, and pattern data consisting of 2 bits obtained by changing the order of the high-order four bits of input digital data 7 is generated and inputted to a DA converter 1; and the obtained output analog value E0 is converted by a high-precision AD converter 3 into a digital value 10, and the input and output relation of the DA converter 1 is calculated by an arithmetic circuit 4 on the basis of the bit data 9 of the input digital data 7 to further calculate the difference. Then, 2 corrected values are stored in a storage circuit 5. When the control circuit 6 inputs the digital data 7 to the DA converter 1 for DA converting operation, the corrected values are read out of the storange circuit 5 and the correction of the correcting DA converter 1 is performed.
摘要翻译：目的：通过测量和计算DA转换器的输入和输出关系，并通过设置DA变换器的校正值，提高线性度精度，同时校正由于参考电源的输出值变化引起的误差，输入和输出关系。构成：控制电路6设置校正操作状态，并且生成由通过改变输入数字数据7的高位四位的顺序获得的2×4位的模式数据并输入到DA转换器1; 并且所获得的输出模拟值E0由高精度AD转换器3转换成数字值10，并且由转换器1的输入和输出关系由算术电路4基于位数据9的位数据9 输入数字数据7进一步计算差值。然后，将2 <4个校正值存储在存储电路5中。当控制电路6将数字数据7输入到DA转换器1进行DA转换操作时，校正值从存储电路5读出并进行校正执行校正DA转换器1。

5. 发明专利

JPS57122524A Blanking circuit for electron beam projector 失效
标题翻译：电子束投影机电路
公开(公告)号：JPS57122524A
公开(公告)日：1982-07-30
申请号：JP867781
申请日：1981-01-23
申请人： Hitachi Ltd , Nippon Telegr & Teleph Corp
发明人： SHIBAYAMA AKINORI , MATSUDA KOREHITO , TAKAMOTO KIICHI , OKUMURA MASAHIDE
IPC分类号： H01J37/26 , H01J37/04 , H01L21/027 , H01L21/30
CPC分类号： H01J37/045
摘要： PURPOSE:To improve accuracy for beam deflection position by a method wherein a blanking circuit is composed of a first current control element which is operated by on-off control signals of electron beams from an external unit and a second current control element which is activated by synchronizing opposite phase to the first current control element. In addition to this, constant electric current flow is maintained between a power supply and those current control elements independent of the on-off actions. CONSTITUTION:The blanking circuit consists of blanking plates 5, a control circuit 6A and the power supply 7A, and on-off control signals 1 of electron beams are applied to the circuit 6A from an external unit. In this arrangement, the circuit 6A is provided with a receiver 2 to receive the signals 1 and has a parallel circuit comprising a series circuit consisting of the first current control element 3A and a load resistance 4A, and a series circuit consisting of the second current control element 3B and a load resistance 4B. Then, voltage at the middle point between the element 3A and the resistance 4A is applied to the plate 5. The circuit is so provided that the second element 3B is characterized so as to synchronize opposite phase to the element 3A, and constant electric current flows through both the elements 3A, 3B from a constant-current source 12.
摘要翻译：目的：通过一种方法提高光束偏转位置的精度，其中消隐电路由第一电流控制元件组成，第一电流控制元件由来自外部单元的电子束的开 - 关控制信号和第二电流控制元件操作，第二电流控制元件由使与第一电流控制元件相反的相位同步。除此之外，在电源和那些电流控制元件之间保持恒定的电流流动，而与开 - 关动作无关。构成：消隐电路由消隐板5，控制电路6A和电源7A组成，电子束的开关控制信号1从外部单元施加到电路6A。在这种布置中，电路6A设置有接收信号1的接收机2，并且具有包括由第一电流控制元件3A和负载电阻4A组成的串联电路的并联电路和由第二电流组成的串联电路控制元件3B和负载电阻4B。然后，将元件3A和电阻4A之间的中点处的电压施加到板5.电路被设置为使得第二元件3B的特征在于与元件3A相反相位，并且恒定电流流动通过来自恒流源12的元件3A，3B两者。

6. 发明专利

JPS57124433A Patterning data processing for electron beam expossing device 失效
标题翻译：电子束曝光装置的数据处理方法
公开(公告)号：JPS57124433A
公开(公告)日：1982-08-03
申请号：JP880781
申请日：1981-01-23
申请人： Hitachi Ltd , Nippon Telegr & Teleph Corp
发明人： SHIMAZU NOBUO , SHIBAYAMA AKINORI , TAKAMOTO KIICHI , YODA HARUO , ISHIGA TADAKATSU
IPC分类号： H01L21/027 , H01J37/302 , H01L21/30
CPC分类号： H01J37/302
摘要： PURPOSE:To reduce the capacitance of the memory storage in which patterning data are memorized by a method wherein the pattern group to be repeatedly patterned is memorized as common patterning data, and a patterning is performed by repeatedly reading out the common patterning data. CONSTITUTION:The patterning data are transferred from the magnetic disc 1, wherein the patterning data of a plurality of chips are memorized, to a memory storage 2, and then transferred to a high-speed small capacitance memory storage 4 through the intermediary of a control section 3. A device control section 5 reads out the data stored in the memory storage 4, and a patterning is performed on the face of the sample on a stage 9 by controlling an electrooptical assembly 10. Among the patterns drawn on the surface of the sample, those which are repeatedly patterned are stored in the common data block of the memory storage 2 as common patterning data, and are used by repeatedly transferring them to the memory storage 4 every time a common pattern is drawn.
摘要翻译：目的：为了减少图案形成数据被存储的存储器存储器的电容，其中要重复构图的图案组被存储为常见的图案化数据，并且通过重复读出公共图案形成数据来执行图案化。构成：图形数据从磁盘1传送，其中多个芯片的图案化数据被存储到存储器存储器2中，然后通过控制的中间传送到高速小容量存储器存储器4 设备控制部分5读出存储在存储器4中的数据，并通过控制电光组件10在台9上的样品的表面上进行图案化。样本，被重复图案化的那些被存储在存储器存储器2的公共数据块中作为公共图案化数据，并且每当绘制公共图案时将它们重复地传送到存储器4来使用。

7. 发明专利

JPS57122528A Drawing system for electron beam exposure apparatus 失效
标题翻译：电子束曝光装置绘图系统
公开(公告)号：JPS57122528A
公开(公告)日：1982-07-30
申请号：JP880581
申请日：1981-01-23
申请人： Hitachi Ltd , Nippon Telegr & Teleph Corp
发明人： SHIMAZU NOBUO , SHIBAYAMA AKINORI , OOKUBO TSUNEO , YODA HARUO
IPC分类号： G06K15/12 , B43L13/00 , G03F7/20 , G03F7/26 , H01J37/302 , H01L21/027
CPC分类号： H01J37/3023
摘要： PURPOSE:To alleviate the steps in designing with an exposure apparatus by drawing a pattern with a data which designates a main deflection amount as a drawing data, a data which designates a drawing pattern in a sub deflection range and further additionally a data which designates a drawing pattern group repeatedly while superposing arbitrary sub deflection ranges. CONSTITUTION:A drawing data 11 is applied to a data translator 12, and selected data is supplied to a drawing controller 13 and main and sub deflection registers 14, 15. Subsequently, the output of the controller 13 is supplied to the registers 14, 15, and is also applied through a blanker 16 to an electro-optical mirror 19. Further, the output from the register 14 is applied through a main deflector DA converter 17 to a main deflector 20, and the output from the register 15 is supplied through a sub deflector DA converter 18 to a sub deflector 21. In this structure, the data 11 is composed of 3 types A, B, C. The A employs a data which sets the main deflection amount, the B employs B-1, B-2, wherein the B-1 designates a pattern in the sub deflection range, and the B-2 designates the indirect drawing. Further, C is similar to the B-1, but is used for the repeated data.
摘要翻译：目的：为了减轻用曝光装置进行设计的步骤，通过绘制具有指定主偏转量的数据作为绘图数据的图案，指定在亚偏转范围内的绘制图案的数据，并且还附加指定在叠加任意子偏转范围的同时反复绘制图案组。构成：将图形数据11应用于数据转换器12，将选择的数据提供给绘图控制器13以及主偏转寄存器14和主偏转寄存器15.随后，控制器13的输出被提供给寄存器14,15 并且还通过阻挡器16施加到电光镜19.另外，寄存器14的输出通过主偏转器DA转换器17施加到主偏转器20，并且寄存器15的输出通过副偏转器DA转换器18到副偏转器21.在该结构中，数据11由A，B，C三种组成.A采用设定主偏转量的数据，B使用B-1，B -2，其中B-1表示亚偏转范围内的图案，B-2表示间接图。此外，C类似于B-1，但用于重复数据。

8. 发明专利

JPS57122526A Dividing method for drawing figure in electron beam exposure apparatus 失效
标题翻译：用于在电子束曝光装置中绘制图的分割方法
公开(公告)号：JPS57122526A
公开(公告)日：1982-07-30
申请号：JP867981
申请日：1981-01-23
申请人： Hitachi Ltd , Nippon Telegr & Teleph Corp
发明人： SHIBAYAMA AKINORI , SHIMAZU NOBUO , MATSUDA KOREHITO , YODA HARUO , OZASA SUSUMU
IPC分类号： H01L21/027 , H01J37/302 , H01L21/30
CPC分类号： H01J37/302
摘要： PURPOSE:To eliminate the unsharpness of the periphery of an electron beam of an electron beam size variable exposure apparatus by comparing a figure to be drawn with the maximum allowable size of the beam, comparing the area of the figure with the predetermined value, and dividing the figure with the two values. CONSTITUTION:An exposure apparatus is composed of a height direction division control circuit 1, a width direction division control circuit 2, registers 3-9, a digital multiplier 10, digital comparators 11-15, a comparator 16 with a register, a subtractor 17, a digital comparator 18, selectors 19, 20 with registers, and a controller 21. Thus, the maximum allowable width W0 and the height H0 are respectively applied to the registers 3, 6, and the figure width W1 and height H1 to be divided are respectively set in the registers 5, 8. The value of H1XW1=C is set in the register 9, and the figure width W and height H of the entire figure to be divided are respectively set in the registers 4, 7. In this manner, the dividing mode is determined, and a figure is drawn in accordance with this.
摘要翻译：目的：为了消除电子束尺寸可变曝光装置的电子束周围的不清晰度，通过将要绘制的图形与光束的最大允许尺寸进行比较，将图形的面积与预定值进行比较，数字与两个值。构成：曝光装置由高度方向分割控制电路1，宽度方向分割控制电路2，寄存器3-9，数字乘法器10，数字比较器11-15，具有寄存器的比较器16，减法器17 数字比较器18，具有寄存器的选择器19,20以及控制器21.因此，最大允许宽度W0和高度H0分别施加到寄存器3,6，并且图形宽度W1和高度H1被分割分别设置在寄存器5,8中。在寄存器9中设置H1XW1 = C的值，并且要分割的整个图形的图形宽度W和高度H分别设置在寄存器4,7中。在此方式，确定分割模式，并根据此绘制图形。

9. 发明专利

JPS57122525A Dividing method for drawing figure in electron beam exposure apparatus 失效
标题翻译：用于在电子束曝光装置中绘制图的分割方法
公开(公告)号：JPS57122525A
公开(公告)日：1982-07-30
申请号：JP867881
申请日：1981-01-23
申请人： Hitachi Ltd , Nippon Telegr & Teleph Corp
发明人： SHIBAYAMA AKINORI , SHIMAZU NOBUO , FUJINAMI AKIHIRA , YODA HARUO
IPC分类号： H01L21/027 , H01J37/302 , H01L21/30
CPC分类号： H01J37/302
摘要： PURPOSE:To eliminate the unsharpness of the end of an electron beam of an electron beam size variable exposure apparatus by dividing a figure into figure segments of the size capable of being solely emitted when a figure which is larger than the maximum size capable of being drawn by the beam is drawn and dividing the size of the figure into the figure segments larger than the predetermined minimum size. CONSTITUTION:There are provided figure height and width size registers 21, 22, electron beam height and width maximum size registers 23, 24, registers 25, 26 for setting the sum of the electron beam height and width minimum size plus previous maximum size of the beam not affected by the influence of an unsharpness, and registers 27, 28 for dividing the height and the width into desired size, and further registers 29-31 capable of selecting two inputs at the rear stages of the registers 21, 23, 25, 27, a register 32, a subtractor 33, an AND gate 34, digital comparators 35, 36, and a controller 37. A figure 40 to be drawn and to be divided is connected to the rear stages of the registers 22, 24, 26, 28, and a name register is controlled by the controller 37, and the figure 40 is divided into the size larger than the predetermined minimum size.
摘要翻译：目的：为了消除电子束尺寸可变曝光装置的电子束末端的不清晰度，通过将图形划分成当能够被绘制的大于最大尺寸的图形时能够被单独发射的尺寸的图形部分通过光束被绘制并将图的大小划分成大于预定最小尺寸的图形段。规定：提供图形高度和宽度尺寸寄存器21,22，电子束高度和宽度最大尺寸寄存器23,24，寄存器25,26，用于设置电子束高度和宽度最小尺寸之和加上先前最大尺寸的和光束不受不清晰度的影响的影响，并且用于将高度和宽度分成所需尺寸的寄存器27,28以及能够在寄存器21,23,25的后级选择两个输入的另外的寄存器29-31， 27，寄存器32，减法器33，与门34，数字比较器35,36和控制器37.待绘制并被分割的图40连接到寄存器22,24,26的后级，28，并且由控制器37控制名称寄存器，并且将图40划分为大于预定最小尺寸的尺寸。

10. 发明专利

JPS60263526A REFERENCE SIGNAL GENERATING CIRCUIT 失效
公开(公告)号：JPS60263526A
公开(公告)日：1985-12-27
申请号：JP12011784
申请日：1984-06-11
申请人： ADVANTEST CORP , NIPPON TELEGRAPH & TELEPHONE
发明人： HARAGUCHI HIROBUMI , SHIBAYAMA AKINORI
IPC分类号： H03F3/343 , H03F3/34 , H03M1/74
摘要： PURPOSE:To obtain a high-stability reference signal generating circuit without expensive parts by converting a reference voltage to a current and giving this current to a converting resistor coupled thermally to a bit current determining resistor of the signal generating circuit. CONSTITUTION:A reference voltage Vr generated in a reference voltage generating part 1 is converted to a current signal Jr by a voltage-current converting part 11, and this signal Jr is converted reverse to a voltage V0 by a current- voltage converter 12, and this voltage V0 is supplied as the reference voltage to a signal generating part 2. A voltage converting resistor 12a of the converter 12 and bit current determining resistors 2i (i=a-n) of the generating part 2 are formed close to each other on the same substrate as thin film resistors, and the same conditions are given to them with respect to temperature. A switch 4i is turned on selectively by a digital signal, and an analog voltage corresponding to a bit current Ji flowed to a constant current circuit 3i is obtained in an output terminal 6 of an operational amplifier 5. Since voltages generated in resistances 12a and 2i in the same temperature conditions are applied to in-phase and anti-phase input terminals of an operational amplifier Ai, the variation of voltage due to temperature is cancelled.

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