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1. 发明专利

JP2007124141A Delay lock loop circuit, timing generator, semiconductor test apparatus, semiconductor integrated circuit, and delay amount calibration method 有权
标题翻译：延迟锁定环路，时序发生器，半导体测试装置，半导体集成电路和延迟量校准方法
公开(公告)号：JP2007124141A
公开(公告)日：2007-05-17
申请号：JP2005311661
申请日：2005-10-26
申请人： Advantest Corp , 株式会社アドバンテスト
发明人： HASUMI TAKUYA , SUDA MASAKATSU
IPC分类号： H03L7/081 , G01R31/28 , G01R31/3183 , G01R31/319 , H03K5/00 , H03K5/04 , H03L7/095
CPC分类号： H04L7/0337 , H03K5/133 , H03K2005/00026 , H03K2005/00097 , H03L7/0812 , H03L7/087 , H03L7/091
摘要： PROBLEM TO BE SOLVED: To provide a delay lock loop circuit, a timing generator, a semiconductor test apparatus, a semiconductor integrated circuit, and a delay amount calibration method capable of reducing a time required for calibrating a delay circuit by determining an initial setting value of a counter by a technology in place of measuring a delay amount. SOLUTION: One of a plurality of counter setting values is loaded, a delay lock loop circuit 10-1 is switched to a lock mode, a sequence circuit 22 of a cycle slip detection circuit 20-1 is reset, and thereafter when a cyclic slip detection signal outputted from the sequence circuit 22 is read, whether or not an output signal of the delay circuit 11 causes a cycle slip on the basis of the cyclic slip detection signal is discriminated, when the cycle slip takes place, another counter setting value is selected, or when no cycle slip takes place, the counter is locked and the processing is terminated. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种延迟锁定环路电路，定时发生器，半导体测试装置，半导体集成电路和延迟量校准方法，其能够通过确定延迟锁定环路电路来缩短校准延迟电路所需的时间代替测量延迟量的技术的计数器的初始设定值。解决方案：加载多个计数器设置值中的一个，延迟锁定环路电路10-1被切换到锁定模式，周期滑移检测电路20-1的序列电路22被复位，之后当读取从顺序电路22输出的循环滑移检测信号，判断延迟电路11的输出信号是否在循环滑移检测信号的基础上引起循环滑移，当发生循环滑移时，另一个计数器选择设定值，或者当没有发生循环滑移时，计数器被锁定，处理结束。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2007033385A Timing generator and semi-conductor testing equipment 有权
标题翻译：定时发电机和半导体测试设备
公开(公告)号：JP2007033385A
公开(公告)日：2007-02-08
申请号：JP2005220766
申请日：2005-07-29
申请人： Advantest Corp , 株式会社アドバンテスト
发明人： SUDA MASAKATSU
IPC分类号： G01R31/3183
CPC分类号： G01R31/31922 , H03K5/133 , H03K2005/00156 , H03K2005/00195 , H03K2005/00208
摘要： PROBLEM TO BE SOLVED: To simplify the circuit for controlling the variable delay circuit of a timing generator in real time and to secure the timing margin (Eye opening). SOLUTION: The variable delay circuit 10 of the timing generator comprises: the delay circuit 11 comprising the serially connected plurality of clock buffers 13-1 to 13-n, a plurality of serially connected data buffers 15-11 to 15-nn, and the data retaining circuit 16-0 to 16-n for outputting the data to the data buffers 15-11 to 15-nn while synchronizing with the clock from the delay circuit 11. The delayed amount added to the data by the data buffer 15-11 to 15-nn and the delayed amount added to the clock by the clock buffers 13-1 to 13-n, are made the same. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：简化用于实时控制定时发生器的可变延迟电路的电路并确保定时裕度（眼睛打开）。解决方案：定时发生器的可变延迟电路10包括：延迟电路11，包括串行连接的多个时钟缓冲器13-1至13-n，多个串行连接的数据缓冲器15-11至15-nn 以及用于在与来自延迟电路11的时钟同步的同时将数据输出到数据缓冲器15-11至15-nn的数据保持电路16-0至16-n。由数据缓冲器添加到数据的延迟量 15-11至15-nn，并且由时钟缓冲器13-1至13-n添加到时钟的延迟量被制成相同。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2007071622A Tester and test method 有权
标题翻译：测试和测试方法
公开(公告)号：JP2007071622A
公开(公告)日：2007-03-22
申请号：JP2005257435
申请日：2005-09-06
申请人： Advantest Corp , 株式会社アドバンテスト
发明人： TANAKA KOICHI , SUDA MASAKATSU
IPC分类号： G01R31/319 , G01R19/252
CPC分类号： G01R31/31901 , G01R31/31721
摘要： PROBLEM TO BE SOLVED: To efficiently measure the amount of variation in a power source voltage accompanying a change in electric current consumption in a device under test. SOLUTION: This tester for testing variation in the power source voltage supplied to the device under test is equipped with: a power source part for supplying the power source voltage to a power source input terminal of the device; an oscillator for outputting a clock signal of a frequency corresponding to the source voltage supplied to the input terminal of the device; and a measurement part for measuring the frequency of the clock signal. For example, the oscillator outputs, as the clock signal, an output signal of any NOT logical element out of an odd number of NOT logical elements together connected like a loop. The logical element operates with a voltage corresponding to the source voltage used as a voltage source, the source voltage supplied to the input terminal of the device. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了有效地测量伴随着被测设备的电流消耗变化的电源电压的变化量。该测试器用于测试供应给被测器件的电源电压变化，该电源部件用于将电源电压提供给该器件的电源输入端; 振荡器，用于输出与提供给所述装置的输入端的源电压相对应的频率的时钟信号; 以及用于测量时钟信号的频率的测量部分。例如，振荡器作为时钟信号输出来自奇数个非逻辑元件的任何NOT逻辑元件的输出信号，其一起连接成环路。逻辑元件以与用作电压源的源电压相对应的电压工作，源电压提供给器件的输入端。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2007033386A Timing generator and semi-conductor testing equipment 有权
标题翻译：定时发电机和半导体测试设备
公开(公告)号：JP2007033386A
公开(公告)日：2007-02-08
申请号：JP2005220767
申请日：2005-07-29
申请人： Advantest Corp , 株式会社アドバンテスト
发明人： SUDA MASAKATSU
IPC分类号： G01R31/3183
CPC分类号： G01R31/31922 , G01R31/31721 , H03K5/131 , H03K5/1504 , H03K2005/00026 , H03L7/0812
摘要： PROBLEM TO BE SOLVED: To reduce the consuming electric power (AC component) depending on the motion, or the noise generated by a clock distribution circuit itself, and also to reduce the SKEW due to the clock distribution. SOLUTION: The clock distribution circuit 20 for distributing the clock to a plurality of timing generators 10-1 to 10-n comprises: the clock maine path 21 connected with the main buffer 24 for the main path; and the clock send back path 26 connected with the buffer 27 for the send back path, wherein the load capacities of buffer 24 for the main path and the buffer 27 for the send back path are designed to be the same, and biases of these buffers are made the same potential, and controlled so that the delay time of the propagation of the clock distribution circuits is made integer times of the clock interval by generating the bias by the delay locked loop 30. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：根据运动或由时钟分配电路本身产生的噪声来减少消耗电力（AC分量），并且还由于时钟分配而减少SKEW。解决方案：用于将时钟分配给多个定时发生器10-1至10-n的时钟分配电路20包括：与用于主路径的主缓冲器24连接的时钟脉冲路径21; 以及与发送回路径的缓冲器27连接的时钟发回路径26，其中用于主路径的缓冲器24的负载容量和用于发送回路径的缓冲器27被设计为相同，并且这些缓冲器的偏置被制成相同的电位，并被控制，使得时钟分配电路的传播的延迟时间通过延迟锁定环路30产生偏置量而变成时钟间隔的整数倍。（C）2007， JPO＆INPIT

5. 发明专利

JP2006229622A Load fluctuation compensating circuit, electronic device, testing device and timing generating circuit 有权
标题翻译：负载增益补偿电路，电子设备，测试设备和时序生成电路
公开(公告)号：JP2006229622A
公开(公告)日：2006-08-31
申请号：JP2005041182
申请日：2005-02-17
申请人： Advantest Corp , 株式会社アドバンテスト
发明人： HASUMI TAKUYA , SUDA MASAKATSU
IPC分类号： H03K19/00
CPC分类号： H03K19/00346 , H03K19/007
摘要： PROBLEM TO BE SOLVED: To provide a load fluctuation compensating circuit for compensating the fluctuation of current consumption depending on the driving status of a logic circuit thereby reducing the fluctuation of a power supply voltage to be applied to the logic circuit.
SOLUTION: The load fluctuation compensating circuit compensates a power supply voltage to be supplied to the logic circuit. The load fluctuation compensating circuit is designed so that a cyclic signal to be applied is outputted with a predetermined time delay when the power supply voltage to be supplied to the logic circuit is applied as a power source, and the load fluctuation compensating circuit is provided with: a delay circuit for driving the power supply voltage to be supplied to the logic circuit as a power source; a current consuming circuit whose power source is common to the logic circuit; and a phase comparator circuit for controlling current quantity to be consumed by the current consuming circuit so that a phase difference between the phase of a cyclic signal to be inputted to the delay circuit and the phase of a signal to be outputted by the delay circuit becomes a predetermined time.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：提供一种负载波动补偿电路，用于根据逻辑电路的驱动状态补偿电流消耗的波动，从而减少施加到逻辑电路的电源电压的波动。
解决方案：负载波动补偿电路补偿供给逻辑电路的电源电压。负载波动补偿电路被设计成当要施加到逻辑电路的电源电压作为电源时，以预定的时间延迟输出要施加的循环信号，并且负载波动补偿电路设置有用于驱动作为电源提供给逻辑电路的电源电压的延迟电路; 其电源与逻辑电路相同的电流消耗电路; 以及相位比较器电路，用于控制由电流消耗电路消耗的电流量，使得要输入到延迟电路的循环信号的相位与由延迟电路输出的信号的相位之间的相位差成为一个预定的时间。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2005311564A Jitter generation circuit 审中-公开
标题翻译：犹太人生成电路
公开(公告)号：JP2005311564A
公开(公告)日：2005-11-04
申请号：JP2004123872
申请日：2004-04-20
申请人： Advantest Corp , 株式会社アドバンテスト
发明人： WATANABE DAISUKE , SUDA MASAKATSU
IPC分类号： H03K5/156 , H03K5/1532
CPC分类号： H03K5/156
摘要： PROBLEM TO BE SOLVED: To provide a jitter generation circuit that does not require an analog circuit, reduces circuit size, and can reduce power consumption. SOLUTION: The jitter generation circuit comprises signal wiring P1 to which a clock signal, where a jitter component is added, is transmitted; an input buffer 10 provided at the input side of the signal wiring P1; an output buffer 30 provided at the output side of the signal wiring P1; signal wiring P2 closely arranged to the signal wiring P1; and a jitter generation signal output section 20 for inputting a jitter generation signal in synchronization with the clock signal inputted to the signal wiring P1 to the signal wiring P2. As the jitter generation signal, for example a pseudo random bit string signal is used. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供不需要模拟电路的抖动生成电路，减小电路尺寸，并且可以降低功耗。解决方案：抖动发生电路包括发送抖动分量的时钟信号的信号布线P1; 设置在信号线P1的输入侧的输入缓冲器10; 设置在信号线P1的输出侧的输出缓冲器30; 信号线P2紧贴在信号线P1上; 和抖动产生信号输出部分20，用于与输入到信号线P1的时钟信号同步地向信号线P2输入抖动产生信号。作为抖动产生信号，例如使用伪随机位串信号。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2003017988A Delay circuit and test device 有权
标题翻译：延迟电路和测试设备
公开(公告)号：JP2003017988A
公开(公告)日：2003-01-17
申请号：JP2001198359
申请日：2001-06-29
申请人： Advantest Corp , 株式会社アドバンテスト
发明人： SUDA MASAKATSU
IPC分类号： G01R31/28 , H03K5/14
摘要： PROBLEM TO BE SOLVED: To provide a delay circuit with a small delay error.
SOLUTION: This invention provides the delay circuit for delaying a given input signal on the basis of a delay setting value and providing an output is characterized in to comprise a delay section comprising a plurality of delay elements, a storage section for storing supply position data for denoting to which of a plurality of the delay elements in cascade connection the input signal is to be supplied corresponding respectively to each of a plurality of predetermined delay setting values, and a selection section for selecting to which of a plurality of the delay elements the input signal is to be supplied based on the delay setting values and the supply position data.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供延迟误差小的延迟电路。解决方案：本发明提供延迟电路，用于基于延迟设置值延迟给定的输入信号，并提供输出的特征在于包括一个包括多个延迟元件的延迟部分，一个存储部分，用于存储供给位置数据，表示级联连接中的多个延迟元件中的哪一个将分别输入到多个预定延迟设置值中的每一个，以及选择部分，用于选择多个延迟元件中的哪一个延迟元件的输入将根据延迟设定值和供给位置数据提供信号。

8. 发明专利

JP2013058908A Compensation device and testing device 审中-公开
标题翻译：补偿装置和测试装置
公开(公告)号：JP2013058908A
公开(公告)日：2013-03-28
申请号：JP2011196057
申请日：2011-09-08
申请人： Advantest Corp , 株式会社アドバンテスト
发明人： IKEMOTO JUNICHI , SUDA MASAKATSU
IPC分类号： H03K19/00 , G01R31/28
摘要： PROBLEM TO BE SOLVED: To suppress power consumption.SOLUTION: A compensation device for compensating for current consumption of a target circuit which operates by a power supply voltage applied from a power supply device includes: a current consumption unit which is connected to power supply wiring for supplying the power supply voltage from the power supply device to the target circuit and consumes a current flowing through the power supply wiring; a current control unit which changes the current to be consumed by the current consumption unit in accordance with the power supply voltage applied to the current consumption unit; and a setting unit which changes the amount of reference current of the current consumption unit. The setting unit reduces the amount of reference current when the target circuit is in a standby state.
摘要翻译：要解决的问题：抑制功耗。解决方案：一种补偿装置，用于补偿由从电源装置施加的电源电压工作的目标电路的电流消耗，包括：电流消耗单元，连接到电源布线，用于将电源电压从电源装置到目标电路并消耗流过电源布线的电流; 电流控制单元，其根据施加到电流消耗单元的电源电压改变由电流消耗单元消耗的电流; 以及改变电流消耗单元的参考电流量的设置单元。当目标电路处于待机状态时，该设置单元减少参考电流的量。版权所有（C）2013，JPO＆INPIT

9. 发明专利

JP2011154009A Testing instrument, measuring instrument, and electronic device 审中-公开
标题翻译：测试仪器，测量仪器和电子设备
公开(公告)号：JP2011154009A
公开(公告)日：2011-08-11
申请号：JP2010017462
申请日：2010-01-28
申请人： Advantest Corp , 株式会社アドバンテスト
发明人： SUDA MASAKATSU , HAYASE YUSUKE
IPC分类号： G01R29/02 , G01R29/00 , G01R31/319 , H01L21/822 , H01L27/04
CPC分类号： G01R31/31709
摘要： PROBLEM TO BE SOLVED: To solve the problem that, when a jitter is measured using a time interval analyzer or the like, measurement cost will increase, and when an analysis signal is used, computation of measured data becomes troublesome, and to make it possible to easily measure jitter of measured signal. SOLUTION: A testing instrument for determining whether or not measured signals are appropriate includes a frequency counter for repeating plural times a counting step of counting the number of pulses of a reference signal the cycle of which is known, and the number of pulses of the measured signals in parallel within the identical measurement period of time, an average period calculation unit for calculating average periods of the measured signals in the measurement period of time for respective counting steps, based on a ratio of the number of pulses of the reference signal to the number of pulses of the measured signals counted within the identical measurement period of time, and a frequency of the reference signal, a noise calculation unit for calculating dispersion of the average periods calculated by the average period calculation unit, and a determination unit for determining whether or not the measured signals are appropriate, based on the dispersion of the average periods. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题为了解决当使用时间间隔分析器等测量抖动时，测量成本将增加的问题，并且当使用分析信号时，测量数据的计算变得麻烦，并且可以轻松测量测量信号的抖动。解决方案：用于确定测量信号是否适当的测试仪器包括用于重复多次的计数步骤，该计数步骤对已知周期的参考信号的脉冲数进行计数，并且脉冲数在相同的测量时段内并联测量的信号，平均周期计算单元，用于基于参考的脉冲数的比率来计算各个计数步骤的测量时间段中的测量信号的平均周期信号到在相同的测量时段内计数的测量信号的脉冲数和参考信号的频率，用于计算由平均周期计算单元计算的平均周期的色散的噪声计算单元和确定单元用于基于平均周期的偏差来确定测量信号是否合适。版权所有（C）2011，JPO＆INPIT

10. 发明专利

JP2009246484A Vernier delay circuit, time digital converter using the same, and test device 有权
标题翻译： VERNIER延迟电路，使用相同的时间数字转换器和测试设备
公开(公告)号：JP2009246484A
公开(公告)日：2009-10-22
申请号：JP2008088016
申请日：2008-03-28
申请人： Advantest Corp , 株式会社アドバンテスト
发明人： KOJIMA SHOJI , SUDA MASAKATSU
IPC分类号： H03K5/13 , H03L7/00
CPC分类号： H03K5/131 , H03K2005/00052 , H03K2005/00065 , H03L7/0805 , H03L7/0995
摘要： PROBLEM TO BE SOLVED: To provide a vernier delay circuit for performing highly precise calibration. SOLUTION: A ring oscillator 10 oscillates at a frequency corresponding to an input bias signal SbiasG. A bias signal adjustment part 12 generates the bias signal SbiasG to the ring oscillator 10 by feedback so that an oscillation frequency of the ring oscillator 10 matches a prescribed reference frequency. An individual bias circuit 14 is provided with a plurality of bias circuits BIAS 1 to BIAS N provided for each of N second variable delay elements D2 1 to D2 N . The respective bias circuits BIAS 1 to BIAS N are configured to adjust each of bias signals Sbias2A 1 to Sbias2A N . COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于执行高精度校准的游标延迟电路。解决方案：环形振荡器10以对应于输入偏置信号SbiasG的频率振荡。偏置信号调整部分12通过反馈产生环形振荡器10的偏置信号SbiasG，使得环形振荡器10的振荡频率与规定的参考频率相匹配。单个偏置电路14设置有为N个第二可变延迟元件D2 1 中的每一个提供的多个偏置电路BIAS 1 到BIAS N 到D2 N 。各个偏置电路BIAS 1 到BIAS N 被配置为将每个偏置信号Sbias2A 1 调整为Sbias2A N 。版权所有（C）2010，JPO＆INPIT

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