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1. 发明专利

JP2011154762A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2011154762A
公开(公告)日：2011-08-11
申请号：JP2010015731
申请日：2010-01-27
申请人： Toshiba Corp , 株式会社東芝
发明人： ITO MIKIHIKO , NAKANO TAKESHI , NAKAGAWA MICHIO
IPC分类号： G11C16/02 , G11C16/06
CPC分类号： G11C16/16 , G11C5/145 , G11C16/0483 , G11C16/30
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device having data erase mode that suppresses deterioration of cell characteristics. SOLUTION: The semiconductor memory device includes: a memory cell array where nonvolatile memory cells are arranged; and an erase voltage generation circuit that generates an erase voltage for erasing data in the memory cell array. In the data erase mode that applies the erase voltage to selected regions in the memory cell array in multiple cycles, a rise waveform of the erase voltage at an initial phase of the multiple erase cycles is less steep than that in subsequent cycles. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有抑制电池特性劣化的数据擦除模式的半导体存储器件。解决方案：半导体存储器件包括：非易失性存储单元布置的存储单元阵列; 以及产生用于擦除存储单元阵列中的数据的擦除电压的擦除电压产生电路。在以多个周期将擦除电压施加到存储单元阵列中的选定区域的数据擦除模式中，多个擦除周期的初始相位处的擦除电压的上升波形不如后续周期那样急剧上升。版权所有（C）2011，JPO＆INPIT

2. 发明专利

JP2008028004A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2008028004A
公开(公告)日：2008-02-07
申请号：JP2006196505
申请日：2006-07-19
申请人： Toshiba Corp , 株式会社東芝
发明人： ITO MIKIHIKO , KOYANAGI MASARU , MATSUDERA KATSUKI
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： G11C5/14 , G11C5/02 , G11C5/025 , H01L2224/48091 , H01L2224/48227 , H01L2225/06562 , H01L2924/13091 , H01L2924/15192 , H01L2924/30107 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that can be inexpensively manufactured by reducing a chip area of a semiconductor chip and that of a memory controller, and also that achieves relaxation in spatial restrictions between chips in a multi-chip package. SOLUTION: The semiconductor device is provided with a package substrate 11, each semiconductor chip 12, the memory controller 13 for controlling each semiconductor chip 12, and a power-supply chip 14 having a semiconductor capacitor. The semiconductor device is composed so that the semiconductor chips 12(1), 12(2) are mounted on the package substrate 11, the memory controller 13 and the power-supply chip 14 are mounted on the semiconductor chip 12(2), and the semiconductor capacitor is used for stabilizing a voltage supplied to the semiconductor chips 12(1), 12(2). COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供可以通过减少半导体芯片和存储器控制器的芯片面积而廉价地制造的半导体器件，并且还实现了在多芯片封装中的芯片之间的空间限制的放松。解决方案：半导体器件设置有封装基板11，每个半导体芯片12，用于控制每个半导体芯片12的存储器控制器13以及具有半导体电容器的电源芯片14。半导体器件被构成为使得半导体芯片12（1），12（2）安装在封装基板11上，存储器控制器13和电源芯片14安装在半导体芯片12（2）上，并且半导体电容器用于稳定提供给半导体芯片12（1），12（2）的电压。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2014187416A Differential amplifier and data output circuit 有权
标题翻译：差分放大器和数据输出电路
公开(公告)号：JP2014187416A
公开(公告)日：2014-10-02
申请号：JP2013058940
申请日：2013-03-21
申请人： Toshiba Corp , 株式会社東芝
发明人： INAGAKI MANO , KOYANAGI MASARU , ITO MIKIHIKO
IPC分类号： H03K5/08 , H03F3/45 , H03F3/68
摘要： PROBLEM TO BE SOLVED: To provide a differential amplifier and a data output circuit that reduce current consumption by suppressing a tail current.SOLUTION: A first transistor N103 is connected between a first constant current source CI1 and a first current mirror type differential amplifier CDA1 and is supplied with a first input signal at a gate electrode. A second transistor P103 is connected between a second current mirror type differential amplifier and a second constant current source CI2 and is supplied with the first input signal at a gate electrode.
摘要翻译：要解决的问题：提供一种通过抑制尾流来降低电流消耗的差分放大器和数据输出电路。解决方案：第一晶体管N103连接在第一恒流源CI1和第一电流镜型差分放大器CDA1之间，在栅电极处提供第一输入信号。第二晶体管P103连接在第二电流镜型差分放大器和第二恒流源CI2之间，并在栅电极处被提供有第一输入信号。

4. 发明专利

JP2009123292A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2009123292A
公开(公告)日：2009-06-04
申请号：JP2007297024
申请日：2007-11-15
申请人： Toshiba Corp , 株式会社東芝
发明人： ITO MIKIHIKO
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C7/04 , G11C11/5642 , G11C16/26 , G11C16/30
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of correctly reading memory cell data and reducing defective bits without any dependence on temperature. SOLUTION: The semiconductor memory device includes a memory cell array 21 where memory cells capable of storing multiple bit data are arranged in a matrix, a reading part 23 for reading data from the memory cells of the memory cell array, a writing part 23 for writing data in the memory cells of the memory cell array, a reading voltage generation part 28 for generating a reading voltage to supply it to the reading part, and a voltage control unit 30 for controlling the reading voltage depending on a temperature. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：提供能够正确读取存储单元数据并减少有缺陷的位而不依赖于温度的半导体存储器件。解决方案：半导体存储器件包括存储单元阵列21，其中能够存储多个位数据的存储器单元以矩阵形式布置;读取部分23，用于从存储单元阵列的存储单元读取数据;写入部分 23，用于在存储单元阵列的存储单元中写入数据，用于产生读取电压以将其提供给读取部分的读取电压产生部分28，以及用于根据温度控制读取电压的电压控制单元30。版权所有（C）2009，JPO＆INPIT

5. 发明专利

JP2008166430A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2008166430A
公开(公告)日：2008-07-17
申请号：JP2006353225
申请日：2006-12-27
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： KODAMA CHIKAAKI , ITO MIKIHIKO
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L25/0657 , H01L24/06 , H01L2224/05553 , H01L2224/05599 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/85399 , H01L2225/0651 , H01L2225/06527 , H01L2225/06555 , H01L2225/06562 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/07802 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a technique device, whereby the size and thickness of a multiple-chip package can be reduced and the inside connections of the package can be simplified. SOLUTION: In the semiconductor device, there is provided a package substrate 100 and first and second semiconductor chips 10, 20 which have rectangular top surfaces and are laminated on the package substrate 100, and the first semiconductor chip 10 has a plurality of first pads 11 provided along a short side W1. The second semiconductor chip 20 has a plurality of second pads 21 provided along a short side W2, and the topmost vertex of the second semiconductor chip 20 which comprises its long side and its short side that have no plurality of second pads 21 and the topmost vertex of the first semiconductor chip 10, which comprises its long side and short side that have no plurality of first pads 11 overlaps with each other in the vertical direction, and the first and second semiconductor chips 10, 20 are so laminated so that their long sides cross. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种技术装置，由此可以减少多芯片封装的尺寸和厚度，并且可以简化封装的内部连接。解决方案：在半导体器件中，提供了封装基板100和具有矩形顶表面并层叠在封装基板100上的第一和第二半导体芯片10,20，并且第一半导体芯片10具有多个沿短边W1设置的第一焊盘11。第二半导体芯片20具有沿着短边W2设置的多个第二焊盘21，第二半导体芯片20的最上面的顶点包括其长边和短边，其中没有多个第二焊盘21和最顶端的顶点第一半导体芯片10包括其长边和短边，其没有多个第一焊盘11在垂直方向上彼此重叠，并且第一和第二半导体芯片10,20被层压，使得它们的长边交叉。版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP2008130998A Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：JP2008130998A
公开(公告)日：2008-06-05
申请号：JP2006317523
申请日：2006-11-24
申请人： Toshiba Corp , 株式会社東芝
发明人： ITO MIKIHIKO , KOYANAGI MASARU
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L25/0657 , H01L23/50 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/18 , H01L2224/0401 , H01L2224/05553 , H01L2224/05554 , H01L2224/05599 , H01L2224/45144 , H01L2224/48091 , H01L2224/48145 , H01L2224/48147 , H01L2224/48599 , H01L2224/4911 , H01L2224/85399 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2225/06555 , H01L2225/06562 , H01L2225/06575 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/07802 , H01L2924/14 , H01L2924/30105 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which can prevent deterioration in the performance of memory chips that constitute a multi-chip package, and further for which increase in the package size is suppressed. SOLUTION: This semiconductor integrated circuit comprises a package substrate 100; a first memory chip 1 which has a first power source pad 11A, disposed on a first side A1 of the package substrate 100 and a second power source pad 11B, disposed on a second side B1 being perpendicular to the first side A1; and a second memory chip 2 placed above the first memory chip 1 and has the same structure as that of the first memory chip 1. The second memory chip 2 is subjected to parallel movement, in such a direction that the first power source pad 11A and the second power source pad 11B are exposed, and the first power source pad 11A and the second power source pad 11B are disposed at the diagonal portions of the first memory chip 1, respectively. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种可以防止构成多芯片封装的存储芯片的性能劣化的半导体集成电路，并且进一步抑制了封装尺寸的增加。解决方案：该半导体集成电路包括封装基板100; 第一存储器芯片1，其具有设置在封装基板100的第一侧A1上的第一电源焊盘11A和与第一侧A1垂直的第二侧面B1上的第二电源焊盘11B; 以及设置在第一存储芯片1上方并具有与第一存储芯片1相同结构的第二存储芯片2.第二存储芯片2沿第一电源焊盘11A和第二电源焊盘11B被暴露，并且第一电源焊盘11A和第二电源焊盘11B分别设置在第一存储芯片1的对角部分。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2006277867A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2006277867A
公开(公告)日：2006-10-12
申请号：JP2005097936
申请日：2005-03-30
申请人： Toshiba Corp , 株式会社東芝
发明人： ITO MIKIHIKO , MATSUDERA KATSUKI
IPC分类号： G11C29/56 , G01R31/28 , G11C11/401
CPC分类号： G11C7/1036 , G11C7/1039 , G11C7/1051 , G11C7/106 , H03K3/356139
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device which can check its input and output function and reduce the check cost even when using an inexpensive checker which has input and output speed slower than its own data input and out put speed.
SOLUTION: A data multiplexer 11 has a plurality of input parallel data lines and a plurality of output parallel data lines and switches its outputting states according to the control signals: that is, the state of outputting the parallel data that are read from the memory core section 2 and inputted into the plurality of parallel data lines to the plurality of output parallel data lines corresponding respectively, and the state of selecting 1-bit data from the parallel data that are inputted into the plurality of input parallel data lines to output to plurality of the output parallel data lines. The data outputted from the data multiplexer 11 are converted by the shift register 8 and the output data buffer circuit 9 into the serial data, and outputted to the external data line pair DQ/bDQ by the output drive circuit 10.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种可以检查其输入和输出功能并降低检查成本的半导体存储器件，即使当使用具有比其自身数据输入和输出速度慢的输入和输出速度的廉价检查器时。解决方案：数据多路复用器11具有多条输入并行数据线和多条输出并行数据线，并根据控制信号切换其输出状态：即输出从存储器核心部分2并分别输入到分别对应的多个输出并行数据线的多条并行数据线中，以及从输入到多条输入并行数据线的并行数据中选择1位数据的状态，输出到多个输出并行数据线。从数据多路复用器11输出的数据由移位寄存器8和输出数据缓冲电路9转换为串行数据，并通过输出驱动电路10输出到外部数据线对DQ / bDQ。版权所有：（C）2007，JPO＆INPIT

8. 发明专利

JP2006005184A Semiconductor integrated circuit 审中-公开
标题翻译：半导体集成电路
公开(公告)号：JP2006005184A
公开(公告)日：2006-01-05
申请号：JP2004180375
申请日：2004-06-18
申请人： Toshiba Corp , 株式会社東芝
发明人： ITO MIKIHIKO , KOYANAGI MASARU
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8234 , H01L27/06 , H01L27/088 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of operating at a voltage lower than the inverse breakdown voltage of a protective diode and having a protection circuit.
SOLUTION: An n+ drain layer D1 and a polycrystalline silicon film 16 are connected to an electrostatic protection circuit, and a vertical trench type MOS transistor TR1 is provided with the n+ polycrystalline silicon film 16 as a gate, the n+ drain layer D1 as a drain, a first n-well layer 11 as a source, and a first p-well layer 13 as a channel. A capacity C1 is provided among the n+ policrystalline silicon film 16, the first p-well layer 13, the first n-well layer 11, and a p-type silicon substrate 10. At the same time, a diode Di1 is provided between the p-type silicon substrate 10 and the second n-well layer 12.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够以低于保护二极管的反向击穿电压的电压工作并具有保护电路的半导体集成电路。
解决方案：n +漏极层D1和多晶硅膜16连接到静电保护电路，并且垂直沟槽型MOS晶体管TR1设置有n +多晶硅膜16作为栅极，n +漏极层D1 作为漏极，作为源的第一n阱层11和作为沟道的第一p阱层13。在n +极晶硅膜16，第一p阱层13，第一n阱层11和p型硅衬底10之间提供电容C1。同时，二极管Di1设置在 p型硅衬底10和第二n阱层12.版权所有（C）2006，JPO＆NCIPI

9. 发明专利

JP2004178738A Semiconductor memory 有权
公开(公告)号：JP2004178738A
公开(公告)日：2004-06-24
申请号：JP2002345655
申请日：2002-11-28
申请人： Toshiba Corp , 株式会社東芝
发明人： ITO MIKIHIKO , TAIRA TAKASHI , KOYANAGI MASARU
IPC分类号： G11C11/409 , G11C7/06 , G11C11/4091
CPC分类号： G11C7/065 , G11C11/4091 , G11C2207/005 , G11C2207/065 , G11C2207/2281
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory which can amplify data at a high speed and can prevent the occurrence of noise due to the capacitance of a bit line during amplification of the data. SOLUTION: The semiconductor memory is provided with a memory cell array which includes a number of memory cells and the bit line for transmitting the data in the memory cells, an amplifier circuit which is connected to the bit line and amplifiers the data, a switching element Q109 which is connected between the bit line and the amplifier circuit, a reference voltage source Vpp which impresses the voltage to turn on Q109 to its gate, switching elements Q139 and Q140 which are connected in series between the gate and Vpp of Q109 and are connected in parallel to each other, a reference voltage source Vss which impresses the voltage for turning on Q139 and Q140 to their gates, and a timing changing circuit which is connected between the gate and Vss of Q140 and delays the operation of Q140 from the operation of Q139. COPYRIGHT: (C)2004,JPO

10. 发明专利

JP2015019158A 半導体回路审中-公开
标题翻译：半导体电路
公开(公告)号：JP2015019158A
公开(公告)日：2015-01-29
申请号：JP2013143835
申请日：2013-07-09
申请人：株式会社東芝 , Toshiba Corp
发明人： KONO MASATOSHI , MASUDA MASAMI , ITO MIKIHIKO , KOYANAGI MASARU
IPC分类号： H03F3/343 , G11C16/06 , H03F3/45
CPC分类号： H03F3/45183 , G11C7/062 , G11C16/28 , H03F2203/45091
摘要：【課題】半導体回路の動作特性を向上する。【解決手段】本実施形態の半導体回路は、第1の入力信号Vinが入力される第1の入力部10と、第2の入力信号VREFが入力される第2の入力部11と、入力部10,11に接続され、入力信号Vin,VREFに基づいて、出力信号Voutを生成する出力生成回路30と、出力信号Voutを出力するための出力部20と、入力部10,11と出力生成回路30との接続ノードに接続される電流源190と、を含む。【選択図】図1
摘要翻译：要解决的问题：提高半导体电路的工作特性。解决方案：本实施例的半导体电路包括：第一输入部分10，输入第一输入信号Vin; 输入第二输入信号VREF的第二输入部11; 输出产生电路30，其连接到输入部分10,11，并基于输入信号Vin，VREF产生输出信号Vout; 用于输出输出信号Vout的输出部20; 以及分别连接到输入部分10,11和输出发生电路30之间的连接节点的电流源190。

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