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1. 发明专利

JP2014036115A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2014036115A
公开(公告)日：2014-02-24
申请号：JP2012176531
申请日：2012-08-08
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： MIURA YOSHINAO , NEGA RYOHEI
IPC分类号： H01L21/337 , H01L21/336 , H01L21/338 , H01L21/8232 , H01L21/8234 , H01L27/06 , H01L27/088 , H01L27/095 , H01L27/098 , H01L29/778 , H01L29/78 , H01L29/808 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To inhibit increase in the size of a semiconductor device when a pn-junction diode is formed by using a silicon layer.SOLUTION: A semiconductor device comprises: a high-concentration first conductivity type region DIFE1 provided on a substrate SUB1 and connected to an epitaxial silicon layer EPI; a second conductivity type region DIFE2 provided on the substrate SUB1 and connected to the epitaxial silicon layer EPI; a first through electrode TRE1 which pierces a channel layer CNL and which is connected to the high-concentration first conductivity type region DIFE1; and a gate electrode GE which extends in a first direction and which is arranged between the first through electrode TRE1 and a second through electrode TRE2. That is, a direction in which the frist through electrode TRE1 and the second through electrode TRE2 are arranged is orthogonal to a direction in which ON-state current of a transistor SEL flows.
摘要翻译：要解决的问题：通过使用硅层来形成pn结二极管时，抑制半导体器件的尺寸增加。解决方案：半导体器件包括：设置在衬底SUB1上的高浓度第一导电类型区域DIFE1 并连接到外延硅层EPI; 设置在基板SUB1上并连接到外延硅层EPI的第二导电类型区域DIFE2; 穿过沟道层CNL并连接到高浓度第一导电类型区域DIFE1的第一穿透电极TRE1; 以及栅极电极GE，其沿第一方向延伸并且布置在第一贯通电极TRE1和第二贯通电极TRE2之间。也就是说，通过电极TRE1和第二贯通电极TRE2排列的方向与晶体管SEL的导通状态电流流动的方向正交。

2. 发明专利

JP2014022413A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2014022413A
公开(公告)日：2014-02-03
申请号：JP2012156891
申请日：2012-07-12
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： OKAMOTO YASUHIRO , INOUE TAKASHI , NAKAYAMA TATSUO , NEGA RYOHEI , KANAZAWA MASAAKI , MIYAMOTO HIRONOBU
IPC分类号： H01L21/338 , H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/768 , H01L23/522 , H01L23/532 , H01L29/41 , H01L29/417 , H01L29/778 , H01L29/78 , H01L29/812 , H02M7/5387
CPC分类号： H01L29/452 , H01L29/2003 , H01L29/205 , H01L29/517 , H01L29/518 , H01L29/66462 , H01L29/7787 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To improve reliability of a field effect transistor using a nitride semiconductor material.SOLUTION: A semiconductor device of an embodiment has such a feature point that a plurality of unit electrodes UE1 divided to separate from each other compose an ohmic electrode OE1. With this composition, flow of on-state current in a Y-axis direction (negative direction) across the plurality of unit electrodes UE1 can be inhibited. Further, increase in current density of on-state current flowing in the Y-axis direction (negative direction) in each of the plurality of unit electrodes UE1 can be inhibited. As a result, according to the embodiment, electromigration resistance of the ohmic electrode OE1 can be improved.
摘要翻译：要解决的问题：提高使用氮化物半导体材料的场效应晶体管的可靠性。解决方案：一个实施例的半导体器件具有这样的特征：多个彼此分离的单元电极UE1组成欧姆电极OE1 。通过该构成，能够抑制跨越多个单位电极UE1的Y轴方向（负方向）的通态电流的流动。此外，可以抑制在多个单位电极UE1中的每一个中沿Y轴方向（负方向）流动的导通电流的电流密度的增加。结果，根据实施例，可以提高欧姆电极OE1的电迁移电阻。

3. 发明专利

JP2014087148A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2014087148A
公开(公告)日：2014-05-12
申请号：JP2012233481
申请日：2012-10-23
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： NEGA RYOHEI , MIURA YOSHINAO
IPC分类号： H02M3/155 , H01L25/07 , H01L25/18
CPC分类号： H02M3/158 , H01L21/8252 , H01L23/49562 , H01L23/49575 , H01L23/49844 , H01L23/49861 , H01L27/0605 , H01L27/088 , H01L27/0883 , H01L29/2003 , H01L29/205 , H01L29/41758 , H01L29/42364 , H01L29/7786 , H01L29/7787 , H01L2224/48091 , H01L2224/48247 , H01L2224/49111 , H02M1/34 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To improve power-supply efficiency while achieving simplification of a DC/DC converter circuit.SOLUTION: A semiconductor device includes a DC/DC converter circuit CC1. The DC/DC converter circuit CC1 has a normally-off transistor HT1 having a first drain electrode connected to an input terminal IT1 and a first source electrode connected to an output terminal OT1, and formed on a first compound semiconductor substrate having a two-dimentional electron gas layer; and a transistor LT1 having a second drain electrode connected to the first source electrode and a second source electrode connected to the ground.
摘要翻译：要解决的问题：提高电源效率，同时实现DC / DC转换器电路的简化。解决方案：半导体器件包括DC / DC转换器电路CC1。 DC / DC转换器电路CC1具有常闭晶体管HT1，其具有连接到输入端子IT1的第一漏电极和连接到输出端子OT1的第一源电极，并形成在具有二维电子气层; 以及具有连接到第一源电极的第二漏极和连接到地的第二源电极的晶体管LT1。

4. 发明专利

JP2015035534A 半導体装置及び半導体装置の製造方法审中-公开
标题翻译：半导体器件和半导体器件制造方法
公开(公告)号：JP2015035534A
公开(公告)日：2015-02-19
申请号：JP2013166315
申请日：2013-08-09
申请人：ルネサスエレクトロニクス株式会社 , Renesas Electronics Corp
发明人： NAKAYAMA TATSUO , KANAZAWA MASAAKI , OKAMOTO YASUHIRO , INOUE TAKASHI , MIYAMOTO HIRONOBU , NEGA RYOHEI
IPC分类号： H01L21/338 , H01L21/28 , H01L21/336 , H01L29/417 , H01L29/778 , H01L29/78 , H01L29/812
CPC分类号： H01L29/66462 , H01L29/2003 , H01L29/4236 , H01L29/42368 , H01L29/452 , H01L29/66522 , H01L29/7786 , H01L29/78
摘要：【課題】Al電極をAlGaN層にオーミック接続させる。【解決手段】半導体装置SDは、窒化物半導体層GN2、AlxGa(1−x)N層AGN(以下、AlGaN層AGNと記載)、及びAl電極DE,SEを有している。AlGaN層AGNにおいて、0
摘要翻译：要解决的问题：在Al电极和AlGaN层之间形成欧姆接触。解决方案：半导体器件SD具有氮化物半导体层GN2，AlGaN层AGN（以下称为AlGaN层AGN）和Al电极DE， SE。在AlGaN层AGN中，0

5. 发明专利

JP2014179389A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2014179389A
公开(公告)日：2014-09-25
申请号：JP2013051047
申请日：2013-03-13
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： NAKAYAMA TATSUO , MIYAMOTO HIRONOBU , OKAMOTO YASUHIRO , NEGA RYOHEI , KANAZAWA MASAAKI , INOUE TAKASHI
IPC分类号： H01L29/812 , H01L21/336 , H01L21/338 , H01L29/778 , H01L29/78 , H01S5/343
CPC分类号： H01L29/66462 , H01L29/155 , H01L29/2003 , H01L29/7787
摘要： PROBLEM TO BE SOLVED: To improve the performance of a semiconductor device.SOLUTION: For example, the density of acceptors introduced into a nitride semiconductor layer LBL constituting a part of a superlattice layer PSL is higher than the density of acceptors introduced into a nitride semiconductor layer HBL constituting the other part of the superlattice layer PSL on a condition that the superlattice layer PSL is inserted between a buffer layer BUF and an electron transit layer CH. In other words, the density of acceptors introduced to the nitride semiconductor layer LBL having a small band gap is higher than the density of acceptors introduced to the nitride semiconductor layer HBL having a large band gap.
摘要翻译：要解决的问题：提高半导体器件的性能。解决方案：例如，引入构成超晶格层PSL的一部分的氮化物半导体层LBL中的受主的密度高于引入氮化物半导体的受主的密度在超晶格层PSL插入在缓冲层BUF和电子传输层CH之间的条件下，构成超晶格层PSL的另一部分的层HBL。换句话说，导入具有小带隙的氮化物半导体层LBL的受主的密度高于导入具有大带隙的氮化物半导体层HBL的受主的密度。

6. 发明专利

JP2014175624A Semiconductor device and manufacturing method of the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2014175624A
公开(公告)日：2014-09-22
申请号：JP2013049724
申请日：2013-03-12
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： NAKAYAMA TATSUO , MIYAMOTO HIRONOBU , OKAMOTO YASUHIRO , INOUE TAKASHI , NEGA RYOHEI , KANAZAWA MASAAKI
IPC分类号： H01L29/812 , H01L21/28 , H01L21/336 , H01L21/338 , H01L29/417 , H01L29/778 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To inhibit increase in contact resistance between a nitride semiconductor layer and an ohmic electrode based on aluminum.SOLUTION: A semiconductor device comprises: an ohmic electrode OE formed on an electron supply layer ES composed of an AlGaN layer; and a wiring layer WL which is formed on the ohmic electrode OE and electrically connected with the ohmic electrode OE. The ohmic electrode OE includes an Al layer 10 whose chief component is aluminum and an AlTi layer 11 of "uniform composition" formed on the Al layer 10. On the other hand, the wiring layer WL includes a Ti layer 12A which is formed on the AlTi layer 11 of "uniform composition" and whose chief component is titanium, a TiN layer 12B formed on the Ti layer 12A and an AlSiCu layer 13 formed on the TiN layer 12B.
摘要翻译：要解决的问题：抑制氮化物半导体层和基于铝的欧姆电极之间的接触电阻的增加。解决方案：半导体器件包括：形成在由AlGaN层构成的电子供给层ES上的欧姆电极OE; 以及形成在欧姆电极OE上并与欧姆电极OE电连接的布线层WL。欧姆电极OE包括主要成分为铝的Al层10和形成在Al层10上的“均匀成分”的AlTi层11.另一方面，布线层WL包括形成在Al层10上的Ti层12A AlTi层11，其主要成分为钛，形成在Ti层12A上的TiN层12B和形成在TiN层12B上的AlSiCu层13。

7. 发明专利

JP2014135439A Semiconductor device and semiconductor device manufacturing method 审中-公开
标题翻译：半导体器件和半导体器件制造方法
公开(公告)号：JP2014135439A
公开(公告)日：2014-07-24
申请号：JP2013003630
申请日：2013-01-11
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： INOUE TAKASHI , MIYAMOTO HIRONOBU , NEGA RYOHEI , NAKAYAMA TATSUO , OKAMOTO YASUHIRO
IPC分类号： H01L29/812 , H01L21/28 , H01L21/336 , H01L21/338 , H01L29/423 , H01L29/49 , H01L29/778 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To improve characteristics of a high-electron-mobility transistor.SOLUTION: A high-electron-mobility transistor comprises: a laminate having an electron transit layer and an electron supply layer and having a source region, a drain region and an opposite region to the source region and the drain region; and a gate electrode 109 having a main gate part EM which is formed on the source electrode, the drain electrode and the opposite region and a gate extension part E1 drawn from the opposite region. In the high-electron-mobility transistor, the gate extension part E1 is arranged in a groove 121 formed in the laminate and the high-electron-mobility transistor comprises a separation part SP provided between a side wall of the gate extension part E1 and a side wall of the groove 121. The separation part SP cuts off a leak path and can reduce a leakage current. Especially, even when ion implantation for forming an element isolation region is performed after a formation process of the source electrode, the drain electrode and the gate electrode 109, the leak path is cut off by providing the separation part SP.
摘要翻译：要解决的问题：提高高电子迁移率晶体管的特性。解决方案：高电子迁移率晶体管包括：具有电子转移层和电子供应层的层压体，具有源极区，漏极区和与源极区域和漏极区域相反的区域; 以及栅极电极109，其具有形成在源极电极，漏极电极和相对区域上的主栅极部分EM和从相对区域拉出的栅极延伸部分E1。在高电子迁移率晶体管中，栅极延伸部分E1布置在形成在层叠体中的沟槽121中，高电子迁移率晶体管包括设置在栅延伸部分E1的侧壁和分离部分SP切断泄漏路径并且可以减少泄漏电流。特别是，即使在源电极，漏电极和栅电极109的形成处理之后进行用于形成元件隔离区域的离子注入，通过设置分离部分SP来切断泄漏路径。

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