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    • 2. 发明专利
    • 半導体記憶装置及び半導体記憶装置の制御方法
    • 半导体存储器件和控制半导体存储器件的方法
    • JP2014199698A
    • 2014-10-23
    • JP2013074622
    • 2013-03-29
    • シャープ株式会社Sharp Corpマイクロンメモリジャパン株式会社Micron Technology Japan Inc
    • NAGURA MITSURUNAKANO TAKASHIISHIHARA KAZUYAAWAYA NOBUYOSHIKINO YUSUKEHATTORI YASUKO
    • G11C13/00
    • 【課題】高速動作が可能な半導体記憶装置を提供する。【解決手段】半導体記憶装置1は、メモリセルアレイを複数に分割して成るブロックB1〜B4と、メモリセルが備える可変抵抗素子を低抵抗化させるセット動作と、メモリセルが備える可変抵抗素子を高抵抗化させるリセット動作と、をブロックB1〜B4毎に独立して実行する動作実行回路D1〜D4と、動作実行回路D1〜D4によるセット動作及びリセット動作の実行を制御する制御回路21と、を備える。制御回路21は、セット動作が実行されるブロック以外のブロックから、不要なデータを記憶しているメモリセルから成る不要データ領域を検出し、セット動作と並行して当該不要データ領域を成すメモリセルの少なくとも1つにリセット動作が実行されるように、動作実行回路D1〜D4を制御する。【選択図】図3
    • 要解决的问题:提供能够进行高速操作的半导体存储器件。解决方案:半导体存储器件1包括:通过将存储单元阵列分割成多个片而构成的块B1至B4; 对于每个块独立地执行用于降低包括在存储单元中的可变电阻元件的电阻的设置操作和用于增加包含在存储单元中的可变电阻元件的电阻的复位操作的操作执行电路D1至D4 B1至B4; 以及控制电路21,其控制由操作执行电路D1至D4执行设定操作和复位操作。 控制电路21控制操作执行电路D1至D4,以检测由存储单元构成的不必要的数据区,该存储单元从执行设置操作的块以外的块存储不必要的数据,并且执行至少一个 存储单元与所设置的操作并行地构成不必要的数据区域。
    • 3. 发明专利
    • Semiconductor memory device and method for rewriting of memory cell
    • 半导体存储器件和记忆单元的擦除方法
    • JP2012185890A
    • 2012-09-27
    • JP2011049111
    • 2011-03-07
    • Sharp Corpシャープ株式会社
    • KAWABATA MASARUSHIBUYA TAKAHIROTABUCHI YOSHIAKIISHIHARA KAZUYAAWAYA NOBUYOSHI
    • G11C13/00
    • G11C13/0002G11C13/0069G11C2013/0083
    • PROBLEM TO BE SOLVED: To realize a reliable semiconductor memory device in which a burden on a variable resistive element is reduced, and a method for rewriting of memory cell.SOLUTION: When conducting rewriting (set operation) for shifting a resistance state of a variable resistive element from a high resistance state to a low resistance state, a discharge current applied to the variable resistive element as part of set current is reduced by connecting a parallel resistance circuit 121 so as to be in parallel with a series circuit of a variable resistive element 105 and a cell transistor 106, and by discharging at least part of electric charge, which is stored in parasitic capacitance of the variable resistive element in association with application of set voltage, through the parallel resistance circuit. This reduces the set current and prevents a resistance value of the variable resistive element from becoming too low.
    • 要解决的问题:实现可变电阻元件的负担减小的可靠的半导体存储器件以及用于重写存储单元的方法。 解决方案:当将可变电阻元件的电阻状态从高电阻状态转换为低电阻状态进行重写(设置操作)时,作为设定电流的一部分施加到可变电阻元件的放电电流被减少 将并联电阻电路121与可变电阻元件105和单元晶体管106的串联电路并联,并且将存储在可变电阻元件的寄生电容中的至少一部分电荷放电 与设定电压的关联,通过并联电阻电路。 这减小了设定电流并且防止可变电阻元件的电阻值变得太低。 版权所有(C)2012,JPO&INPIT
    • 4. 发明专利
    • Non-volatile semiconductor memory device and manufacturing method of the same
    • 非挥发性半导体存储器件及其制造方法
    • JP2012060072A
    • 2012-03-22
    • JP2010204586
    • 2010-09-13
    • Sharp Corpシャープ株式会社
    • SHIBUYA TAKAHIROKAWABATA MASARUAWAYA NOBUYOSHIONISHI JUNYA
    • H01L27/10H01L45/00H01L49/00
    • PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory device including a variable resistive element which reduces the variation in the resistance values among elements, restrains read-out disturbance in a high-resistance state, and performs stable switching operation at high speed.SOLUTION: A first electrode is achieved by a bit line BL. A second electrode 26 is constituted by a conductive material of which work function is smaller than the first electrode, has a bottom to contact the upper surface of a relay wiring 67, and comprises a cylindrical region projecting vertically upward so as to penetrate a first interlayer insulation film 21, the first electrode (bit line BL), and a second interlayer insulation film 22. A variable resistive element 25 is formed to project vertically upward so as to contact an outer side face of the second electrode 26 to be connected with the upper surface of the relay wiring 67 with a first buffer layer 23 of metal oxide formed on the underlayer of the bottom and to be connected with the first electrode (bit line BL) in the horizontal direction through a second buffer layer 24 of metal oxide formed on the height position of the first electrode (bit line BL).
    • 解决的问题:提供一种包括可变电阻元件的非易失性半导体存储器件,其减少元件之间的电阻值的变化,抑制高电阻状态下的读出干扰,并且执行稳定的开关操作 高速 解决方案:通过位线BL实现第一电极。 第二电极26由功函数小于第一电极的导电材料构成,具有与中继布线67的上表面接触的底部,并且包括垂直向上突出的圆柱形区域,以穿透第一中间层 绝缘膜21,第一电极(位线BL)和第二层间绝缘膜22.可变电阻元件25形成为垂直向上突出以与第二电极26的外侧面接触,以与第 中继配线67的上表面具有金属氧化物的第一缓冲层23,其形成在底部的底层上并且通过形成的金属氧化物的第二缓冲层24在水平方向上与第一电极(位线BL)连接 在第一电极(位线BL)的高度位置上。 版权所有(C)2012,JPO&INPIT
    • 5. 发明专利
    • Semiconductor storage element using nonvolatile variable-resistance element
    • 使用非易失性电阻元件的半导体存储元件
    • JP2011023645A
    • 2011-02-03
    • JP2009168839
    • 2009-07-17
    • Sharp Corpシャープ株式会社
    • AWAYA NOBUYOSHITAMAI YUKIO
    • H01L27/10H01L45/00H01L49/00
    • PROBLEM TO BE SOLVED: To provide a large-capacity and inexpensive memory cell array of a nonvolatile variable-resistance element excelling in current controllability.
      SOLUTION: In a nonvolatile variable-resistance element equipped with: a first electrode 11; a second electrode 12; and a variable resistor 15 connected directly to the first electrode and directly or indirectly to the second electrode, a metal oxide having a site with oxygen missed and taking a stable structure in both a first condition where at least one electron is trapped in the site with oxygen missed and a second condition without trapping an electron is used as a variable resistor material. By interposing a tunnel insulation film 16 between the variable resistor and the second electrode, current flowing from the second electrode to the variable resistor is limited, and the nonvolatile variable-resistance element is provided with a function of a nonlinear element.
      COPYRIGHT: (C)2011,JPO&INPIT
    • 要解决的问题:提供具有优异的电流可控性的非易失性可变电阻元件的大容量且廉价的存储单元阵列。 解决方案:在具有第一电极11的非易失性可变电阻元件中, 第二电极12; 以及与第一电极直接或间接地连接到第二电极的可变电阻器15,具有氧缺失的位置的金属氧化物在第一状态和第二状态下都具有稳定的结构,其中至少一个电子被捕获在该位置, 氧缺失,而不捕获电子的第二条件被用作可变电阻材料。 通过在可变电阻器和第二电极之间插入隧道绝缘膜16,限制了从第二电极流向可变电阻器的电流,并且非易失性可变电阻元件具有非线性元件的功能。 版权所有(C)2011,JPO&INPIT
    • 6. 发明专利
    • Semiconductor memory device using nonvolatile variable resistance element, and method for manufacturing the same
    • 使用非易失性可变电阻元件的半导体存储器件及其制造方法
    • JP2010205853A
    • 2010-09-16
    • JP2009048524
    • 2009-03-02
    • Sharp Corpシャープ株式会社
    • TABUCHI YOSHIAKIHOSOI YASUNARIAWAYA NOBUYOSHI
    • H01L27/10G11C13/00H01L45/00H01L49/00
    • PROBLEM TO BE SOLVED: To achieve a memory cell array of nonvolatile variable resistance elements that respectively suppress a sneak current, achieve a reduction in cell area, and are easily manufacturable. SOLUTION: A nonvolatile semiconductor memory device is configured as follows. A three-terminal type nonvolatile variable resistance element includes: a first electrode 12; a second electrode 14; a variable resistor 13 electrically connected with both of the first/second electrodes; and a control electrode 16 facing the variable resistor 13 via a dielectric layer 15. One memory cell is composed by using the three-terminal type nonvolatile variable resistance element. A plurality of the memory cells are respectively arranged in row and column directions in a matrix form. In one memory cell and the other memory cell that are adjacent to each other in the column direction, the first electrode of the one memory cell and the second electrode of the other memory cell are electrically connected to each other so as to connect the plurality of memory cells in series in the column direction, thereby constituting a column memory cell. Both ends of the column memory cell are connected to a bit line while the control electrode of the memory cell is connected to a word line extending in the row direction. COPYRIGHT: (C)2010,JPO&INPIT
    • 要解决的问题:为了实现分别抑制潜行电流的非易失性可变电阻元件的存储单元阵列,实现单元面积的减小,并且易于制造。 解决方案:非易失性半导体存储器件如下构成。 三端型易失性可变电阻元件包括:第一电极12; 第二电极14; 与第一/第二电极电连接的可变电阻器13; 以及通过电介质层15面对可变电阻器13的控制电极16.通过使用三端子型非易失性可变电阻元件来构成一个存储单元。 多个存储单元分别以矩阵形式排列成行和列方向。 在列方向上彼此相邻的一个存储单元和另一个存储单元中,一个存储单元的第一电极和另一个存储单元的第二电极彼此电连接,以便将多个 存储单元在列方向上串联,从而构成列存储单元。 列存储单元的两端连接到位线,同时存储单元的控制电极连接到在行方向上延伸的字线。 版权所有(C)2010,JPO&INPIT
    • 8. 发明专利
    • Variable resistance element, and manufacturing method thereof
    • 可变电阻元件及其制造方法
    • JP2009043850A
    • 2009-02-26
    • JP2007205802
    • 2007-08-07
    • Sharp Corpシャープ株式会社
    • SHIBUYA TAKAHIROONISHI TETSUYAAWAYA NOBUYOSHI
    • H01L27/10H01L45/00H01L49/00
    • PROBLEM TO BE SOLVED: To provide a variable resistance element in which the area of an electrically contributing region of a variable resistance element is made smaller, and to provide a manufacturing method thereof. SOLUTION: The variable resistance element includes: a first electrode which is in a plate shape parallel to a substrate surface of a semiconductor substrate 10 and has a first opening portion in a first direction perpendicular to the substrate surface; an annular variable resistance element 13 whose outer side surface comes in contact with an inner wall surface of the first opening portion of the first electrode 11; a first interlayer insulating film 14 which has a second opening portion penetrating the film 14 in the first direction on the first opening portion formed on the first electrode; an annular second interlayer insulating film 15 formed in a side wall shape on the variable resistance element whose outer side surface comes in contact with an inner wall surface of the second opening portion of the first interlayer insulating film 14; and a second electrode 12 formed in contact with a top surface of the first interlayer insulating film 14, an inner side surface of the second interlayer insulating film 15, and an inner side surface of the variable resistance element 13. COPYRIGHT: (C)2009,JPO&INPIT
    • 要解决的问题:提供一种可变电阻元件,其中使可变电阻元件的电区域的面积更小,并提供其制造方法。 解决方案:可变电阻元件包括:第一电极,其平板于半导体衬底10的衬底表面并具有垂直于衬底表面的第一方向上的第一开口部分; 环形可变电阻元件13,其外侧表面与第一电极11的第一开口部分的内壁表面接触; 第一层间绝缘膜14,其具有在形成于第一电极上的第一开口部上沿第一方向贯穿膜14的第二开口部; 在外侧表面与第一层间绝缘膜14的第二开口部分的内壁表面接触的可变电阻元件上形成为侧壁形状的环形第二层间绝缘膜15; 以及与第一层间绝缘膜14的顶表面,第二层间绝缘膜15的内侧表面和可变电阻元件13的内侧表面接触形成的第二电极12。 C)2009年,JPO&INPIT
    • 9. 发明专利
    • Method for driving variable resistor element and storage device
    • 用于驱动可变电阻元件和存储器件的方法
    • JP2006019444A
    • 2006-01-19
    • JP2004194799
    • 2004-06-30
    • Sharp Corpシャープ株式会社
    • HOSOI YASUNARITAMAI YUKIOISHIHARA KAZUYAKOBAYASHI SHINJIAWAYA NOBUYOSHI
    • H01L27/105G11C13/00
    • G11C29/50G11C13/0007G11C13/0069G11C29/50008G11C2013/009G11C2213/31
    • PROBLEM TO BE SOLVED: To provide a method of driving a variable resistor element including a perovskite oxide with electric resistance varying by applying voltage pulses, capable of stably keeping reversible resistance variation operations. SOLUTION: The variable resistor element is formed by providing the perovskite oxide 2 between a first electrode 1 and a second electrode 3. The element has resistance history characteristics that the electric resistance between the first electrode 1 and the second electrode 3 varies by applying voltage pulses with constant polarity between the first and second electrodes 1 and 3, and further the rate of change in the resistance value changes from positive to negative for an increase in accumulated pulse applied time during the application of the voltage pulses. The voltage pulses are applied to the variable resistor element so that the accumulated pulse applied time does not exceed the specific accumulated pulse applied time when the rate of change in the resistance value for the increase in the accumulated pulse applied time changes from positive to negative in the resistance history characteristics. COPYRIGHT: (C)2006,JPO&NCIPI
    • 解决的问题:提供一种驱动包括钙电位氧化物的可变电阻元件的方法,其中电阻通过施加电压脉冲而变化,能够稳定地保持可逆电阻变化操作。 解决方案:可变电阻器元件通过在第一电极1和第二电极3之间提供钙钛矿氧化物2而形成。元件具有电阻历史特性,即第一电极1和第二电极3之间的电阻变化 在第一和第二电极1和3之间施加具有恒定极性的电压脉冲,并且进一步地,在施加电压脉冲期间累积脉冲施加时间的增加,电阻值的变化率从正变化到负。 电压脉冲被施加到可变电阻元件,使得当累积脉冲施加时间的增加的电阻值的变化率从正向变化到负时,累积脉冲施加时间不超过特定累积脉冲施加时间 电阻历史特征。 版权所有(C)2006,JPO&NCIPI