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1. 发明专利

JP2012204553A Semiconductor device manufacturing method and semiconductor device mounting structure manufacturing method 审中-公开
标题翻译：半导体器件制造方法和半导体器件安装结构制造方法
公开(公告)号：JP2012204553A
公开(公告)日：2012-10-22
申请号：JP2011066885
申请日：2011-03-25
申请人： Teramikros Inc , 株式会社テラミクロス
发明人： ARAI KAZUYOSHI
IPC分类号： H01L23/12 , H01L21/60
CPC分类号： H01L2224/11 , H01L2924/07802 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To improve a lifetime of a bump by inhibiting bump fatigue.SOLUTION: A method comprises forming recesses 25b on a surface side of an encapsulation layer 25 of a semiconductor wafer 111 on which the encapsulation layer 25 is provided above one surface, and filling a low elastic material 26 having an elastic modulus lower than the elastic modulus of the encapsulation layer 25 in the recesses 25b to form bumps 27 above the one surface of the semiconductor wafer 111.
摘要翻译：要解决的问题：通过抑制凸起疲劳来提高凸块的寿命。解决方案：一种方法包括在半导体晶片111的封装层25的表面侧上形成凹部25b，在该半导体晶片111的一个表面上设置有封装层25，并填充弹性模量低于封装层25在凹部25b中的弹性模量，以在半导体晶片111的一个表面上方形成凸块27.版权所有：（C）2013，JPO＆INPIT

2. 发明专利

JP2012186403A Semiconductor device manufacturing method 审中-公开
标题翻译：半导体器件制造方法
公开(公告)号：JP2012186403A
公开(公告)日：2012-09-27
申请号：JP2011049851
申请日：2011-03-08
申请人： Teramikros Inc , 株式会社テラミクロス
发明人： SHIODA JUNJI
IPC分类号： H01L21/56 , H01L23/12
CPC分类号： H01L2224/11
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which can inhibit a dent from being formed on a surface of an encapsulation layer in a package.SOLUTION: In a semiconductor device manufacturing process, after forming an encapsulation film 17-1 in a temporary cured state by performing a series of processes including coating of a liquid encapsulation material 33 on a semiconductor wafer 21, defoaming and calcination, a series of processes including coating of the liquid encapsulation material 33, defoaming and final baking is performed again, and an encapsulation layer 17 forming an integrated layer without a borderline, which includes the encapsulation film 17-1 in the temporary cured state and an encapsulation film 17-2 composed of the encapsulation material 33 coated thereafter is formed. Accordingly, the encapsulation layer 17 having a uniform film thickness and a flat surface condition is formed.
摘要翻译：要解决的问题：提供一种能够抑制在封装中的封装层的表面上形成凹陷的半导体器件制造方法。解决方案：在半导体器件制造工艺中，在通过执行包括在半导体晶片21上涂覆液体封装材料33的一系列工艺，消泡和煅烧之后，在临时固化状态下形成封装膜17-1之后，再次进行包括液体包封材料33的涂布，消泡和最终烘烤的一系列处理，形成没有边界线的一体化层的封装层17，其包括处于临时固化状态的封装膜17-1和封装膜形成由其后涂覆的封装材料33构成的17-2。因此，形成具有均匀膜厚和平坦表面状态的封装层17。版权所有（C）2012，JPO＆INPIT

3. 发明专利

JP2012174950A Semiconductor device and manufacturing method of the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012174950A
公开(公告)日：2012-09-10
申请号：JP2011036626
申请日：2011-02-23
申请人： Teramikros Inc , 株式会社テラミクロス
发明人： KAWAMURA MASAO
IPC分类号： H01L23/12
CPC分类号： H01L2224/16
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device including a semiconductor structure called SOI, which is less likely to be restricted in circuit design to set a lower surface of a semiconductor substrate of the semiconductor structure to ground potential.SOLUTION: A semiconductor device comprises a multilayer printed board 12 and a semiconductor structure 31 called SOI mounted in a recess 15 provided on the side of a lower surface of the multilayer printed board 12 in a face-up manner. Further, the semiconductor structure 31 is mounted on a printed wiring board 1 by connection of a center part of a lower surface of a semiconductor substrate 33 with ground wiring 3 of the printed wiring board 1 via a conductive adhesive layer 43 arranged below the lower surface of the semiconductor substrate 33. In this case, it is almost unnecessary to regard a routing line for ground. Accordingly, it becomes possible to cause the semiconductor device to be less likely to be restricted in circuit design to set the lower surface of the semiconductor substrate 33 of the semiconductor structure 31 to ground potential.
摘要翻译：要解决的问题：提供一种包括称为SOI的半导体结构的半导体器件，其不太可能限制电路设计以将半导体结构的半导体衬底的下表面设置为接地电位。解决方案：半导体器件包括多层印刷电路板12和称为SOI的半导体结构31，其被安装在设置在多层印刷电路板12的下表面侧面上的凹部15中。此外，半导体结构31通过半导体衬底33的下表面的中心部分与印刷电路板1的接地布线3之间的连接，安装在印刷电路板1上，导电粘合层43布置在下表面在这种情况下，几乎不需要考虑用于地面的路线。因此，可以使半导体器件不太可能受到电路设计的限制，以将半导体结构31的半导体衬底33的下表面设置为接地电位。版权所有（C）2012，JPO＆INPIT

4. 发明专利

JP2012074581A Semiconductor device and method for manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012074581A
公开(公告)日：2012-04-12
申请号：JP2010218973
申请日：2010-09-29
申请人： Teramikros Inc , 株式会社テラミクロス
发明人： KANEKO NORIHIKO
IPC分类号： H01L23/12 , H01L21/3205 , H01L23/52
CPC分类号： H01L24/97 , H01L24/82 , H01L2224/12105 , H01L2224/24 , H01L2224/32225 , H01L2224/73267 , H01L2224/97 , H01L2924/14 , H01L2224/83 , H01L2224/82 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To shorten the time required to form through holes without weakening the strength of a laser beam.SOLUTION: A semiconductor die 1 includes a semiconductor substrate 11, electric wiring 23 provided on the semiconductor substrate 11, and laser beam protection electrodes 27 provided on the electric wiring 23. A semiconductor device 40 includes the semiconductor die 1, a sealing layer 43 covering the semiconductor die 1 and having through holes 43a provided at a portion corresponding to the laser beam protection electrodes 27, and conductors 44 provided in the through holes 43a of the sealing layer 43. An upper surface of each laser beam protection electrode 27 has a first region 27d which contacts with the conductor 44 and a second region 27c which does not contact with the conductor 44.
摘要翻译：要解决的问题：缩短形成通孔所需的时间，而不会削弱激光束的强度。解决方案：半导体管芯1包括半导体衬底11，设置在半导体衬底11上的电线23和设置在电线23上的激光束保护电极27.半导体器件40包括半导体管芯1，密封层43覆盖半导体管芯1，并且具有设置在与激光束保护电极27相对应的部分的通孔43a，以及设置在密封层43的通孔43a中的导体44.每个激光束保护电极27的上表面具有与导体44接触的第一区域27d和不与导体44接触的第二区域27c。版权所有（C）2012，JPO＆INPIT

5. 发明专利

JP2013026438A Semiconductor device built-in substrate module and method of manufacturing the same 审中-公开
标题翻译：半导体器件内置衬底模块及其制造方法
公开(公告)号：JP2013026438A
公开(公告)日：2013-02-04
申请号：JP2011159826
申请日：2011-07-21
申请人： Teramikros Inc , 株式会社テラミクロス
发明人： WAKIZAKA SHINJI
IPC分类号： H01L23/12 , H01L25/10 , H01L25/18
CPC分类号： H01L24/97 , H01L2223/6677 , H01L2224/12105 , H01L2224/19 , H01L2224/24 , H01L2224/24137 , H01L2224/73267 , H01L2224/94 , H01L2224/97 , H01L2924/3025 , H01L2224/82 , H01L2224/83 , H01L2224/03 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device built-in substrate module, along with its manufacturing method, for higher integration and smaller size of a semiconductor device equipped with a specific function, and for simpler and more efficient manufacturing process related to component mounting, capable of realizing a good circuit characteristic.SOLUTION: In a semiconductor device built-in substrate module 10, a substrate device part 20 which incorporates a semiconductor device 30 having a wafer level CSP structure and a coil part 50 which is a functional part having a desired function are integrally formed on a core substrate 21. A terminal part 52 of a coil pattern 51 of the coil part 50 is electrically connected to a post-like electrode 36 of the semiconductor device 30 by way of a through electrode 23 provided at such position as face each other across the semiconductor device 30.
摘要翻译：要解决的问题：提供一种半导体器件内置基板模块及其制造方法，用于具有特定功能的半导体器件的更高集成度和更小尺寸，以及更简单和更有效的制造工艺相关能够实现良好的电路特性。解决方案：在半导体器件内置衬底模块10中，集成有具有晶片级CSP结构的半导体器件30和具有期望功能的功能部件的线圈部分50的衬底器件部件20 线圈部分50的线圈图形51的端子部分52通过设置在彼此面对的位置处的通孔23电连接到半导体器件30的柱状电极36 跨越半导体器件30.版权所有（C）2013，JPO＆INPIT

6. 发明专利

JP2012204557A Semiconductor device, manufacturing method of the same, and mounting structure of semiconductor device 审中-公开
标题翻译：半导体器件及其制造方法以及半导体器件的安装结构
公开(公告)号：JP2012204557A
公开(公告)日：2012-10-22
申请号：JP2011066969
申请日：2011-03-25
申请人： Teramikros Inc , 株式会社テラミクロス
发明人： WAKIZAKA SHINJI
IPC分类号： H01L23/12 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L2224/16
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which prevents its plane size from becoming larger than a semiconductor substrate when electrodes for external connection are provided on both surface sides of the semiconductor device where the electrodes for the external connection and a sealing layer covering the electrodes for the external connection are provided, and to provide a manufacturing method of the semiconductor device and a structure for mounting the semiconductor device to a circuit board.SOLUTION: In a semiconductor device 10, connection pads 12a, 12b, connected with each other through a through electrode 12c, are provided on an upper surface 11a and a lower surface 11b of a silicon substrate 11. Further, wiring 15a, 15b respectively connecting with the connection pads 12a, 12b and columnar electrodes for external connection 16a, 16b are respectively provided on the upper surface side and the lower surface side of the silicon substrate 11. Furthermore, sealing layers 17a, 17b are respectively provided so as to cover peripheral side parts of the electrodes for the external connection 16a, 16b and expose end parts of the electrodes for the external connection 16a, 16b.
摘要翻译：要解决的问题：提供一种半导体器件，当半导体器件的外部连接用电极和密封件的两面设置有用于外部连接的电极时，防止其平面尺寸变得大于半导体衬底提供覆盖用于外部连接的电极的层，并且提供半导体器件的制造方法和用于将半导体器件安装到电路板的结构。解决方案：在半导体器件10中，通过贯通电极12c彼此连接的连接焊盘12a，12b设置在硅基板11的上表面11a和下表面11b上。此外，布线15a， 15b分别设置在与硅衬底11的上表面侧和下表面侧连接的连接焊盘12a，12b和用于外部连接的柱状电极16a，16b。此外，密封层17a，17b分别设置为以覆盖用于外部连接16a，16b的电极的周边侧部分，并暴露用于外部连接16a，16b的电极的端部。版权所有（C）2013，JPO＆INPIT

7. 发明专利

JP2012178405A Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012178405A
公开(公告)日：2012-09-13
申请号：JP2011039675
申请日：2011-02-25
申请人： Teramikros Inc , 株式会社テラミクロス
发明人： KIDO TOSHIHIRO
IPC分类号： H01L23/12 , H01L21/60 , H05K1/18 , H05K3/46
CPC分类号： H01L2224/16225 , H01L2924/15153 , H01L2924/1533 , H01L2924/19105
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device with which a semiconductor component is disposed within a semiconductor component recess provided on an upper surface side of a cavity, and which can be reduced in thickness.SOLUTION: Inside a semiconductor component recess 4 which is provided on an upper surface side of a cavity 1, a semiconductor component 11 is disposed in a face-down manner. Inside the semiconductor component recess 4, an insulating layer 35 is provided so as to cover the semiconductor component 11. An upper surface of the insulating layer 35 becomes flush with an upper surface of an upper overcoat film 33 provided on the upper surface of the cavity 1. Upper layer wiring 37 is provided on the upper surfaces of the insulating layer 35 and the upper overcoat film 33. In such a case, no upper insulating film is provided on the cavity 1 and the semiconductor component 11, thereby making a semiconductor device thin for the upper insulating film.
摘要翻译：要解决的问题：提供一种半导体器件，半导体元件设置在设置在空腔的上表面侧的半导体元件凹部内，并且可以减小厚度。解决方案：在设置在空腔1的上表面侧的半导体部件凹部4的内部，以面朝下的方式设置半导体部件11。在半导体部件凹部4内部，设置绝缘层35以覆盖半导体部件11.绝缘层35的上表面与设置在空腔的上表面上的上覆盖膜33的上表面齐平上层布线37设置在绝缘层35和上覆盖膜33的上表面上。在这种情况下，在空腔1和半导体部件11上不设置上绝缘膜，从而制成半导体器件上绝缘膜薄。版权所有（C）2012，JPO＆INPIT

8. 发明专利

JP2012143849A Method and apparatus for chamfering 审中-公开
标题翻译：用于切割的方法和装置
公开(公告)号：JP2012143849A
公开(公告)日：2012-08-02
申请号：JP2011005484
申请日：2011-01-14
申请人： Teramikros Inc , 株式会社テラミクロス
发明人： KURIHARA MITSUHIKO
IPC分类号： B24B9/00 , B24B1/00
摘要： PROBLEM TO BE SOLVED: To enable chamfering of corners of a semiconductor chip that is preliminarily divided into individual pieces.SOLUTION: A chamfering apparatus 10 includes: a rotating device 30 for rotating the semiconductor chip 11; tools 40 disposed around the rotating device 30 so as to be brought into contact with/be separated from the corners of the semiconductor chip 11; and a moving device 50 for moving the tools 40 along a radial direction with respect to the rotation axis of the rotating device 30 to bring the tools 40 into contact with the corners of the semiconductor chip 11, thereby chamfering the corners of the semiconductor chip 11.
摘要翻译：要解决的问题：为了使预先分成单独的片的半导体芯片的角部能够倒角。解决方案：倒角装置10包括：用于旋转半导体芯片11的旋转装置30; 工具40设置在旋转装置30周围，以便与半导体芯片11的角部接触/分离; 以及用于相对于旋转装置30的旋转轴线沿径向移动工具40以使工具40与半导体芯片11的角部接触从而倒角半导体芯片11的角部的移动装置50 （C）2012年，JPO＆INPIT

9. 发明专利

JP2012074538A Semiconductor device and method of manufacturing the semiconductor device 审中-公开
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：JP2012074538A
公开(公告)日：2012-04-12
申请号：JP2010218228
申请日：2010-09-29
申请人： Teramikros Inc , 株式会社テラミクロス
发明人： KURIHARA MITSUHIKO
IPC分类号： H01L21/60 , H01L23/12
CPC分类号： H01L2224/11
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of improving yield by preventing the occurrence of resist residue even if the center interval between columnar electrodes is small.SOLUTION: A semiconductor device comprises a semiconductor substrate, wiring that is provided on the semiconductor substrate and has lands, and columnar electrodes provided on the lands. The shape of the surface, contacting the land, of each columnar electrode has three or more salients 20b composed of convex curves and sides composed of concave curves 20c connecting each of the salients.

10. 发明专利

JP2012074461A Semiconductor device, and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012074461A
公开(公告)日：2012-04-12
申请号：JP2010216881
申请日：2010-09-28
申请人： Teramikros Inc , 株式会社テラミクロス
发明人： SHIODA JUNJI
IPC分类号： H01L23/12 , H01L21/3205 , H01L23/52
CPC分类号： H01L24/03 , H01L23/3114 , H01L23/3192 , H01L24/13 , H01L2224/02311 , H01L2224/02331 , H01L2224/0239 , H01L2224/024 , H01L2224/03462 , H01L2224/0362 , H01L2224/0401 , H01L2224/05569 , H01L2224/05644 , H01L2224/05647 , H01L2224/13022 , H01L2224/131 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2224/05552 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device called CSP in which the periphery of an electrode for external connection is covered with a sealing film and burrs are prevented from being produced on the top face of the electrode for external connection when grinding the top face side of the sealing film.SOLUTION: After forming electrodes 10 for external connection by electrolytic plating using a plating resist film, the upper parts of all the electrodes 10 for external connection and the top face sides of the plating resist films corresponding to them are cut and removed by using a surface planer to align the heights of the electrodes 10 for external connection. In this case, no burr is produced on the top face of the electrode 10 for external connection. The plating resist film is then peeled off to form the sealing film 11, and the top face side of the sealing film 11 is grounded so as to slightly leave the sealing film 11 (for example, a few μm-10 μm in thickness) on the electrode 10 for external connection. In this case, no burr is produced on the top face of the electrode 10 for external connection, since the upper part of the electrode 10 for external connection is not grounded. An opening part 12 is then formed by laser processing for irradiating the sealing film 11 in a section corresponding to the center part of the top face of the electrode 10 for external connection with a laser beam.
摘要翻译：要解决的问题：提供一种称为CSP的半导体器件，其中用密封膜覆盖用于外部连接的电极的周边，并且在研磨时防止在用于外部连接的电极的顶面上产生毛刺密封膜的顶面。解决方案：通过使用电镀抗蚀剂膜通过电解电镀形成用于外部连接的电极10之后，用于外部连接的所有电极10的上部和与它们相对应的电镀抗蚀剂膜的顶面侧被切除并除去使用表面平面线来对准电极10的高度用于外部连接。在这种情况下，在用于外部连接的电极10的顶面上不产生毛刺。然后将电镀抗蚀剂膜剥离以形成密封膜11，并且密封膜11的顶面侧接地，以便稍微离开密封膜11（例如，厚度为几μm-10μm）上用于外部连接的电极10。在这种情况下，由于用于外部连接的电极10的上部没有接地，所以在用于外部连接的电极10的顶面上不产生毛刺。然后通过激光加工形成开口部分12，以在与激光束外部连接的电极10的顶面的中心部分相对应的部分中照射密封膜11。版权所有（C）2012，JPO＆INPIT

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